parent
6203117522
commit
0e4b502319
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@ -132,12 +132,12 @@ extern "C" {
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
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#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_RX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define USART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define UART1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define USART1_RX_DMA_INSTANCE DMA2_Stream2
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#define UART1_RX_DMA_INSTANCE DMA2_Stream2
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#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define USART1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#define UART1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#endif
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#endif
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/* DMA2 stream3 */
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/* DMA2 stream3 */
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@ -184,12 +184,12 @@ extern "C" {
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
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#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_TX_DMA_CHANNEL DMA_CHANNEL_3
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#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
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#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(USART1_RX_DMA_INSTANCE)
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define USART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
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#define UART1_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
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#define USART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define USART1_RX_DMA_INSTANCE DMA2_Stream5
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#define UART1_RX_DMA_INSTANCE DMA2_Stream5
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#define USART1_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define UART1_RX_DMA_CHANNEL DMA_CHANNEL_4
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#define USART1_RX_DMA_IRQ DMA2_Stream5_IRQn
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#define UART1_RX_DMA_IRQ DMA2_Stream5_IRQn
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#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream5_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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