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add:air105 bsp (#5607) 

* add:air105 bsp

* add:去掉注释代码

* add:注释修改

* fix:格式化一遍代码格式

* add:main函数添加闪灯

* add:完善bsp

* add:添加一些信息

* add:使用工作队列喂狗

* add:整理目录

* add:去掉乱码部分

* add:修改readme

* add:更新readme说明

* add:去掉bootloader.bin和soc_download.exe，README.md中添加标注

* fix:去除多余文件

* add:补充license

* add:支持scons --dist

* add:更新soc_download.exe连接地址
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打盹的消防车 2022-03-08 12:04:17 +08:00 committed by GitHub
parent 7746d288d7
commit 0e254652aa
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GPG Key ID: 4AEE18F83AFDEB23
143 changed files with 46668 additions and 0 deletions
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20
bsp/airm2m/README.md Normal file
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### 本文档为 合宙 开发团队为 airm2m bsp 提供的资料、介绍说明。
**合宙官网：https://openluat.com**
**wiki教程文档：https://wiki.luatos.com/**
**luatos仓库：https://gitee.com/openLuat/LuatOS**
**Luatos RTthread 软件包仓库：https://github.com/openLuat/luatos-soc-rtt**
**API手册：https://wiki.luatos.com/api/index.html**
**社区：https://doc.openluat.com/**
**air105仓库：https://gitee.com/openLuat/luatos-soc-air105**
**购买地址：https://luat.taobao.com/index.htm?spm=a1z10.5-c-s.w5002-24045920810.2.457f5bcdtkiPyX**
**如有问题提问请详细说明现象，提供日志以及最新复现工程,在https://gitee.com/openLuat/LuatOS/issues报问题**

666
bsp/airm2m/air105/.config Normal file
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#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40100
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_SERIAL_V1 is not set
CONFIG_RT_USING_SERIAL_V2=y
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
CONFIG_RT_USING_WDT=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_POSIX_TIMER is not set
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
#
# Network
#
# CONFIG_RT_USING_SAL is not set
# CONFIG_RT_USING_NETDEV is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_QRCODE is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# POSIX extension functions
#
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_RT_USING_ARDUINO is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_PERSIMMON is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_USB_STACK is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_RS232 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
# CONFIG_PKG_USING_CONTROLLER is not set
# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_AIR105=y
#
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_SHELL_TO_USART=y
# CONFIG_BSP_USING_SPI_FLASH is not set
# CONFIG_BSP_USING_ETH is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
CONFIG_BSP_UART0_RX_BUFSIZE=256
CONFIG_BSP_UART0_TX_BUFSIZE=0
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_I2C is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
CONFIG_BSP_USING_WDT=y

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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
source "board/Kconfig"

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# AIR105开发板 BSP 说明
## 简介
本文档为 合宙 开发团队为 AIR105开发板提供的 BSP (板级支持包) 说明。
主要内容如下：
- 开发板资源介绍
- BSP 快速上手
- 进阶使用方法
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
## 开发板介绍
AIR105 是合宙推出的一款基于 ARM Cortex-M4 内核的10mm x 10mm 大小的MCU，最高主频为 204Mhz，不仅提供UART/GPIO/I2C/ADC/SPI等基础外设，更提供DAC/USB/DCMI/HSPI等高级外设接口，内置充电功能，支持5V/3.3V供电，同时自带5v转3.3V的LDO，4M字节Flash，640K字节RAM。
开发板外观如下图所示：
![board](figures/board.png)
该开发板常用 **板载资源** 如下：
- MCU：Air105，主频 204MHz，4M FLASH ，640KB RAM
- 调试下载接口，UART0 To Type-c USB 接口
开发板更多详细信息请参考合宙Air105 [合宙Air105开发板介绍](https://wiki.luatos.com/chips/air105/board.html)。
## 外设支持
本 BSP 目前对外设的支持情况如下：
| 片上外设 | **支持情况** |
| -------- | ------------ |
| GPIO | 支持 |
| UART | 支持 |
| SPI | 支持 |
| I2C | 支持 |
| RTC | 支持 |
| WDT | 支持 |
## 使用说明
使用说明分为如下两个章节：
- 快速上手
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
- 进阶使用
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
### 快速上手
本 BSP 为开发者提供 GCC 工程，支持 GCC 开发环境。下面介绍如何将系统运行起来。
#### 硬件连接
使用数据线连接开发板到 PC。
#### 编译下载
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`。
3. 输入`scons`进行编译。
编译完成会自动打包bl : bootloader.bin和下载工具:soc_download.exe在bsp目录下生成rtthread_air105.soc，使用[Luatools](http://cdndownload.openluat.com/Luat_tool_src/last_release/Luatools_v2.exe)下载进开发板即可。
#### 运行结果
下载程序成功之后，系统会自动运行。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口（1500000-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
```bash
\ | /
- RT - Thread Operating System
/ | \ 4.1.0 build Feb 22 2022 09:53:22
2006 - 2022 Copyright by RT-Thread team
msh >
```
### 进阶使用
此 BSP 默认只开启了 GPIO 和 串口0 的功能，如果需使用更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
1. 在 bsp 下打开 env 工具。
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
3. 输入`pkgs --update`命令更新软件包。
4. 输入`scons`进行编译。
**Luatos同样也上线了RTthread 软件包，仓库：https://github.com/openLuat/luatos-soc-rtt**
## 注意事项
**bootloader.bin和soc_download.exe如不存在会自动下载，请保持网络通畅**
**烧录前请设置波特率为1500000**
**air105必须启用看门狗，默认启用**
**更多资料参考[WIKI](https://wiki.luatos.com/)**
## 联系人信息
维护人:
- [**合宙Luat**](https://gitee.com/openLuat)
- [**淘宝地址**](https://item.taobao.com/item.htm?spm=a1z10.5-c-s.w4002-24045920841.15.29395bcdUExSHR&id=666216389131)

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# for module compiling
import os
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')

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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
if rtconfig.PLATFORM == 'iar':
env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
env.Replace(ARFLAGS = [''])
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
Export('RTT_ROOT')
Export('rtconfig')
SDK_ROOT = os.path.abspath('./')
if os.path.exists(SDK_ROOT + '/libraries'):
libraries_path_prefix = SDK_ROOT + '/libraries'
else:
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
SDK_LIB = libraries_path_prefix
Export('SDK_LIB')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
# make a building
DoBuilding(TARGET, objs)

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import rtconfig
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd, str(Dir('#'))]
src = Split("""
main.c
""")
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-02-22 airm2m first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include <board.h>
#include "drv_gpio.h"
/* defined the LED2 pin: PD14 */
#define LED0_PIN GPIOD_14
/* defined the LED3 pin: PD15 */
#define LED1_PIN GPIOD_15
/* defined the LED4 pin: PC3 */
#define LED2_PIN GPIOC_03
int main(void)
{
uint32_t Speed = 200;
/* set LED2 pin mode to output */
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
/* set LED3 pin mode to output */
rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
/* set LED4 pin mode to output */
rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED0_PIN, PIN_LOW);
rt_thread_mdelay(Speed);
rt_pin_write(LED1_PIN, PIN_LOW);
rt_thread_mdelay(Speed);
rt_pin_write(LED2_PIN, PIN_LOW);
rt_thread_mdelay(Speed);
rt_pin_write(LED0_PIN, PIN_HIGH);
rt_thread_mdelay(Speed);
rt_pin_write(LED1_PIN, PIN_HIGH);
rt_thread_mdelay(Speed);
rt_pin_write(LED2_PIN, PIN_HIGH);
rt_thread_mdelay(Speed);
}
}

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menu "Hardware Drivers Config"
config SOC_AIR105
bool
select ARCH_ARM_CORTEX_M4
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select BSP_USING_WDT
default y
menu "Onboard Peripheral Drivers"
config BSP_USING_SHELL_TO_USART
bool "Enable SHELL TO USART (uart0)"
select BSP_USING_UART
select BSP_USING_UART0
default y
config BSP_USING_SPI_FLASH
bool "Enable SPI FLASH (W25Q64 spi1)"
select BSP_USING_SPI
select RT_USING_SFUD
select RT_SFUD_USING_SFDP
default n
config BSP_USING_ETH
bool "Enable Ethernet Driver"
select PKG_USING_WIZNET
select BSP_USING_SPI
default n
if BSP_USING_ETH
config EXTERNAL_PHY_ADDRESS
hex
default 0x00
config WIZ_SPI_BUS
string "WIZ SPI bus name"
default "spi2"
config WIZ_SPI_CS
int "WIZ SPI bus cs pin"
default 19
endif
endmenu
menu "On-chip Peripheral Drivers"
config BSP_USING_GPIO
bool "Enable GPIO"
select RT_USING_PIN
default y
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
menuconfig BSP_USING_UART0
bool "Enable UART0 (Debugger)"
default n
if BSP_USING_UART0
config BSP_UART0_RX_BUFSIZE
int "Set UART0 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART0_TX_BUFSIZE
int "Set UART0 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
menuconfig BSP_USING_UART1
bool "Enable UART1"
default n
if BSP_USING_UART1
config BSP_UART1_RX_BUFSIZE
int "Set UART1 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART1_TX_BUFSIZE
int "Set UART1 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 0
endif
menuconfig BSP_USING_UART2
bool "Enable UART2"
default n
if BSP_USING_UART2
config BSP_UART2_RX_BUFSIZE
int "Set UART2 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART2_TX_BUFSIZE
int "Set UART2 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 256
endif
menuconfig BSP_USING_UART3
bool "Enable UART3"
default n
if BSP_USING_UART3
config BSP_UART3_RX_BUFSIZE
int "Set UART3 RX buffer size"
range 64 65535
depends on RT_USING_SERIAL_V2
default 256
config BSP_UART3_TX_BUFSIZE
int "Set UART3 TX buffer size"
range 0 65535
depends on RT_USING_SERIAL_V2
default 256
endif
endif
config BSP_USING_I2C
bool "Enable HW I2C"
select RT_USING_I2C
default n
if BSP_USING_I2C
config I2C_BUS_NAME
string "HW I2C bus name"
default "i2c"
endif
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
select RT_USING_SPI
if BSP_USING_SPI
config BSP_USING_HSPI0
bool "Enable HSPI0 BUS"
default n
config BSP_USING_SPI0
bool "Enable SPI0 BUS"
default n
config BSP_USING_SPI1
bool "Enable SPI1 BUS"
default n
config BSP_USING_SPI2
bool "Enable SPI2 BUS"
default n
config BSP_USING_SPI0S
bool "Enable SPI0S BUS"
default n
endif
config BSP_USING_ONCHIP_RTC
bool "Enable HW onchip rtc"
select RT_USING_ONCHIP_RTC
default n
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
select RT_USING_DEVICE_IPC
select RT_USING_SYSTEM_WORKQUEUE
default n
endmenu
endmenu

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import os
import rtconfig
from building import *
Import('SDK_LIB')
cwd = GetCurrentDir()
CPPDEFINES = ['__USE_XTL__']
# add general drivers
src = Split('''
board.c
''')
if GetDepend(['BSP_USING_ETH']):
src += Glob('ports/w5500_device.c')
if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('ports/spi_flash_init.c')
if GetDepend(['BSP_USING_WDT']):
src += Glob('wdt_feed.c')
path = [cwd]
startup_path_prefix = SDK_LIB
if rtconfig.CROSS_TOOL == 'gcc':
src += [startup_path_prefix + '/HAL_Driver/Startup/gcc/startup_gcc.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += [startup_path_prefix + '/HAL_Driver/Startup/arm/startup_gcc.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [startup_path_prefix + '/HAL_Driver/Startup/iar/startup_gcc.s']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-02-22 airm2m first version
*/
#include "board.h"
uint32_t SystemCoreClock;
extern const uint32_t __isr_start_address;
const uint32_t __attribute__((section (".app_info")))
g_CAppInfo[256] =
{
__APP_START_MAGIC__,
sizeof(g_CAppInfo),
0,
0,
};
void SystemInit(void)
{
#ifdef __USE_XTL__
SYSCTRL->FREQ_SEL = 0x20000000 | SYSCTRL_FREQ_SEL_HCLK_DIV_1_2 | (1 << 13) | SYSCTRL_FREQ_SEL_CLOCK_SOURCE_EXT | SYSCTRL_FREQ_SEL_XTAL_192Mhz;
#else
SYSCTRL->FREQ_SEL = 0x20000000 | SYSCTRL_FREQ_SEL_HCLK_DIV_1_2 | (1 << 13) | SYSCTRL_FREQ_SEL_CLOCK_SOURCE_INC | SYSCTRL_FREQ_SEL_XTAL_192Mhz;
#endif
SCB->VTOR = (uint32_t)(&__isr_start_address);
SYSCTRL->CG_CTRL1 = SYSCTRL_APBPeriph_ALL;
SYSCTRL->SOFT_RST1 = SYSCTRL_APBPeriph_ALL;
SYSCTRL->PHER_CTRL &= ~(1 << 20);
SYSCTRL->SOFT_RST2 &= ~SYSCTRL_USB_RESET;
SYSCTRL->LOCK_R |= SYSCTRL_USB_RESET;
__enable_irq();
}
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
SystemCoreClock = HSE_VALUE * (((SYSCTRL->FREQ_SEL & SYSCTRL_FREQ_SEL_XTAL_Mask) >> SYSCTRL_FREQ_SEL_XTAL_Pos) + 1);
}
void rt_hw_board_init(void)
{
GPIO_Config(GPIOC_03, 0, 0);
GPIO_Config(GPIOD_14, 0, 0);
GPIO_Config(GPIOD_15, 0, 0);
__NVIC_SetPriorityGrouping(7 - __NVIC_PRIO_BITS);
SystemCoreClockUpdate();
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
rt_hw_systick_init();
DMA_GlobalInit();
Uart_GlobalInit();
DMA_TakeStream(DMA1_STREAM_1);//for qspi
CoreTick_Init();
#ifdef RT_USING_PIN
rt_hw_pin_init();
#endif
/* USART driver initialization is open by default */
#ifdef RT_USING_SERIAL
rt_hw_usart_init();
#endif
/* Set the shell console output device */
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* Board underlying hardware initialization */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
}

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-02-22 airm2m first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "app_inc.h"
#include <rtthread.h>
#include "rtconfig.h"
#ifdef __CC_ARM
extern int Image$$RW_IRAM1$$ZI$$Limit;
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
#elif __ICCARM__
#pragma section="HEAP"
#define HEAP_BEGIN (__segment_end("HEAP"))
#else
extern int __bss_end;
#define HEAP_BEGIN ((void *)&__bss_end)
#endif
#define HEAP_END (void*)(0x20000000 + 0xA0000)
void rt_hw_board_init(void);
int rt_vbus_do_init(void);
#endif

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x01000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0102FFFF;
define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM1_end__ = 0x2009FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0400;
define symbol __ICFEDIT_size_heap__ = 0x000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM1_region { readwrite, last block CSTACK };

156
bsp/airm2m/air105/board/linker_scripts/link.lds Normal file
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@ -0,0 +1,156 @@
/* Program Entry, set to mark it as "used" and avoid gc */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 640K
FLASH (rx) : ORIGIN = 0x1010000, LENGTH = 3008K
}
ENTRY(Reset_Handler)
_system_stack_size = 0x4000;
SECTIONS
{
.app_info :
{
. = ALIGN(512);
KEEP(*(.app_info))
. = ALIGN(512);
} >FLASH
.text :
{
. = ALIGN(4);
__isr_start_address = .;
_stext = .;
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
*startup_gcc.o(.text .text.*)
*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
_etext = .;
} > FLASH
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
/* This is used by the startup in order to initialize the .data secion */
_sidata = .;
} > FLASH
__exidx_end = .;
/* .data section which is used for initialized data */
.data : AT (_sidata)
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
*(.RamFunc) /* .RamFunc sections */
*(.RamFunc*) /* .RamFunc* sections */
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM
.stack :
{
. = ALIGN(4);
_sstack = .;
. = . + _system_stack_size;
. = ALIGN(4);
_estack = .;
} >RAM
__bss_start = .;
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
*(.bss.init)
} > RAM
__bss_end = .;
_end = .;
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

15
bsp/airm2m/air105/board/linker_scripts/link.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x01010000 0x002F0000 { ; load region size_region
ER_IROM1 0x01010000 0x002F0000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x000A0000 { ; RW data
.ANY (+RW +ZI)
}
}

31
bsp/airm2m/air105/board/ports/spi_flash_init.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-02-22 airm2m first version
*/
#include <rtthread.h>
#include "spi_flash.h"
#include "spi_flash_sfud.h"
#include "drv_spi.h"
#if defined(BSP_USING_SPI_FLASH)
static int rt_hw_spi_flash_init(void)
{
__HAL_RCC_GPIOA_CLK_ENABLE();
rt_hw_spi_device_attach("spi1", "spi10", GPIOA, GPIO_PIN_4);
if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi10"))
{
return -RT_ERROR;
};
return RT_EOK;
}
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init);
#endif

17
bsp/airm2m/air105/board/ports/w5500_device.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-02-22 airm2m first version
*/
#include "drv_spi.h"
#include "board.h"
int w5500_spi_device_init(void)
{
return rt_hw_spi_device_attach(WIZ_SPI_BUS,WIZ_SPI_DEVICE, WIZ_SPI_CS);
}
INIT_DEVICE_EXPORT(w5500_spi_device_init);

53
bsp/airm2m/air105/board/wdt_feed.c Normal file
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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-02-22 airm2m first version
*/
#include <rtthread.h>
#include <rtdevice.h>
static char device_name[] = "wdt";
static rt_device_t wdg_dev;
static struct rt_work wdt_feed;
static void wdt_feed_func(struct rt_work *work, void *work_data)
{
rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_KEEPALIVE, RT_NULL);
rt_work_submit(&wdt_feed, 1200);
}
static int wdt_feed_init(void)
{
rt_err_t ret = RT_EOK;
rt_uint32_t timeout = 2;
wdg_dev = rt_device_find(device_name);
if (!wdg_dev)
{
rt_kprintf("find %s failed!\n", device_name);
return RT_ERROR;
}
ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_SET_TIMEOUT, &timeout);
if (ret != RT_EOK)
{
rt_kprintf("set %s timeout failed!\n", device_name);
return RT_ERROR;
}
ret = rt_device_control(wdg_dev, RT_DEVICE_CTRL_WDT_START, RT_NULL);
if (ret != RT_EOK)
{
rt_kprintf("start %s failed!\n", device_name);
return -RT_ERROR;
}
rt_work_init(&wdt_feed, wdt_feed_func, RT_NULL);
rt_work_submit(&wdt_feed, 1200);
return RT_EOK;
}
INIT_COMPONENT_EXPORT(wdt_feed_init);

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2087
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147
bsp/airm2m/air105/libraries/HAL_Driver/Inc/air105_adc.h Normal file
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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_ADC_H__
#define __AIR105_ADC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Include ------------------------------------------------------------------*/
#include "air105.h"
#define IS_ADC_PERIPH(PERIPH) ((PERIPH) == ADC0)
#define ADC_CR1_CHANNEL_MASK ((uint32_t)0x07)
#define ADC_CR1_SAMPLE_RATE_Pos 3
#define ADC_CR1_SAMPLE_RATE_MASK (0x3 << ADC_CR1_SAMPLE_RATE_Pos)
#define ADC_CR1_SAMP_ENABLE BIT(6)
#define ADC_CR1_POWER_DOWN BIT(8)
#define ADC_CR1_IRQ_ENABLE BIT(5)
#define ADC_SR_DONE_FLAG BIT(0)
#define ADC_SR_FIFO_OV_FLAG BIT(1)
#define ADC_FIFO_OV_INT_ENABLE BIT(2)
#define ADC_FIFO_RESET BIT(1)
#define ADC_FIFO_ENABLE BIT(0)
#define ADC_CR2_BUFF_ENABLE BIT(14)
#define ADC_DIV_RESISTOR_EN_BIT BIT(13)
typedef enum
{
ADC_Overflow = 0,
ADC_NoOverflow = 1,
}ADC_OverflowTypeDef;
/* ADC Channel select */
typedef enum
{
ADC_CHANNEL_CHARGE_VBAT =0,
ADC_CHANNEL_1,
ADC_CHANNEL_2,
ADC_CHANNEL_3,
ADC_CHANNEL_4,
ADC_CHANNEL_5,
ADC_CHANNEL_6,
}ADC_ChxTypeDef;
#define IS_ADC_CHANNEL(CHANNEL_NUM) (((CHANNEL_NUM) == ADC_CHANNEL_CHARGE_VBAT) || \
((CHANNEL_NUM) == ADC_CHANNEL_1) || \
((CHANNEL_NUM) == ADC_CHANNEL_2) || \
((CHANNEL_NUM) == ADC_CHANNEL_3) || \
((CHANNEL_NUM) == ADC_CHANNEL_4) || \
((CHANNEL_NUM) == ADC_CHANNEL_5) || \
((CHANNEL_NUM) == ADC_CHANNEL_6))
/* ADC Samp Select */
typedef enum
{
ADC_SpeedPrescaler_None = 0,
ADC_SpeedPrescaler_2,
ADC_SpeedPrescaler_4,
ADC_SpeedPrescaler_8,
}ADC_SampTypeDef;
#define IS_ADC_SAMP(SAMP) (((SAMP) == ADC_SpeedPrescaler_None) || \
((SAMP) == ADC_SpeedPrescaler_2) || \
((SAMP) == ADC_SpeedPrescaler_4) || \
((SAMP) == ADC_SpeedPrescaler_8))
typedef struct _ADC_InitTypeDef
{
ADC_ChxTypeDef ADC_Channel; /* ADC Channel select */
ADC_SampTypeDef ADC_SampSpeed; /* ADC sampspeed select */
FunctionalState ADC_IRQ_EN; /* ADC IRQ/Polling Select */
FunctionalState ADC_FIFO_EN; /* ADC FIFO Enable Select */
} ADC_InitTypeDef;
/* Exported constants -------------------------------------------------------*/
/* Exported macro -----------------------------------------------------------*/
/* Exported functions -------------------------------------------------------*/
void ADC_Init(ADC_InitTypeDef *ADC_InitStruct);
void ADC_StartCmd(FunctionalState NewState);
void ADC_FIFODeepth(uint32_t FIFO_Deepth);
void ADC_FIFOReset(void);
void ADC_ITCmd(FunctionalState NewState);
void ADC_FIFOOverflowITcmd(FunctionalState NewState);
void ADC_BuffCmd(FunctionalState NewState);
void ADC_DivResistorCmd(FunctionalState NewState);
int32_t ADC_GetFIFOCount(void);
int32_t ADC_GetResult(void);
int32_t ADC_GetFIFOResult(uint16_t *ADCdata, uint32_t len);
uint32_t ADC_CalVoltage(uint32_t u32ADC_Value, uint32_t u32ADC_Ref_Value);
ADC_ChxTypeDef ADC_GetChannel(void);
FunctionalState ADC_IsDivResistorEnable(void);
ADC_OverflowTypeDef ADC_IsFIFOOverflow(void);
void ADC_ChannelSwitch(ADC_ChxTypeDef Channelx);
/* Exported variables -------------------------------------------------------*/
/* Exported types -----------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif /* __AIR105_ADC_H__ */

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_BPK_H
#define __AIR105_BPK_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/** @defgroup BPK_Exported_Types
* @{
*/
#define BPK_KEY_REGION_0 ((uint32_t)0x0001)
#define BPK_KEY_REGION_1 ((uint32_t)0x0002)
#define BPK_KEY_REGION_ALL ((uint32_t)0x0003)
#define IS_BPK_KEY_REGION(REGION) ((((REGION) & ~BPK_KEY_REGION_ALL) == 0x00) && ((REGION) != 0x00))
#define IS_BPK_LOCK(LOCK) ((((LOCK) & ~BPK_LR_LOCK_ALL) == 0x00) && ((LOCK) != (uint32_t)0x00))
FlagStatus BPK_IsReady(void);
ErrorStatus BPK_WriteKey(uint32_t *Key,uint32_t Key_Len, uint32_t Key_Offset);
ErrorStatus BPK_ReadKey(uint32_t *Key,uint32_t Key_Len, uint32_t Key_Offset);
void BPK_KeyWriteLock(uint16_t BPK_KEY_Region, FunctionalState NewState);
void BPK_KeyReadLock(uint16_t BPK_KEY_Region, FunctionalState NewState);
void BPK_KeyClear(uint16_t BPK_KEY_Region);
void BPK_SetScramber(uint32_t Scram);
void BPK_Lock(uint32_t BPK_LOCK, FunctionalState NewState);
void BPK_LockSelf(void);
FlagStatus BPK_GetLockStatus(uint32_t BPK_LOCK);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

114
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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_CACHE_H
#define __AIR105_CACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
#define CACHE_REFRESH ((uint32_t)0x80000000)
#define CACHE_REFRESH_ALLTAG ((uint32_t)0x40000000)
#define CACHE_KEY_GEN_START ((uint32_t)0x80000000)
#define CACHE_IS_BUSY ((uint32_t)0x20000000)
#define CACHE_SIZE ((uint32_t)0x8000)
#define CACHE_PARTICLE_SIZE (0x20)
#define CACHE_ADDRESS_START ((uint32_t)0x01000000)
#define CACHE_ADDRESS_MAX ((uint32_t)0x00FFFFFF)
#define IS_CACHE_ADDR_VALID(addr) (((addr) & CACHE_ADDRESS_START) == CACHE_ADDRESS_START)
#define CACHE_AES_BYPASS (0xA5)
#define CACHE_KEY_GEN (0xA5)
#define CACHE_WRAP_ENABLE (0xA5)
#define CACHE_ZONE_ENCRYPT ((uint32_t)0xA5000000)
#define CACHE_CODE_BUS_OFFSET_POS (0)
#define CACHE_CODE_BUS_OFFSET_WIDTH (5)
#define CACHE_CODE_BUS_OFFSET_MASK ((uint32_t)0x001F)
#define CACHE_CODE_BUS_SET_POS (5)
#define CACHE_CODE_BUS_SET_WIDTH (8)
#define CACHE_CODE_BUS_SET_MASK ((uint32_t)0x00FF)
#define CACHE_CODE_BUS_TAG_POS (13)
#define CACHE_CODE_BUS_TAG_WIDTH (11)
#define CACHE_CODE_BUS_TAG_MASK ((uint32_t)0x07FF)
#define CHCHE_ALGORITHM_SET_POS (28)
#define CACHE_BUILD_INDEX_OFFSET(x) (((x) & CACHE_CODE_BUS_OFFSET_MASK) << CACHE_CODE_BUS_OFFSET_POS)
#define CACHE_BUILD_INDEX_SET(x) (((x) & CACHE_CODE_BUS_SET_MASK) << CACHE_CODE_BUS_SET_POS)
#define CACHE_BUILD_INDEX_TAG(x) (((x) & CACHE_CODE_BUS_TAG_MASK) << CACHE_CODE_BUS_TAG_POS)
#define CACHE_ADDRESS_BUILD(base,index_set,tag_way,offset) ((base) | CACHE_BUILD_INDEX_SET(index_set) | CACHE_BUILD_INDEX_TAG(tag_way) | CACHE_BUILD_INDEX_OFFSET(offset))
#define CACHE_TAG_NUM(x) ((x >> CACHE_CODE_BUS_TAG_POS) & CACHE_CODE_BUS_TAG_MASK)
#define CACHE_SET_NUM(x) ((x >> CACHE_CODE_BUS_SET_POS) & CACHE_CODE_BUS_SET_MASK)
#define CACHE_OFF_NUM(x) ((x >> CACHE_CODE_BUS_OFFSET_POS) & CACHE_CODE_BUS_OFFSET_MASK)
typedef enum
{
CACHE_Encrypt_Mode_All = 0x0,
CACHE_Encrypt_Mode_Zone,
}CACHE_EncryptModeTypeDef;
#define IS_CACHE_ENCRYPT_MODE(MODE) (((MODE) == CACHE_Encrypt_Mode_All) || \
((MODE) == CACHE_Encrypt_Mode_Zone))
typedef struct
{
uint32_t I[4];
uint32_t K[4];
uint32_t AES_CS;
uint32_t CONFIG;
uint32_t aes_enable;
uint32_t Address;
uint32_t size;
uint32_t algorithm;
uint32_t encrypt_mode;
uint32_t encrypt_saddr;
uint32_t encrypt_eaddr;
}CACHE_InitTypeDef;
void CACHE_Init(CACHE_TypeDef *Cache, CACHE_InitTypeDef *CACHE_InitStruct);
void CACHE_Clean(CACHE_TypeDef *Cache, CACHE_InitTypeDef *CACHE_InitStruct);
void CACHE_CleanAll(CACHE_TypeDef *Cache);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

51
bsp/airm2m/air105/libraries/HAL_Driver/Inc/air105_conf.h Normal file
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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __AIR105_CONF_H
#define __AIR105_CONF_H
/* Includes ------------------------------------------------------------------*/
/* Uncomment the line below to enable peripheral header file inclusion */
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#include "string.h"
#include "air105_cache.h"
#include "air105_dcmi.h"
#include "air105_dma.h"
#include "air105_gpio.h"
#include "air105_i2c.h"
#include "air105_qspi.h"
#include "air105_sysctrl.h"
#include "air105_timer.h"
#include "air105_uart.h"
#include "air105_wdt.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
#endif

74
bsp/airm2m/air105/libraries/HAL_Driver/Inc/air105_crc.h Normal file
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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_CRC_H
#define __AIR105_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/* Exported types ------------------------------------------------------------*/
typedef enum
{
CRC_16 = 0x01,
CRC_16_Modbus = 0x02,
CRC_CCITT_0xffff = 0x03,
CRC_CCITT_XModem = 0x04,
CRC_32 = 0x05
}CRC_Param_TypeDef;
typedef enum
{
CRC_Poly_16_1021 = 0x01,
CRC_Poly_16_8005 = 0x02,
CRC_Poly_32_04C11DB7 = 0x03
}CRC_Poly_TypeDef;
typedef enum
{
CRC_PolyMode_Normal = 0x01,
CRC_PolyMode_Reversed = 0x02,
}CRC_PolyMode_TypeDef;
typedef struct
{
CRC_Poly_TypeDef CRC_Poly;
CRC_PolyMode_TypeDef CRC_PolyMode;
uint32_t CRC_Init_Value;
uint32_t CRC_Xor_Value;
}CRC_ConfigTypeDef;
uint32_t CRC_CalcBlockCRC(uint32_t CRC_type, uint8_t *pData, uint32_t len);
uint32_t CRC_Calc(CRC_ConfigTypeDef *CRC_Config, uint8_t *pData, uint32_t len);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_DAC_H__
#define __AIR105_DAC_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Include ------------------------------------------------------------------*/
#include "air105.h"
#define DAC_CR1_IS_RUNNING ((uint32_t)0x20000000)
#define DAC_CR1_POWER_DOWN ((uint32_t)0x00000010)
#define DAC_CR1_FIFO_RESET ((uint32_t)0x00000008)
#define DAC_CR1_DMA_ENABLE ((uint32_t)0x00000004)
#define IS_DAC_DATA(DATA) ((DATA) <= 0x3FF)
#define DAC_CURR_SEL_MASK ((uint32_t)0x00000020)
#define DAC_CURR_SEL_20K ((uint32_t)0x00000000)
#define DAC_CURR_SEL_2K ((uint32_t)0x00000020)
#define IS_DAC_CURR_SEL(CURR) (((CURR) == DAC_CURR_SEL_20K) || \
((CURR) == DAC_CURR_SEL_2K))
#define IS_DAC_FIFO_THR(THR) ((THR) <= 0xF)
typedef struct _DAC_InitTypeDef
{
uint32_t DAC_CurrSel; /* DAC mode select */
uint32_t DAC_TimerExp; /* DAC timer expectation */
uint32_t DAC_FIFOThr; /* DAC FIFO Threshold */
} DAC_InitTypeDef;
#define DAC_FIFO_DEPTH (16)
#define DAC_IT_STATUS_SHIFT (30)
#define DAC_IT_FIFO_THR ((uint32_t)0x0002)
#define DAC_IT_FIFO_OVERFLOW ((uint32_t)0x0001)
#define IS_DAC_IT(IT) (((IT) == DAC_IT_FIFO_THR) || \
((IT) == DAC_IT_FIFO_OVERFLOW))
#define DAC_FLAG_RUNNING (DAC_CR1_IS_RUNNING)
#define DAC_FLAG_OVERFLOW ((uint32_t)0x40000000)
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_RUNNING) || \
((FLAG) == DAC_FLAG_OVERFLOW))
/* Exported functions -------------------------------------------------------*/
void DAC_Init(DAC_InitTypeDef *DAC_InitStruct);
void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct);
void DAC_FIFOReset(void);
void DAC_Cmd(FunctionalState NewState);
void DAC_DMACmd(FunctionalState NewState);
void DAC_SetData(uint16_t Data);
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Flag);
void DAC_ClearFlag(uint32_t DAC_Flag);
void DAC_ITConfig(uint32_t DAC_IT, FunctionalState NewState);
ITStatus DAC_GetITStatus(uint32_t DAC_IT);
void DAC_ClearITPendingBit(uint32_t DAC_IT);
#ifdef __cplusplus
}
#endif
#endif /* __AIR105_DAC_H__ */

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_DCMI_H
#define __AIR105_DCMI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/* Exported types ------------------------------------------------------------*/
/**
* @brief DCMI Init structure definition
*/
typedef struct
{
uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot.
This parameter can be a value of @ref DCMI_Capture_Mode */
uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
This parameter can be a value of @ref DCMI_Synchronization_Mode */
uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
This parameter can be a value of @ref DCMI_Capture_Rate */
uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
uint32_t DCMI_ByteSelectMode; /*!< Specifies the Capture Select Byte Mode: Select All Bytes, 1 of 2, 1 of 4 or 2 of 4
This parameter can be a value of @ref DCMI_ByteSelect_Mode */
uint32_t DCMI_LineSelectMode; /*!< Specifies the Capture Select Line Mode: Select All Lines, Odd Line or Even Line
This parameter can be a value of @ref DCMI_ByteLine_Mode */
uint32_t DCMI_ClockDiv; /*!< Specifies the DCMI Slave Clock Div: 2~16 from HCLK
This parameter can be a value of @ref DCMI_Clock_Div */
} DCMI_InitTypeDef;
/**
* @brief DCMI CROP Init structure definition
*/
typedef struct
{
uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture
will start. This parameter can be a value between 0x00 and 0x1FFF */
uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture.
This parameter can be a value between 0x00 and 0x3FFF */
uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point.
This parameter can be a value between 0x00 and 0x3FFF */
uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting
point on the same line.
This parameter can be a value between 0x00 and 0x3FFF */
} DCMI_CROPInitTypeDef;
/**
* @brief DCMI Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
} DCMI_CodesInitTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup DCMI_Exported_Constants
* @{
*/
/** @defgroup DCMI_Capture_Mode
* @{
*/
#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously
into the destination memory through the DMA */
#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of
frame and then transfers a single frame through the DMA */
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
((MODE) == DCMI_CaptureMode_SnapShot))
/**
* @}
*/
/** @defgroup DCMI_Synchronization_Mode
* @{
*/
#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
((MODE) == DCMI_SynchroMode_Embedded))
/**
* @}
*/
/** @defgroup DCMI_PIXCK_Polarity
* @{
*/
#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
((POLARITY) == DCMI_PCKPolarity_Rising))
/**
* @}
*/
/** @defgroup DCMI_VSYNC_Polarity
* @{
*/
#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
((POLARITY) == DCMI_VSPolarity_High))
/**
* @}
*/
/** @defgroup DCMI_HSYNC_Polarity
* @{
*/
#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
((POLARITY) == DCMI_HSPolarity_High))
/**
* @}
*/
/** @defgroup DCMI_Capture_Rate
* @{
*/
#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */
#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */
#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
((RATE) == DCMI_CaptureRate_1of4_Frame))
/** @defgroup DCMI_Clock_Div
* @{
*/
#define DCMI_Clock_Div2 ((uint32_t)0x00000000)
#define DCMI_Clock_Div4 ((uint32_t)0x20000000)
#define DCMI_Clock_Div6 ((uint32_t)0x40000000)
#define DCMI_Clock_Div8 ((uint32_t)0x60000000)
#define DCMI_Clock_Div10 ((uint32_t)0x80000000)
#define DCMI_Clock_Div12 ((uint32_t)0xA0000000)
#define DCMI_Clock_Div14 ((uint32_t)0xC0000000)
#define DCMI_Clock_Div16 ((uint32_t)0xE0000000)
#define IS_DCMI_CLOCK_DIV(DIV) (((DIV) == DCMI_Clock_Div2) ||\
((DIV) == DCMI_Clock_Div4) ||\
((DIV) == DCMI_Clock_Div6) ||\
((DIV) == DCMI_Clock_Div8) ||\
((DIV) == DCMI_Clock_Div10) ||\
((DIV) == DCMI_Clock_Div12) ||\
((DIV) == DCMI_Clock_Div14) ||\
((DIV) == DCMI_Clock_Div16))
#define DCMI_Clock_Div_MSK ((uint32_t)0xE0000000)
/**
* @}
*/
/** @defgroup DCMI_Extended_Data_Mode
* @{
*/
#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
#define IS_DCMI_EXTENDED_DATA(DATA) (((DATA) == DCMI_ExtendedDataMode_8b) || \
((DATA) == DCMI_ExtendedDataMode_10b) ||\
((DATA) == DCMI_ExtendedDataMode_12b) ||\
((DATA) == DCMI_ExtendedDataMode_14b))
/** @defgroup DCMI_ByteSelectMode
* @{
*/
#define DCMI_ByteSelect_Mode_AllByte ((uint32_t)0x00000000)
#define DCMI_ByteSelect_Mode_1of2_OddStart ((uint32_t)0x00010000)
#define DCMI_ByteSelect_Mode_1of4_OddStart ((uint32_t)0x00020000)
#define DCMI_ByteSelect_Mode_2of4_OddStart ((uint32_t)0x00030000)
#define DCMI_ByteSelect_Mode_1of2_EvenStart ((uint32_t)0x00050000)
#define DCMI_ByteSelect_Mode_1of4_EvenStart ((uint32_t)0x00060000)
#define DCMI_ByteSelect_Mode_2of4_EvenStart ((uint32_t)0x00070000)
#define IS_DCMI_BYTESELECT_MODE(MODE) (((MODE) == DCMI_ByteSelect_Mode_AllByte) ||\
((MODE) == DCMI_ByteSelect_Mode_1of2_OddStart) ||\
((MODE) == DCMI_ByteSelect_Mode_1of4_OddStart) ||\
((MODE) == DCMI_ByteSelect_Mode_2of4_OddStart) ||\
((MODE) == DCMI_ByteSelect_Mode_1of2_EvenStart) ||\
((MODE) == DCMI_ByteSelect_Mode_1of4_EvenStart) ||\
((MODE) == DCMI_ByteSelect_Mode_2of4_EvenStart))
/** @defgroup DCMI_ByteSelectMode
* @{
*/
#define DCMI_LineSelect_Mode_AllLine ((uint32_t)0x00000000)
#define DCMI_LineSelect_Mode_OddLine ((uint32_t)0x00080000)
#define DCMI_LineSelect_Mode_EvenLine ((uint32_t)0x00180000)
#define IS_DCMI_LINESELECT_MODE(MODE) (((MODE) == DCMI_LineSelect_Mode_AllLine) ||\
((MODE) == DCMI_LineSelect_Mode_OddLine) ||\
((MODE) == DCMI_LineSelect_Mode_EvenLine))
/**
* @}
*/
/** @defgroup DCMI_DMA_Request_FIFO_Size
* @{
*/
#define DCMI_DMARequestFIFOSize_1Word ((uint32_t)0x20000000) /*!< DCMI FIFO DMARequest*/
#define DCMI_DMARequestFIFOSize_2Word ((uint32_t)0x40000000) /*!< DCMI FIFO DMARequest*/
#define DCMI_DMARequestFIFOSize_4Word ((uint32_t)0x80000000) /*!< DCMI FIFO DMARequest*/
#define DCMI_DMARequestFIFOSize_MSK ((uint32_t)0xE0000000)
#define IS_DCMI_DMAREQUESTFIFO_SIZE(SIZE) (((SIZE) == DCMI_DMARequestFIFOSize_1Word) ||\
((SIZE) == DCMI_DMARequestFIFOSize_2Word) ||\
((SIZE) == DCMI_DMARequestFIFOSize_4Word))
/**
* @}
*/
/** @defgroup DCMI_interrupt_sources
* @{
*/
#define DCMI_IT_FRAME ((uint16_t)0x0001)
#define DCMI_IT_OVF ((uint16_t)0x0002)
#define DCMI_IT_ERR ((uint16_t)0x0004)
#define DCMI_IT_VSYNC ((uint16_t)0x0008)
#define DCMI_IT_LINE ((uint16_t)0x0010)
#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
((IT) == DCMI_IT_OVF) || \
((IT) == DCMI_IT_ERR) || \
((IT) == DCMI_IT_VSYNC) || \
((IT) == DCMI_IT_LINE))
/**
* @}
*/
/** @defgroup DCMI_Flags
* @{
*/
/**
* @brief DCMI SR register
*/
#define DCMI_FLAG_HSYNC ((uint16_t)0x2001)
#define DCMI_FLAG_VSYNC ((uint16_t)0x2002)
#define DCMI_FLAG_FNE ((uint16_t)0x2004)
/**
* @brief DCMI RISR register
*/
#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001)
#define DCMI_FLAG_OVFRI ((uint16_t)0x0002)
#define DCMI_FLAG_ERRRI ((uint16_t)0x0004)
#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008)
#define DCMI_FLAG_LINERI ((uint16_t)0x0010)
/**
* @brief DCMI MISR register
*/
#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001)
#define DCMI_FLAG_OVFMI ((uint16_t)0x1002)
#define DCMI_FLAG_ERRMI ((uint16_t)0x1004)
#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008)
#define DCMI_FLAG_LINEMI ((uint16_t)0x1010)
#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
((FLAG) == DCMI_FLAG_VSYNC) || \
((FLAG) == DCMI_FLAG_FNE) || \
((FLAG) == DCMI_FLAG_FRAMERI) || \
((FLAG) == DCMI_FLAG_OVFRI) || \
((FLAG) == DCMI_FLAG_ERRRI) || \
((FLAG) == DCMI_FLAG_VSYNCRI) || \
((FLAG) == DCMI_FLAG_LINERI) || \
((FLAG) == DCMI_FLAG_FRAMEMI) || \
((FLAG) == DCMI_FLAG_OVFMI) || \
((FLAG) == DCMI_FLAG_ERRMI) || \
((FLAG) == DCMI_FLAG_VSYNCMI) || \
((FLAG) == DCMI_FLAG_LINEMI))
#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
/**
* @brief set dcmi input from out signal
*/
#define DCMI_FROM_OUT (0x1<<13)
/* Function used to set the DCMI configuration to the default reset state ****/
void DCMI_DeInit(void);
/* Initialization and Configuration functions *********************************/
void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
void DCMI_CROPCmd(FunctionalState NewState);
void DCMI_JPEGCmd(FunctionalState NewState);
void DCMI_SetDMARequsetFIFOSize(uint32_t NewFIFOSize);
void DCMI_SetExtInput(void);
/* Image capture functions ****************************************************/
void DCMI_Cmd(FunctionalState NewState);
void DCMI_CaptureCmd(FunctionalState NewState);
uint32_t DCMI_ReadData(void);
uint32_t DCMI_GetFIFODataWordNum(void);
/* Interrupts and flags management functions **********************************/
void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
void DCMI_ClearFlag(uint16_t DCMI_FLAG);
ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
#ifdef __cplusplus
}
#endif
#endif /*__AIR105_DCMI_H */

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_DMA_H
#define __AIR105_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
typedef struct
{
uint32_t DMA_Peripheral;
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_incremented_mode */
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_incremented_mode */
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data item width.
This parameter can be a value of @ref DMA_data_size */
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data item width.
This parameter can be a value of @ref DMA_data_size */
uint32_t DMA_PeripheralBurstSize; /*!< Specifies the Peripheral Number of data items during per burst transaction.
read or write from the Peripheral every time a burst transaction request
This parameter can be a value of @ref DMA_burst_size */
uint32_t DMA_MemoryBurstSize; /*!< Specifies the Memory Number of data items during per burst transaction.
read or write from the Memory every time a burst transaction request
This parameter can be a value of @ref DMA_burst_size */
uint32_t DMA_PeripheralHandShake; /*!< Specifies the HandShake to control the DMA transacation.
This parameter can be a value of @ref DMA_peripheral_handshake */
uint32_t DMA_BlockSize; /*!< Specifies the Total Number of data items during the transaction. */
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
}DMA_InitTypeDef;
/**
* DMA多块传输内存表
*
*/
typedef struct _lli
{
uint32_t SAR;
uint32_t DAR;
uint32_t LLP;
uint32_t CTL_L;
uint32_t CTL_H;
uint32_t DSTAT;
}LLI;
/**多块传输模式
* @}
*/
#define Multi_Block_MODE01 (uint8_t)0x00 /*Single-block or last transfer of multi-block*/
#define Multi_Block_MODE02 (uint8_t)0x01 /*Auto-reload multi-block transfer with contiguous SAR*/
#define Multi_Block_MODE03 (uint8_t)0x02 /*Auto-reload multi-block transfer with contiguous DAR*/
#define Multi_Block_MODE04 (uint8_t)0x03 /*Auto-reload multi-block transfer*/
#define Multi_Block_MODE05 (uint8_t)0x04 /*Single-block or last transfer of multi-block*/
#define Multi_Block_MODE06 (uint8_t)0x05 /*Linked list multi-block transfer with contiguous SAR*/
#define Multi_Block_MODE07 (uint8_t)0x06 /*Linked list multi-block transfer with auto-reload SAR*/
#define Multi_Block_MODE08 (uint8_t)0x07 /*Linked list multi-block transfer with contiguous DAR*/
#define Multi_Block_MODE09 (uint8_t)0x08 /*Linked list multi-block transfer with auto-reload DAR*/
#define Multi_Block_MODE10 (uint8_t)0x09 /*Linked list multi-block transfer*/
/** @defgroup DMA_data_transfer_direction
* @{
*/
#define DMA_DIR_Memory_To_Memory ((uint32_t)0x0000)
#define DMA_DIR_Memory_To_Peripheral ((uint32_t)0x0001)
#define DMA_DIR_Peripheral_To_Memory ((uint32_t)0x0002)
/**
* @}
*/
/** @defgroup DMA_incremented_mode
* @{
*/
#define DMA_Inc_Increment ((uint32_t)0x00000000)
#define DMA_Inc_Decrement ((uint32_t)0x00000001)
#define DMA_Inc_Nochange ((uint32_t)0x00000002)
#define IS_DMA_INC_STATE(STATE) (((STATE) == DMA_Inc_Increment) || \
((STATE) == DMA_Inc_Decrement) || \
((STATE) == DMA_Inc_Nochange))
/**
* @}
*/
/** @defgroup DMA_data_size
* @{
*/
#define DMA_DataSize_Byte ((uint32_t)0x0000)
#define DMA_DataSize_HalfWord ((uint32_t)0x0001)
#define DMA_DataSize_Word ((uint32_t)0x0002)
#define IS_DMA_DATA_SIZE(SIZE) (((SIZE) == DMA_DataSize_Byte) || \
((SIZE) == DMA_DataSize_HalfWord) || \
((SIZE) == DMA_DataSize_Word))
/**
* @}
*/
/** @defgroup DMA_burst_size
* @{
*/
#define DMA_BurstSize_1 ((uint32_t)0x00)
#define DMA_BurstSize_4 ((uint32_t)0x01)
#define DMA_BurstSize_8 ((uint32_t)0x02)
#define DMA_BurstSize_16 ((uint32_t)0x03)
#define DMA_BurstSize_32 ((uint32_t)0x04)
/**
* @}
*/
/** @defgroup DMA_peripheral_handshake
* @{
*/
#define DMA_PeripheralHandShake_Hardware ((uint32_t)0x0000)
#define DMA_PeripheralHandShake_Software ((uint32_t)0x0001)
/**
* @}
*/
/** @defgroup DMA_Priority
* @{
*/
#define DMA_Priority_0 ((uint32_t)0x00000000)
#define DMA_Priority_1 ((uint32_t)0x00000020)
#define DMA_Priority_2 ((uint32_t)0x00000040)
#define DMA_Priority_3 ((uint32_t)0x00000060)
#define DMA_Priority_4 ((uint32_t)0x00000080)
#define DMA_Priority_5 ((uint32_t)0x000000A0)
#define DMA_Priority_6 ((uint32_t)0x000000C0)
/**
* @}
*/
/** @defgroup DMA_IT
* @{
*/
#define DMA_IT_BlockTransferComplete ((uint32_t)0x01)
#define DMA_IT_DestinationTransactionComplete ((uint32_t)0x02)
#define DMA_IT_Error ((uint32_t)0x04)
#define DMA_IT_SourceTransactionComplete ((uint32_t)0x08)
#define DMA_IT_DMATransferComplete ((uint32_t)0x10)
/**
* @}
*/
void DMA_Init(DMA_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct);
void DMA_ChannelCmd(DMA_TypeDef* DMA_Channelx, FunctionalState NewState);
void DMA_Cmd(FunctionalState NewState);
void DMA_ChannelConfig(DMA_TypeDef* DMA_Channelx, uint32_t DMA_Peripheral, uint32_t DMA_DIR);
void DMA_SetSRCAddress(DMA_TypeDef* DMA_Channelx, uint32_t Address);
void DMA_SetDSRAddress(DMA_TypeDef* DMA_Channelx, uint32_t Address);
void DMA_ITConfig(DMA_TypeDef* DMA_Channelx, uint32_t DMA_IT, FunctionalState NewState);
FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
void DMA_ClearFlag(uint32_t DMA_FLAG);
FunctionalState DMA_IsChannelEnabled(DMA_TypeDef* DMA_Channelx);
ITStatus DMA_GetITStatus(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT);
FlagStatus DMA_GetRawStatus(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT);
void DMA_ClearITPendingBit(DMA_TypeDef* DMA_Channelx,uint32_t DMA_IT);
void DMA_MultiBlockInit(DMA_TypeDef* DMA_Channelx, DMA_InitTypeDef* DMA_InitStruct ,\
LLI *first_lli,uint8_t Multi_Block_Mode);
void DMA_InitLLI(DMA_TypeDef* DMA_Channelx,LLI *lli,LLI *next_lli,
void *src_addr,void *dest_addr,uint16_t btsize);
uint32_t DMA_GetTransferNum(DMA_TypeDef* DMA_Channelx, uint32_t first_adr);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_EXTI_H
#define __AIR105_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "air105.h"
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Off = (uint32_t)0x00,
EXTI_Trigger_Rising = (uint32_t)0x01,
EXTI_Trigger_Falling = (uint32_t)0x02,
EXTI_Trigger_Rising_Falling = (uint32_t)0x03
}EXTI_TriggerTypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Off) || \
((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling) || \
((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @}
*/
/** @defgroup EXTI_Lines
* @{
*/
#define EXTI_Line0 ((uint32_t)0x0000) /*!< External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x0001) /*!< External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x0002) /*!< External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x0003) /*!< External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x0004) /*!< External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x0005) /*!< External interrupt line 5 */
#define IS_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5))
/**
* @}
*/
/** @defgroup EXTI_PinSource
* @{
*/
#define EXTI_PinSource0 ((uint32_t)0x0001) /*!< Pin 0 selected */
#define EXTI_PinSource1 ((uint32_t)0x0002) /*!< Pin 1 selected */
#define EXTI_PinSource2 ((uint32_t)0x0004) /*!< Pin 2 selected */
#define EXTI_PinSource3 ((uint32_t)0x0008) /*!< Pin 3 selected */
#define EXTI_PinSource4 ((uint32_t)0x0010) /*!< Pin 4 selected */
#define EXTI_PinSource5 ((uint32_t)0x0020) /*!< Pin 5 selected */
#define EXTI_PinSource6 ((uint32_t)0x0040) /*!< Pin 6 selected */
#define EXTI_PinSource7 ((uint32_t)0x0080) /*!< Pin 7 selected */
#define EXTI_PinSource8 ((uint32_t)0x0100) /*!< Pin 8 selected */
#define EXTI_PinSource9 ((uint32_t)0x0200) /*!< Pin 9 selected */
#define EXTI_PinSource10 ((uint32_t)0x0400) /*!< Pin 10 selected */
#define EXTI_PinSource11 ((uint32_t)0x0800) /*!< Pin 11 selected */
#define EXTI_PinSource12 ((uint32_t)0x1000) /*!< Pin 12 selected */
#define EXTI_PinSource13 ((uint32_t)0x2000) /*!< Pin 13 selected */
#define EXTI_PinSource14 ((uint32_t)0x4000) /*!< Pin 14 selected */
#define EXTI_PinSource15 ((uint32_t)0x8000) /*!< Pin 15 selected */
#define EXTI_PinSourceAll ((uint32_t)0xffff) /*!< Pin All selected */
#define IS_EXTI_PIN_SOURCE(PIN) (((((PIN) & ~(uint32_t)0xFFFF)) == 0x00) && ((PIN) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions
* @{
*/
void EXTI_DeInit(void);
void EXTI_LineConfig(uint32_t EXTI_Line, uint32_t EXTI_PinSource, EXTI_TriggerTypeDef EXTI_Trigger);
uint32_t EXTI_GetITStatus(void);
uint32_t EXTI_GetITLineStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif // __AIR105_EXTI_H
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_GPIO_H
#define __AIR105_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/**
* @brief Configuration Mode enumeration
*/
typedef enum
{
GPIO_Mode_IN_FLOATING = 0x01,
GPIO_Mode_IPU = 0x02,
GPIO_Mode_Out_OD = 0x03,
GPIO_Mode_Out_OD_PU = 0x04,
GPIO_Mode_Out_PP = 0x05
}GPIO_ModeTypeDef;
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN_FLOATING) || \
((MODE) == GPIO_Mode_IPU) || \
((MODE) == GPIO_Mode_Out_OD) || \
((MODE) == GPIO_Mode_Out_PP) || \
((MODE) == GPIO_Mode_Out_OD_PU))
/**
* @brief GPIO Remap Type definition
*/
typedef enum
{
GPIO_Remap_0 = 0x01,
GPIO_Remap_1 = 0x02,
GPIO_Remap_2 = 0x03,
GPIO_Remap_3 = 0x04,
}GPIO_RemapTypeDef;
#define IS_GET_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_0) || \
((REMAP) == GPIO_Remap_1) || \
((REMAP) == GPIO_Remap_2) || \
((REMAP) == GPIO_Remap_3) )
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIO_ModeTypeDef GPIO_Mode;
GPIO_RemapTypeDef GPIO_Remap;
}GPIO_InitTypeDef;
/**
* @brief Bit_SET and Bit_RESET enumeration
*/
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
/**
* @}
*/
/** @defgroup GPIO_Exported_Constants
* @{
*/
/** @defgroup GPIO_pins_define
* @{
*/
#define IS_GPIO_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || \
((PERIPH) == GPIOD) || \
((PERIPH) == GPIOE) || \
((PERIPH) == GPIOF))
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xffff) /*!< Pin All selected */
#define IS_GPIO_PIN(PIN) (((((PIN) & ~(uint16_t)0xFFFF)) == 0x00) && ((PIN) != (uint16_t)0x00))
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
((PIN) == GPIO_Pin_1) || \
((PIN) == GPIO_Pin_2) || \
((PIN) == GPIO_Pin_3) || \
((PIN) == GPIO_Pin_4) || \
((PIN) == GPIO_Pin_5) || \
((PIN) == GPIO_Pin_6) || \
((PIN) == GPIO_Pin_7) || \
((PIN) == GPIO_Pin_8) || \
((PIN) == GPIO_Pin_9) || \
((PIN) == GPIO_Pin_10) || \
((PIN) == GPIO_Pin_11) || \
((PIN) == GPIO_Pin_12) || \
((PIN) == GPIO_Pin_13) || \
((PIN) == GPIO_Pin_14) || \
((PIN) == GPIO_Pin_15))
/**
* @}
*/
#define GPIO_PinSource0 0x00
#define GPIO_PinSource1 0x01
#define GPIO_PinSource2 0x02
#define GPIO_PinSource3 0x03
#define GPIO_PinSource4 0x04
#define GPIO_PinSource5 0x05
#define GPIO_PinSource6 0x06
#define GPIO_PinSource7 0x07
#define GPIO_PinSource8 0x08
#define GPIO_PinSource9 0x09
#define GPIO_PinSource10 0x0A
#define GPIO_PinSource11 0x0B
#define GPIO_PinSource12 0x0C
#define GPIO_PinSource13 0x0D
#define GPIO_PinSource14 0x0E
#define GPIO_PinSource15 0x0F
/** @defgroup GPIO_Port_Sources
* @{
*/
#define GPIO_PortSourceGPIOA ((uint32_t)0x00)
#define GPIO_PortSourceGPIOB ((uint32_t)0x01)
#define GPIO_PortSourceGPIOC ((uint32_t)0x02)
#define GPIO_PortSourceGPIOD ((uint32_t)0x03)
#define GPIO_PortSourceGPIOE ((uint32_t)0x04)
#define GPIO_PortSourceGPIOF ((uint32_t)0x05)
#define IS_GPIO_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \
((PORTSOURCE) == GPIO_PortSourceGPIOB) || \
((PORTSOURCE) == GPIO_PortSourceGPIOC) || \
((PORTSOURCE) == GPIO_PortSourceGPIOD) || \
((PORTSOURCE) == GPIO_PortSourceGPIOE) || \
((PORTSOURCE) == GPIO_PortSourceGPIOF))
/**
* @}
*/
/** @defgroup GPIO_WakeMode
* @{
*/
typedef enum
{
GPIO_WakeMode_Now = (uint32_t)0x00,
GPIO_WakeMode_AfterGlitch = (uint32_t)0x01
}GPIO_WakeModeTypeDef;
#define IS_GPIO_WAKE_MODE(MODE) (((MODE) == GPIO_WakeMode_Now) || \
((MODE) == GPIO_WakeMode_AfterGlitch))
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions
* @{
*/
void GPIO_DeInit(void);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void GPIO_PullUpCmd(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, FunctionalState NewState);
void GPIO_PinRemapConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_RemapTypeDef GPIO_Remap);
void GPIO_WakeEvenDeInit(void);
void GPIO_WakeEvenConfig(uint32_t GPIO_PortSource, uint32_t GPIO_Pin, FunctionalState NewState);
void GPIO_WakeModeConfig(GPIO_WakeModeTypeDef GPIO_WakeMode);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_HSPIM_H
#define __AIR105_HSPIM_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "air105.h"
typedef struct
{
uint8_t HSPIM_Enable;
uint8_t HSPIM_Mode;
uint8_t HSPIM_FirstBit;
uint8_t HSPIM_CPOL;
uint8_t HSPIM_CPHA;
uint8_t HSPIM_DivideEnable;
uint8_t HSPIM_BaudRatePrescaler;
uint8_t HSPIM_ReceiveDataLength;
uint8_t HSPIM_RXFIFOFullThreshold;
uint8_t HSPIM_TXFIFOEmptyThreshold;
}HSPIM_InitTypeDef;
typedef struct
{
uint8_t HSPIM_DMAReceiveEnable;
uint8_t HSPIM_DMATransmitEnable;
uint8_t HSPIM_DMAReceiveLevel;
uint8_t HSPIM_DMATransmitLevel;
}HSPIM_DMAInitTypeDef;
/** @defgroup HSPIM_Mode
* @{
*/
#define HSPIM_MODE_STANDARD (0x01)
#define HSPIM_MODE_DUAL_RECEIVE (0x02)
#define HSPIM_MODE_DUAL_TRANSMIT (0x03)
#define HSPIM_MODE_QUAD_RECEIVE (0x04)
#define HSPIM_MODE_QUAD_TRANSMIT (0x05)
#define IS_HSPIM_MODE(MODE) (((MODE) == HSPIM_MODE_STANDARD) || \
((MODE) == HSPIM_MODE_DUAL_RECEIVE) || \
((MODE) == HSPIM_MODE_DUAL_TRANSMIT) || \
((MODE) == HSPIM_MODE_QUAD_RECEIVE) || \
((MODE) == HSPIM_MODE_QUAD_TRANSMIT))
/**
* @}
*/
/** @defgroup HSPIM_Clock_Polarity
* @{
*/
#define HSPIM_CPOL_LOW (0x00)
#define HSPIM_CPOL_HIGH (0x01)
#define IS_HSPIM_CPOL(CPOL) (((CPOL) == HSPIM_CPOL_LOW)|| \
((CPOL) == HSPIM_CPOL_HIGH))
/**
* @}
*/
/** @defgroup HSPIM_Clock_Phase
* @{
*/
#define HSPIM_CPHA_1EDGE (0x00)
#define HSPIM_CPHA_2EDGE (0x01)
#define IS_HSPIM_CPHA(CPHA) (((CPHA) == HSPIM_CPHA_1EDGE) || \
(CPHA) == HSPIM_CPHA_2EDGE)
/**
* @}
*/
/** @defgroup HSPIM_First_Bit
* @{
*/
#define HSPIM_FIRST_BIT_MSB (0x00)
#define HSPIM_FIRST_BIT_LSB (0x01)
#define IS_HSPIM_FIRST_BIT(BIT) (((BIT) == HSPIM_FIRST_BIT_MSB) || \
((BIT) == HSPIM_FIRST_BIT_LSB))
/**
* @}
*/
/** @defgroup HSPIM_BaudRate_Prescaler
* @{
*/
#define HSPIM_BAUDRATE_PRESCALER_2 (0x01)
#define HSPIM_BAUDRATE_PRESCALER_4 (0x02)
#define HSPIM_BAUDRATE_PRESCALER_8 (0x04)
#define HSPIM_BAUDRATE_PRESCALER_16 (0x08)
#define HSPIM_BAUDRATE_PRESCALER_32 (0x10)
#define IS_HSPIM_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == HSPIM_BAUDRATE_PRESCALER_2) || \
((PRESCALER) == HSPIM_BAUDRATE_PRESCALER_4) || \
((PRESCALER) == HSPIM_BAUDRATE_PRESCALER_8) || \
((PRESCALER) == HSPIM_BAUDRATE_PRESCALER_16) || \
((PRESCALER) == HSPIM_BAUDRATE_PRESCALER_32))
/**
* @}
*/
/** @defgroup HSPIM_Receive_Data_Length
* @{
*/
#define HSPIM_RECEIVE_DATA_LENGTH_1_BYTE (0x00)
#define HSPIM_RECEIVE_DATA_LENGTH_2_BYTE (0x01)
#define HSPIM_RECEIVE_DATA_LENGTH_3_BYTE (0x02)
#define HSPIM_RECEIVE_DATA_LENGTH_4_BYTE (0x03)
#define HSPIM_RECEIVE_DATA_LENGTH_5_BYTE (0x04)
#define HSPIM_RECEIVE_DATA_LENGTH_6_BYTE (0x05)
#define HSPIM_RECEIVE_DATA_LENGTH_7_BYTE (0x06)
#define HSPIM_RECEIVE_DATA_LENGTH_8_BYTE (0x07)
#define HSPIM_RECEIVE_DATA_LENGTH_9_BYTE (0x08)
#define HSPIM_RECEIVE_DATA_LENGTH_10_BYTE (0x09
#define HSPIM_RECEIVE_DATA_LENGTH_11_BYTE (0x0A)
#define HSPIM_RECEIVE_DATA_LENGTH_12_BYTE (0x0B)
#define HSPIM_RECEIVE_DATA_LENGTH_13_BYTE (0x0C)
#define HSPIM_RECEIVE_DATA_LENGTH_14_BYTE (0x0D)
#define HSPIM_RECEIVE_DATA_LENGTH_15_BYTE (0x0E)
#define HSPIM_RECEIVE_DATA_LENGTH_16_BYTE (0x0F)
#define HSPIM_RECEIVE_DATA_LENGTH_32_BYTE (0x1F)
/**
* @}
*/
/** @defgroup HSPIM_TXFIFOEmptyThreshold
* @{
*/
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_1 ((uint32_t)0x0001)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_2 ((uint32_t)0x0002)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_3 ((uint32_t)0x0003)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_4 ((uint32_t)0x0004)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_5 ((uint32_t)0x0005)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_6 ((uint32_t)0x0006)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_7 ((uint32_t)0x0007)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_8 ((uint32_t)0x0008)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_9 ((uint32_t)0x0009)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_10 ((uint32_t)0x000A)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_11 ((uint32_t)0x000B)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_12 ((uint32_t)0x000C)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_13 ((uint32_t)0x000D)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_14 ((uint32_t)0x000E)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_15 ((uint32_t)0x000F)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_31 ((uint32_t)0x001F)
#define HSPIM_TX_FIFO_EMPTY_THRESHOLD_63 ((uint32_t)0x003F)
#define IS_HSPIM_TX_FIFO_EMPTY_THRESHOLD(THRESHOLD) ((((int32_t)(THRESHOLD)) >= HSPIM_TX_FIFO_EMPTY_THRESHOLD_1) && \
(((uint32_t)(THRESHOLD)) <= HSPIM_TX_FIFO_EMPTY_THRESHOLD_63))
/**
* @}
*/
/** @defgroup HSPIM_RXFIFOFullThreshold
* @{
*/
#define HSPIM_RX_FIFO_FULL_THRESHOLD_1 ((uint32_t)0x0001)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_2 ((uint32_t)0x0002)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_3 ((uint32_t)0x0003)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_4 ((uint32_t)0x0004)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_5 ((uint32_t)0x0005)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_6 ((uint32_t)0x0006)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_7 ((uint32_t)0x0007)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_8 ((uint32_t)0x0008)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_9 ((uint32_t)0x0009)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_10 ((uint32_t)0x000A)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_11 ((uint32_t)0x000B)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_12 ((uint32_t)0x000C)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_13 ((uint32_t)0x000D)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_14 ((uint32_t)0x000E)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_15 ((uint32_t)0x000F)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_16 ((uint32_t)0x0010)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_32 ((uint32_t)0x0020)
#define HSPIM_RX_FIFO_FULL_THRESHOLD_63 ((uint32_t)0x003F)
#define IS_HSPIM_RX_FIFO_FULL_THRESHOLD(THRESHOLD) ((((uint32_t)(THRESHOLD)) >= HSPIM_RX_FIFO_FULL_THRESHOLD_1) && \
(((uint32_t)(THRESHOLD)) <= HSPIM_RX_FIFO_FULL_THRESHOLD_63))
/**
* @}
*/
/** @defgroup SPI_DMAReceiveLevel
* @{
*/
#define HSPIM_DMA_RECEIVE_LEVEL_1 ((uint32_t)0x0001)
#define HSPIM_DMA_RECEIVE_LEVEL_2 ((uint32_t)0x0002)
#define HSPIM_DMA_RECEIVE_LEVEL_3 ((uint32_t)0x0003)
#define HSPIM_DMA_RECEIVE_LEVEL_4 ((uint32_t)0x0004)
#define HSPIM_DMA_RECEIVE_LEVEL_5 ((uint32_t)0x0005)
#define HSPIM_DMA_RECEIVE_LEVEL_6 ((uint32_t)0x0006)
#define HSPIM_DMA_RECEIVE_LEVEL_7 ((uint32_t)0x0007)
#define HSPIM_DMA_RECEIVE_LEVEL_8 ((uint32_t)0x0008)
#define HSPIM_DMA_RECEIVE_LEVEL_9 ((uint32_t)0x0009)
#define HSPIM_DMA_RECEIVE_LEVEL_10 ((uint32_t)0x000A)
#define HSPIM_DMA_RECEIVE_LEVEL_11 ((uint32_t)0x000B)
#define HSPIM_DMA_RECEIVE_LEVEL_12 ((uint32_t)0x000C)
#define HSPIM_DMA_RECEIVE_LEVEL_13 ((uint32_t)0x000D)
#define HSPIM_DMA_RECEIVE_LEVEL_14 ((uint32_t)0x000E)
#define HSPIM_DMA_RECEIVE_LEVEL_15 ((uint32_t)0x000F)
#define HSPIM_DMA_RECEIVE_LEVEL_16 ((uint32_t)0x0010)
#define HSPIM_DMA_RECEIVE_LEVEL_32 ((uint32_t)0x0020)
#define HSPIM_DMA_RECEIVE_LEVEL_64 ((uint32_t)0x0040)
#define IS_HSPIM_DMA_RECEIVE_LEVEL(LEVEL) ((((uint32_t)(LEVEL)) >= HSPIM_DMA_RECEIVE_LEVEL_1) && \
(((uint32_t)(LEVEL)) <= HSPIM_DMA_RECEIVE_LEVEL_64))
/**
* @}
*/
/** @defgroup SPI_DMATransmitLevel
* @{
*/
#define HSPIM_DMA_TRANSMIT_LEVEL_1 ((uint32_t)0x0001)
#define HSPIM_DMA_TRANSMIT_LEVEL_2 ((uint32_t)0x0002)
#define HSPIM_DMA_TRANSMIT_LEVEL_3 ((uint32_t)0x0003)
#define HSPIM_DMA_TRANSMIT_LEVEL_4 ((uint32_t)0x0004)
#define HSPIM_DMA_TRANSMIT_LEVEL_5 ((uint32_t)0x0005)
#define HSPIM_DMA_TRANSMIT_LEVEL_6 ((uint32_t)0x0006)
#define HSPIM_DMA_TRANSMIT_LEVEL_7 ((uint32_t)0x0007)
#define HSPIM_DMA_TRANSMIT_LEVEL_8 ((uint32_t)0x0008)
#define HSPIM_DMA_TRANSMIT_LEVEL_9 ((uint32_t)0x0009)
#define HSPIM_DMA_TRANSMIT_LEVEL_10 ((uint32_t)0x000A)
#define HSPIM_DMA_TRANSMIT_LEVEL_11 ((uint32_t)0x000B)
#define HSPIM_DMA_TRANSMIT_LEVEL_12 ((uint32_t)0x000C)
#define HSPIM_DMA_TRANSMIT_LEVEL_13 ((uint32_t)0x000D)
#define HSPIM_DMA_TRANSMIT_LEVEL_14 ((uint32_t)0x000E)
#define HSPIM_DMA_TRANSMIT_LEVEL_15 ((uint32_t)0x000F)
#define HSPIM_DMA_TRANSMIT_LEVEL_31 ((uint32_t)0x001F)
#define HSPIM_DMA_TRANSMIT_LEVEL_63 ((uint32_t)0x003F)
#define IS_HSPIM_DMA_TRANSMIT_LEVEL(LEVEL) ((((uint32_t)(LEVEL)) >= HSPIM_DMA_TRANSMIT_LEVEL_1) && \
(((uint32_t)(LEVEL)) <= HSPIM_DMA_TRANSMIT_LEVEL_63))
/**
* @}
*/
/** @defgroup HSPIM_Interrupt Mask and Status Flag
* @{
*/
#define HSPIM_IT_RX ((uint32_t)0x8000)
#define HSPIM_IT_TX ((uint32_t)0x4000)
#define HSPIM_IT_EN ((uint32_t)0x2000)
#define HSPIM_IT_ID_RXF ((uint32_t)0x0080)
#define HSPIM_IT_ID_RXTF ((uint32_t)0x0040)
#define HSPIM_IT_ID_RXE ((uint32_t)0x0020)
#define HSPIM_IT_ID_TXF ((uint32_t)0x0008)
#define HSPIM_IT_ID_TXE ((uint32_t)0x0002)
#define HSPIM_IT_ID_TXTF ((uint32_t)0x0001)
#define HSPIM_FLAG_TXE ((uint32_t)0x0004)
#define HSPIM_FLAG_TXF ((uint32_t)0x0010)
#define HSPIM_FLAG_TXTF ((uint32_t)0x0020)
#define HSPIM_FLAG_RXE ((uint32_t)0x0400)
#define HSPIM_FLAG_RXF ((uint32_t)0x1000)
#define HSPIM_FLAG_RXTF ((uint32_t)0x2000)
#define HSPIM_FIFO_TX ((uint32_t)0x0080)
#define HSPIM_FIFO_RX ((uint32_t)0x0040)
/**
* @}
*/
void HSPIM_Init(HSPIM_InitTypeDef* HSPIM_InitStruct);
void HSPIM_DMAInit(HSPIM_DMAInitTypeDef* HSPIM_DMAInitStruct);
void HSPIM_Cmd(FunctionalState NewState);
void HSPIM_TransmitCmd(FunctionalState NewState);
void HSPIM_DualQuadReceiveCmd(FunctionalState NewState);
void HSPIM_SendData(uint8_t Data);
uint8_t HSPIM_ReceiveData(void);
void HSPIM_ITConfig(uint32_t HSPIM_IT, FunctionalState NewState);
void HSPIM_FIFOReset(uint32_t HSPIM_IT);
FlagStatus HSPIM_IsTransmitDone(void);
FlagStatus HSPIM_IsReady(void);
FlagStatus HSPIM_GetFlagStatus(uint32_t HSPIM_Flag);
ITStatus HSPIM_GetITStatus(uint32_t HSPIM_IT);
void HSPIM_ModeSwitch(uint8_t Mode);
void HSPIM_WriteBuff(uint8_t Mode, uint16_t Size, uint8_t* Buff);
void HSPIM_ReadBuff(uint8_t Mode, uint16_t Size, uint8_t* Buff);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE***********************************************************************/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_I2C_H
#define __AIR105_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/** @defgroup I2C_mode
* @{
*/
typedef enum
{
I2C_Mode_Master =((uint32_t)0x0001),
I2C_Mode_Slave =((uint32_t)0x0002)
}I2CMode_TypeDef;
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_Master) || \
((MODE) == I2C_Mode_Slave))
/**
* @}
*/
typedef struct
{
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. */
I2CMode_TypeDef I2C_Mode;
uint32_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint32_t I2C_SDASetupTime;
uint32_t I2C_SDAHoldTime;
uint32_t I2C_TargetAddress;
uint32_t I2C_TargetAddressMode;
uint32_t I2C_OwnAddress; /*!< Specifies the slave mode own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
uint32_t I2C_RXFIFOFullThreshold;
uint32_t I2C_TXFIFOEmptyThreshold;
FunctionalState I2C_GenerateRestartEnable;
}I2C_InitTypeDef;
typedef struct
{
uint32_t I2C_DMAReq;
uint32_t I2C_DMAReceiveLevel;
uint32_t I2C_DMATransmitLevel;
FunctionalState I2C_DMAEnCmd;
}I2C_DMAInitTypeDef;
#define I2C_ClockSpeed_100KHz (100000)
#define I2C_ClockSpeed_400KHz (400000)
/** @defgroup I2C_duty_cycle_in_fast_mode
* @{
*/
/*Tlow/Thigh = ((I2C_DutyCycle_x_y & 0xFF00) >> 8) / (I2C_DutyCycle_x_y & 0x00FF)*/
#define I2C_DutyCycle_1 ((uint16_t)0x0101) /*!< I2C standard mode Tlow/Thigh = 1 */
#define I2C_DutyCycle_16_9 ((uint16_t)0x1009) /*!< I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0x0201) /*!< I2C fast mode Tlow/Thigh = 2 */
#define I2C_DutyCycle_8_3 ((uint16_t)0x0803) /*!< I2C high mode Tlow/Thigh = 8/3 */
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
((CYCLE) == I2C_DutyCycle_2))
/**
* @}
*/
#define IS_I2C_SDA_SETUP_TIME(TIME) ((TIME) <= 0x000000FF)
#define IS_I2C_SDA_HOLD_TIME(TIME) ((TIME) <= 0x0000FFFF)
/** @defgroup I2C_acknowledged_address
* @{
*/
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x0001)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0x0002)
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
/**
* @}
*/
/** @defgroup Target_Address_Bit
* @{
*/
#define I2C_TargetAddressMode_7bit ((uint16_t)0x0001)
#define I2C_TargetAddressMode_10bit ((uint16_t)0x0002)
#define IS_I2C_TARGET_ADDRESS_MODE(ADDRESS) (((ADDRESS) == I2C_TargetAddressMode_7bit) || \
((ADDRESS) == I2C_TargetAddressMode_10bit))
/**
* @}
*/
/** @defgroup SPI_RXFIFOFullThreshold
* @{
*/
#define I2C_RXFIFOFullThreshold_1 ((uint32_t)0x0000)
#define I2C_RXFIFOFullThreshold_2 ((uint32_t)0x0001)
#define I2C_RXFIFOFullThreshold_3 ((uint32_t)0x0002)
#define I2C_RXFIFOFullThreshold_4 ((uint32_t)0x0003)
#define I2C_RXFIFOFullThreshold_5 ((uint32_t)0x0004)
#define I2C_RXFIFOFullThreshold_6 ((uint32_t)0x0005)
#define I2C_RXFIFOFullThreshold_7 ((uint32_t)0x0006)
#define I2C_RXFIFOFullThreshold_8 ((uint32_t)0x0007)
#define IS_I2C_RX_FIFO_FULL_THRESHOLD(THRESHOLD) (THRESHOLD <= I2C_RXFIFOFullThreshold_8)
/**
* @}
*/
/** @defgroup SPI_TXFIFOEmptyThreshold
* @{
*/
#define I2C_TXFIFOEmptyThreshold_0 ((uint32_t)0x0000)
#define I2C_TXFIFOEmptyThreshold_1 ((uint32_t)0x0001)
#define I2C_TXFIFOEmptyThreshold_2 ((uint32_t)0x0002)
#define I2C_TXFIFOEmptyThreshold_3 ((uint32_t)0x0003)
#define I2C_TXFIFOEmptyThreshold_4 ((uint32_t)0x0004)
#define I2C_TXFIFOEmptyThreshold_5 ((uint32_t)0x0005)
#define I2C_TXFIFOEmptyThreshold_6 ((uint32_t)0x0006)
#define I2C_TXFIFOEmptyThreshold_7 ((uint32_t)0x0007)
#define I2C_TXFIFOEmptyThreshold_8 ((uint32_t)0x0008)
#define IS_I2C_TX_FIFO_EMPTY_THRESHOLD(THRESHOLD) (THRESHOLD <= I2C_TXFIFOEmptyThreshold_8)
/**
* @}
*/
/** @defgroup I2C_DMAReceiveLevel
* @{
*/
#define I2C_DMAReceiveLevel_1 ((uint32_t)0x0000)
#define I2C_DMAReceiveLevel_2 ((uint32_t)0x0001)
#define I2C_DMAReceiveLevel_3 ((uint32_t)0x0002)
#define I2C_DMAReceiveLevel_4 ((uint32_t)0x0003)
#define I2C_DMAReceiveLevel_5 ((uint32_t)0x0004)
#define I2C_DMAReceiveLevel_6 ((uint32_t)0x0005)
#define I2C_DMAReceiveLevel_7 ((uint32_t)0x0006)
#define I2C_DMAReceiveLevel_8 ((uint32_t)0x0007)
#define IS_I2C_DMA_RECEIVE_LEVEL(LEVEL) (LEVEL <= I2C_DMAReceiveLevel_8)
/**
* @}
*/
/** @defgroup I2C_DMATransmitLevel
* @{
*/
#define I2C_DMATransmitLevel_0 ((uint32_t)0x0000)
#define I2C_DMATransmitLevel_1 ((uint32_t)0x0001)
#define I2C_DMATransmitLevel_2 ((uint32_t)0x0002)
#define I2C_DMATransmitLevel_3 ((uint32_t)0x0003)
#define I2C_DMATransmitLevel_4 ((uint32_t)0x0004)
#define I2C_DMATransmitLevel_5 ((uint32_t)0x0005)
#define I2C_DMATransmitLevel_6 ((uint32_t)0x0006)
#define I2C_DMATransmitLevel_7 ((uint32_t)0x0007)
#define IS_I2C_DMA_TRANSMIT_LEVEL(LEVEL) (LEVEL <= I2C_DMATransmitLevel_7)
/**
* @}
*/
/** @defgroup I2C_DMA_transfer_requests
* @{
*/
#define I2C_DMAReq_Rx ((uint32_t)0x0001)
#define I2C_DMAReq_Tx ((uint32_t)0x0002)
#define IS_I2C_DMAREQ(DMAREQ) (((DMAREQ) & I2C_DMAReq_Tx) || \
((DMAREQ) & I2C_DMAReq_Rx))
/**
* @}
*/
#define I2C_IT_RXUDF ((uint32_t)0x0001) //clear by hardware
#define I2C_IT_RXOVF ((uint32_t)0x0002) //clear by read
#define I2C_IT_RXF ((uint32_t)0x0004) //clear by read
#define I2C_IT_TXOVF ((uint32_t)0x0008) //clear by read
#define I2C_IT_TXE ((uint32_t)0x0010) //clear by hardware
#define I2C_IT_RD_REQ ((uint32_t)0x0020) //clear by read
#define I2C_IT_TX_ABRT ((uint32_t)0x0040) //clear by read
#define I2C_IT_RX_DONE ((uint32_t)0x0080) //clear by read
#define I2C_IT_ACTIVITY ((uint32_t)0x0100) //clear by read
#define I2C_IT_STOP_DET ((uint32_t)0x0200) //clear by read
#define I2C_IT_START_DET ((uint32_t)0x0400)
#define I2C_IT_GEN_CALL ((uint32_t)0x0800)
#define I2C_IT_ALL ((uint32_t)0x0FFF)
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (~(uint32_t)0x0FFF)) == 0x00) && ((IT) != 0x00))
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (~(uint32_t)0x0FFF)) == 0x00) && ((IT) != 0x00))
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_RXUDF) || \
((IT) == I2C_IT_RXOVF) || \
((IT) == I2C_IT_RXF) || \
((IT) == I2C_IT_TXOVF) || \
((IT) == I2C_IT_TXE) || \
((IT) == I2C_IT_RD_REQ) || \
((IT) == I2C_IT_TX_ABRT) || \
((IT) == I2C_IT_RX_DONE) || \
((IT) == I2C_IT_ACTIVITY) || \
((IT) == I2C_IT_STOP_DET) || \
((IT) == I2C_IT_START_DET) || \
((IT) == I2C_IT_GEN_CALL) || \
((IT) == I2C_IT_ALL))
#define I2C_FLAG_ACTIVITY ((uint32_t)0x0001)
#define I2C_FLAG_TXNF ((uint32_t)0x0002)
#define I2C_FLAG_TXE ((uint32_t)0x0004)
#define I2C_FLAG_RXNE ((uint32_t)0x0008)
#define I2C_FLAG_RXF ((uint32_t)0x0010)
#define I2C_FLAG_MST_ACTIVITY ((uint32_t)0x0020)
#define I2C_FLAG_SLV_ACTIVITY ((uint32_t)0x0040)
#define I2C_FLAG_ALL ((uint32_t)0x007F)
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_ACTIVITY) || \
((FLAG) == I2C_FLAG_TXNF) || \
((FLAG) == I2C_FLAG_TXE) || \
((FLAG) == I2C_FLAG_RXNE) || \
((FLAG) == I2C_FLAG_RXF) || \
((FLAG) == I2C_FLAG_MST_ACTIVITY) || \
((FLAG) == I2C_FLAG_SLV_ACTIVITY) || \
((FLAG) == I2C_FLAG_ALL))
#define I2C_TX_ABRT_7BIT_ADDR_NOACK ((uint32_t)0x00000001)
#define I2C_TX_ABRT_10BIT_ADDR1_NOACK ((uint32_t)0x00000002)
#define I2C_TX_ABRT_10BIT_ADDR2_NOACK ((uint32_t)0x00000004)
#define I2C_TX_ABRT_TXDATA_NOACK ((uint32_t)0x00000008)
#define I2C_TX_ABRT_GEN_CALL_NOACK ((uint32_t)0x00000010)
#define I2C_TX_ABRT_GEN_CALL_READ ((uint32_t)0x00000020)
#define I2C_TX_ABRT_HIGH_SPEED_ACKDET ((uint32_t)0x00000040)
#define I2C_TX_ABRT_START_BYTE_ACKDET ((uint32_t)0x00000080)
#define I2C_TX_ABRT_HIGH_SPEED_NORSTRT ((uint32_t)0x00000100)
#define I2C_TX_ABRT_START_BYTE_NORSTRT ((uint32_t)0x00000200)
#define I2C_TX_ABRT_10BIT_RD_NORSTRT ((uint32_t)0x00000400)
#define I2C_TX_ABRT_LOST_ARB ((uint32_t)0x00000800)
#define I2C_TX_ABRT_SLVFLUSH_TXFIFO ((uint32_t)0x00001000)
#define I2C_TX_ABRT_SLV_LOST_ARB ((uint32_t)0x00002000)
#define I2C_TX_ABRT_SLV_RD_INTX ((uint32_t)0x00004000)
#define I2C_TX_ABRT_MASTER_DISABLE ((uint32_t)0x00008000)
#define I2C_TX_ABRT_USER_ABRT ((uint32_t)0x00010000)
#define I2C_TX_ABRT_TX_FLUSH_CNT ((uint32_t)0x00020000)
#define IS_I2C_TX_ABRT(ABRT) (((ABRT) == I2C_TX_ABRT_7BIT_ADDR_NOACK) || \
((ABRT) == I2C_TX_ABRT_10BIT_ADDR1_NOACK) || \
((FLAG) == I2C_TX_ABRT_10BIT_ADDR2_NOACK) || \
((FLAG) == I2C_TX_ABRT_TXDATA_NOACK) || \
((FLAG) == I2C_TX_ABRT_GEN_CALL_NOACK) || \
((FLAG) == I2C_TX_ABRT_GEN_CALL_READ) || \
((FLAG) == I2C_TX_ABRT_HIGH_SPEED_ACKDET) || \
((FLAG) == I2C_TX_ABRT_START_BYTE_ACKDET) || \
((FLAG) == I2C_TX_ABRT_HIGH_SPEED_NORSTRT) || \
((FLAG) == I2C_TX_ABRT_START_BYTE_NORSTRT) || \
((FLAG) == I2C_TX_ABRT_10BIT_RD_NORSTRT) || \
((FLAG) == I2C_TX_ABRT_LOST_ARB) || \
((FLAG) == I2C_TX_ABRT_SLVFLUSH_TXFIFO) || \
((FLAG) == I2C_TX_ABRT_SLV_LOST_ARB) || \
((FLAG) == I2C_TX_ABRT_SLV_RD_INTX) || \
((FLAG) == I2C_TX_ABRT_MASTER_DISABLE) || \
((FLAG) == I2C_TX_ABRT_USER_ABRT) || \
((FLAG) == I2C_TX_ABRT_TX_FLUSH_CNT))
typedef enum
{
I2C_DataCMD_Write = (uint32_t)0x01,
I2C_DataCMD_Read = (uint32_t)0x02
}I2CDataCMD_TypeDef;
#define IS_I2C_DATA_CMD(CMD) (((CMD) == I2C_DataCMD_Write) || \
((CMD) == I2C_DataCMD_Read))
typedef enum
{
I2C_DataEndCondition_None = (uint32_t)0x01,
I2C_DataEndCondition_Stop = (uint32_t)0x02,
I2C_DataEndCondition_Restart = (uint32_t)0x03
}I2CDataEndCondition_TypeDef;
#define IS_I2C_DATA_END_CONDITION(CONDITION) (((CONDITION) == I2C_DataEndCondition_None) || \
((CONDITION) == I2C_DataEndCondition_Stop) || \
((CONDITION) == I2C_DataEndCondition_Restart))
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx,I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_SetTargetAddress(I2C_TypeDef* I2Cx, uint32_t TargetAddress, uint32_t TargetAddressMode);
void I2C_DMAInit(I2C_TypeDef* I2Cx, I2C_DMAInitTypeDef* I2C_DMAInitStruct);
void I2C_DMAStructInit(I2C_DMAInitTypeDef* I2C_DMAInitStruct);
void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
void I2C_SetSDASetupTime(I2C_TypeDef* I2Cx,uint32_t PCLKCycles);
void I2C_SetSDAHoldTime(I2C_TypeDef* I2Cx,uint32_t PCLKCycles);
void I2C_ITConfig(I2C_TypeDef* I2Cx,uint32_t I2C_IT, FunctionalState NewState);
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx,uint32_t I2C_IT);
ITStatus I2C_GetRawITStatus(I2C_TypeDef* I2Cx,uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx,uint32_t I2C_IT);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx,uint32_t I2C_FLAG);
uint32_t I2C_GetFlagStatusReg(I2C_TypeDef* I2Cx);
FlagStatus I2C_GetTXAbortSource(I2C_TypeDef* I2Cx,uint32_t I2C_TX_ABRT);
uint32_t I2C_GetTXAbortSourceReg(I2C_TypeDef* I2Cx);
I2CMode_TypeDef I2C_GetI2CMode(I2C_TypeDef* I2Cx);
void I2C_MasterGenerateReceiveSCL(I2C_TypeDef* I2Cx, I2CDataEndCondition_TypeDef DataCondition);
uint16_t I2C_ExtendData(uint8_t Data, I2CDataCMD_TypeDef DataCMD, I2CDataEndCondition_TypeDef DataCondition);
void I2C_WriteDataToDR(I2C_TypeDef* I2Cx, uint16_t ExtendData);
uint8_t I2C_ReadDataFromDR(I2C_TypeDef* I2Cx);
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data, I2CDataEndCondition_TypeDef DataCondition);
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx, I2CDataEndCondition_TypeDef DataCondition);
void I2C_SendBytes(I2C_TypeDef* I2Cx, uint8_t* Data, uint32_t DataLen, I2CDataEndCondition_TypeDef DataCondition);
void I2C_ReceiveBytes(I2C_TypeDef* I2Cx, uint8_t* Data, uint32_t DataLen, I2CDataEndCondition_TypeDef DataCondition);
void I2C_SlaveGeneralNACKOnlyCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
FlagStatus I2C_IsEnable(I2C_TypeDef* I2Cx);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_IT_H
#define __AIR105_IT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_KCU_H
#define __AIR105_KCU_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/**
* @brief KCU Init structure definition
*/
typedef struct
{
uint32_t KCU_DebounceTimeLevel;
uint32_t KCU_PortInput;
uint32_t KCU_PortOutput;
uint32_t KCU_Rand;
}KCU_InitTypeDef;
#define KCU_IT_PUSH (KCU_CTRL1_PUSH_IT)
#define KCU_IT_RELEASE (KCU_CTRL1_RELEASE_IT)
#define KCU_IT_OVERRUN (KCU_CTRL1_OVERRUN_IT)
void KCU_DeInit(void);
void KCU_Init(KCU_InitTypeDef *KCU_InitStruct);
void KCU_StructInit(KCU_InitTypeDef *KCU_InitStruct);
void KCU_Cmd(FunctionalState NewState);
uint32_t KCU_SetRand(uint32_t rand);
void KCU_ITConfig(uint32_t KCU_IT, FunctionalState NewState);
FlagStatus KCU_GetITStatus(uint32_t KCU_IT);
void KCU_ClearITPending(void);
uint32_t KCU_GetEvenReg(void);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_LCDI_H
#define __AIR105_LCDI_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "air105.h"
#define LCDI_CMD (0)
#define LCDI_DAT (1)
#define LCDI_MODE_6800 (0)
#define LCDI_MODE_8080 (1)
#define LCD_CMD_BUFF_SIZE (64)
#define LCD_READ_BUFF_SIZE (512)
#define LCD_WRITE_BUFF_SIZE (512)
//LCD module
#define LCDI_FIFO_OV_IE (1 << 12)
#define LCDI_FIFO_RST (1 << 11)
#define LCDI_WR_DMA_EN (1 << 10)
#define LCDI_WR_FIFO_EN (1 << 9)
#define LCDI_CTRL_AUTO_READ (1 << 8)
#define LCDI_CTRL_TYPE_8080 (1 << 7)
#define LCDI_CTRL_EN_RD (1 << 6)
#define LCDI_CTRL_RW_WR (1 << 5)
#define LCDI_CTRL_CD (1 << 4)
#define LCDI_CTRL_WIDTH_4BIT (1 << 3)
#define LCDI_CTRL_AUTO (1 << 2)
#define LCDI_CTRL_RD_IE (1 << 1)
#define LCDI_CTRL_WR_IE (1 << 0)
#define LCDI_STATUS_READY (1 << 2)
#define LCDI_STATUS_RD_IS (1 << 1)
#define LCDI_STATUS_WR_IS (1 << 0)
#define RNG_BUF_IS_FULL(pBuf) ((pBuf)->u32Tail == (pBuf)->u32Head)
#define RNG_BUF_NEXT_HEAD(pBuf) (((pBuf)->u32Head + 1) % ((pBuf)->u32BuffSize))
#define RNG_BUF_NEXT_TAIL(pBuf) (((pBuf)->u32Tail + 1) % ((pBuf)->u32BuffSize))
#define RNG_BUF_LEN(pBuf) (((pBuf)->u32Tail + (pBuf)->u32BuffSize - 1 - (pBuf)->u32Head) % (pBuf)->u32BuffSize)
#define RNG_BUF_PERI_TAIL(pBuf) (((pBuf)->u32Tail + (pBuf)->u32BuffSize - 1) % ((pBuf)->u32BuffSize))
typedef struct
{
uint32_t volatile u32Head;
uint32_t volatile u32Tail;
uint32_t volatile u32BuffSize;
uint32_t volatile u32Stat;
uint8_t volatile *pu8Buff;
} RNG_BUF8, *RNG_BUF8_ID;
typedef struct
{
uint32_t volatile u32Head;
uint32_t volatile u32Tail;
uint32_t volatile u32BuffSize;
uint32_t volatile u32Stat;
uint32_t volatile *pu32Buff;
} RNG_BUF32, *RNG_BUF32_ID;
typedef struct
{
uint8_t lcd_ReadBuff[LCD_READ_BUFF_SIZE];
uint8_t lcd_WriteBuff[LCD_WRITE_BUFF_SIZE];
uint32_t lcd_CmdBuff[LCD_CMD_BUFF_SIZE];
RNG_BUF8 rbRead;
RNG_BUF8 rbWrite;
RNG_BUF32 rbCmd;
RNG_BUF32_ID prbCmd;
RNG_BUF8_ID prbRead;
RNG_BUF8_ID prbWrite;
volatile uint32_t u32OpCount;
} RING_BUF;
typedef struct
{
uint8_t LCD_BusMode; //Bus mode(8080/6800)
uint8_t LCD_IntRead; //Read interrupt Enable
uint8_t LCD_IntWrite; //Read interrupt Enable
uint8_t fifo_level;
uint32_t LCD_MaxQTR; //Max qaurter cylce of read/write.
uint32_t fifo_ov_ie_enable;
uint32_t fifo_rst_enable;
uint32_t wr_dma_enable;
uint32_t wr_fifo_enable;
uint32_t opt;
RING_BUF ring_buf;
} LCD_InitTypeDef;
//Operate the bus signal
void LCD_BusRead(LCD_TypeDef *LCDx,uint8_t u8CD);
void LCD_BusWrite(LCD_TypeDef *LCDx,uint8_t u8CD, uint8_t value);
void LCD_Read(LCD_TypeDef *LCDx,uint8_t u8CD, uint8_t *dat);
void LCD_Write(LCD_TypeDef *LCDx,uint8_t u8CD, uint8_t u8Value);
//Buffer mode only can used in interrupt mode.
int32_t LCD_ReadBuff(LCD_TypeDef *LCDx, LCD_InitTypeDef *pLcdInit, uint8_t *pu8Buff, uint32_t u32BuffLen);
int32_t LCD_WriteBuff(LCD_TypeDef *LCDx, LCD_InitTypeDef *pLcdInit, uint8_t *pu8Buff, uint32_t u32BuffLen);
void LCD_Init(LCD_TypeDef *LCDx, LCD_InitTypeDef *pLcdInit);
void LCD_FIFODMAconfig(LCD_TypeDef *LCDx, LCD_InitTypeDef *LCD_InitType);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_OTP_H
#define __AIR105_OTP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/* Exported types ------------------------------------------------------------*/
typedef enum
{
OTP_Complete = 0,
OTP_ReadOnProgramOrSleep, //<2F>ڱ<EFBFBD>̡<EFBFBD><CCA1><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4><EFBFBD>OTP<54><50><EFBFBD>ж<EFBFBD><D0B6><EFBFBD><EFBFBD><EFBFBD>
OTP_ProgramIn_HiddenOrRO_Block, //<2F><>ֻ<EFBFBD><D6BB><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>б<EFBFBD><D0B1>
OTP_ProgramOutOfAddr, //<2F><>̷<EFBFBD>Χ<EFBFBD><CEA7><EFBFBD><EFBFBD>OTP<54><50>Χ
OTP_ProgramOnSleep, //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4><CCAC><EFBFBD>б<EFBFBD>̲<EFBFBD><CCB2><EFBFBD>
OTP_WakeUpOnNoSleep, //<2F>ڷ<EFBFBD><DAB7><EFBFBD><EFBFBD><EFBFBD>״̬<D7B4>½<EFBFBD><C2BD>л<EFBFBD><D0BB>Ѳ<EFBFBD><D1B2><EFBFBD>
OTP_TimeOut, //OTP<54><50>ɱ<EFBFBD>־λ<D6BE><CEBB>ʱû<CAB1><C3BB><EFBFBD><EFBFBD>λ
OTP_DataWrong,
}OTP_StatusTypeDef;
#define IS_OTP_ADDRESS(ADDRESS) (((ADDRESS) > AIR105_OTP_SIZE - 1) && ((ADDRESS) < AIR105_OTP_BASE + AIR105_OTP_SIZE))
void OTP_WakeUp(void);
void OTP_Unlock(void);
void OTP_Lock(void);
void OTP_ClearStatus(void);
void OTP_SetLatency(uint8_t u8_1UsClk, uint8_t u8_10NsCLK);
void OTP_TimCmd(FunctionalState NewState);
void OTP_SetProtect(uint32_t u32Addr);
void OTP_SetProtectLock(uint32_t u32Addr);
void OTP_UnProtect(uint32_t u32Addr);
uint32_t OTP_GetProtect(void);
uint32_t OTP_GetProtectLock(void);
void OTP_PowerOn(void);
Boolean OTP_IsReadReady(void);
Boolean OTP_IsWriteDone(void);
OTP_StatusTypeDef OTP_GetFlag(void);
Boolean OTP_IsProtect(uint32_t u32Addr);
Boolean OTP_IsProtectLock(uint32_t u32Addr);
OTP_StatusTypeDef OTP_WriteWord(uint32_t addr, uint32_t w);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef AIRMCU_FLASH
#define AIRMCU_FLASH
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include "air105.h"
/* Size of the flash */
#define X25Q_PAGE_SIZE 0x100
// Identification Operations
/***Command Definitions***/
// Program Operations
#define PAGE_PROG_CMD 0x02
#define QUAD_INPUT_PAGE_PROG_CMD 0x32
// Erase Operations
#define SECTOR_ERASE_CMD 0x20
#define CHIP_ERASE_CMD 0xC7
#define PROG_ERASE_RESUME_CMD 0x7A
#define PROG_ERASE_SUSPEND_CMD 0x75
#define SET_BURST_WITH_WRAP 0x77
#define RELEASE_FROM_DEEP_POWER_DOWN 0xAB
#define DEEP_POWER_DOWN 0xB9
/***End Cmd***/
#define QSPI_DEVICE_PARA_SAMPLE_DLY_Pos 15
#define QSPI_DEVICE_PARA_SAMPLE_PHA_Pos 14
#define QSPI_DEVICE_PARA_PROTOCOL_Pos 8
#define QSPI_DEVICE_PARA_DUMMY_CYCLE_Pos 4
#define ROM_QSPI_Init (*((void (*)(QSPI_InitTypeDef *))(*(uint32_t *)0x8010)))
#define ROM_QSPI_ReadID (*((uint32_t (*)(QSPI_CommandTypeDef *))(*(uint32_t *)0x8014)))
#define ROM_QSPI_WriteParam (*((uint8_t (*)(QSPI_CommandTypeDef *, uint16_t))(*(uint32_t *)0x8018)))
#define ROM_QSPI_EraseSector (*((uint8_t (*)(QSPI_CommandTypeDef *, uint32_t))(*(uint32_t *)0x801C)))
#define ROM_QSPI_ProgramPage (*((uint8_t (*)(QSPI_CommandTypeDef *, DMA_TypeDef *, uint32_t, uint32_t, uint8_t *))(*(uint32_t *)0x8024)))
#define ROM_QSPI_ReleaseDeepPowerDown (*((uint8_t (*)(QSPI_CommandTypeDef *))(*(uint32_t *)0x802C)))
#define ROM_QSPI_StatusReg (*((uint16_t (*)(QSPI_CommandTypeDef *))(*(uint32_t *)0x8034)))
typedef enum
{
QSPI_BUSMODE_111 = 0x00, //CMD-ADDR-DATA = 1-1-1
QSPI_BUSMODE_114 = 0x01, //CMD-ADDR-DATA = 1-1-4
QSPI_BUSMODE_144 = 0x02, //CMD-ADDR-DATA = 1-4-4
QSPI_BUSMODE_444 = 0x03, //CMD-ADDR-DATA = 4-4-4
}QSPI_BusModeTypeDef;
typedef enum
{
QSPI_CMDFORMAT_CMD8 = 0x00,
QSPI_CMDFORMAT_CMD8_RREG8 = 0x01,
QSPI_CMDFORMAT_CMD8_RREG16 = 0x02,
QSPI_CMDFORMAT_CMD8_RREG24 = 0x03,
QSPI_CMDFORMAT_CMD8_DMY24_WREG8 = 0x04,
QSPI_CMDFORMAT_CMD8_ADDR24_RREG8 = 0x05,
QSPI_CMDFORMAT_CMD8_ADDR24_RREG16 = 0x06,
QSPI_CMDFORMAT_CMD8_WREG8 = 0x07,
QSPI_CMDFORMAT_CMD8_WREG16 = 0x08,
QSPI_CMDFORMAT_CMD8_ADDR24 = 0x09,
QSPI_CMDFORMAT_CMD8_ADDR24_RDAT = 0x0A,
QSPI_CMDFORMAT_CMD8_ADDR24_DMY_RDAT = 0x0B,
QSPI_CMDFORMAT_CMD8_ADDR24_M8_DMY_RDAT = 0x0C,
QSPI_CMDFORMAT_CMD8_ADDR24_PDAT = 0x0D
}QSPI_CmdFormatTypeDef;
typedef enum
{
QSPI_PROTOCOL_CLPL = 0x00,
QSPI_PROTOCOL_CHPH = 0x03
}QSPI_ProtocolTypedef;
typedef enum
{
QSPI_FREQSEL_HCLK_DIV2 = 0x01,
QSPI_FREQSEL_HCLK_DIV3 = 0x02,
QSPI_FREQSEL_HCLK_DIV4 = 0x03
}QSPI_FreqSelTypeDef;
typedef struct
{
//Device Para
uint8_t SampleDly; //Default:0
uint8_t SamplePha; //Default:0
uint8_t ProToCol; //Defualt: QSPI_PROTOCOL_CLPL
uint8_t DummyCycles; //Include M7:0 Defualt: 6
uint8_t FreqSel; //Defualt: QSPI_FREQSEL_HCLK_DIV4
//Setting Cache
uint8_t Cache_Cmd_ReleaseDeepInstruction; //Defualt: 0xAB
uint8_t Cache_Cmd_DeepInstruction; //Defualt: 0xB9
uint8_t Cache_Cmd_ReadBusMode; //Defualt: QSPI_BUSMODE_144
uint8_t Cache_Cmd_ReadFormat; //Defualt: QSPI_CMDFORMAT_CMD8_ADDR24_DMY_RDAT
uint8_t Cache_Cmd_ReadInstruction; //Defualt: 0xEB
}QSPI_InitTypeDef;
typedef struct
{
uint8_t Instruction;
uint32_t BusMode;
uint32_t CmdFormat;
}QSPI_CommandTypeDef;
void QSPI_Init(QSPI_InitTypeDef *mhqspi);
void QSPI_SetLatency(uint32_t u32UsClk);
uint8_t FLASH_EraseSector(uint32_t sectorAddress);
uint8_t FLASH_ProgramPage(uint32_t addr, uint32_t size, uint8_t *buffer);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_RTC_H
#define __AIR105_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
#define RTC_32K_EXT_INC_SELECT (0x00000400U)
typedef enum
{
SELECT_EXT32K,
SELECT_INC32K
} RTCCLK_SOURCE_TypeDef;
#define IS_RTCCLK_SOURCE(FREQ) (((FREQ) == SELECT_EXT32K) || \
((FREQ) == SELECT_INC32K))
FlagStatus RTC_IsReady(void);
void RTC_ResetCounter(void);
uint32_t RTC_GetCounter(void);
void RTC_SetRefRegister(uint32_t RefValue);
uint32_t RTC_GetRefRegister(void);
void RTC_SetAlarm(uint32_t AlarmValue);
uint32_t RTC_GetAttrackTime(void);
void RTC_ITConfig(FunctionalState NewState);
void RTC_ClearITPendingBit(void);
ITStatus RTC_GetITStatus(void);
void RTC_CLKSourceSelect(RTCCLK_SOURCE_TypeDef source);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_SCI_H
#define __AIR105_SCI_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "air105.h"
#include <arm_math.h>
#define SCI_UNCONFIG (-1)
#define SCI_ICC_CLOCK_ERR (-2)
#define SCI_REF_CLOCK_ERR (-3)
#define SCI_IMPRECISION_CLK (-4)
#define SCI_EMV_F_D_ERR (-5)
#define SCI_EMV_TS_ERR (-6)
#define SCI_EMV_ATR_ERR (-7)
#define SCI_CARD_OUT_ERR (-8)
int32_t SCI_ConfigEMV(uint8_t SCI_Bitmap, uint32_t SCIx_Clk);
#ifdef __cplusplus
}
#endif
#endif ///< __AIR105_SCI_H

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_SENSOR_H
#define __AIR105_SENSOR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
typedef struct
{
uint32_t SENSOR_Port_Pull;
uint32_t SENSOR_Port_Static;
uint32_t SENSOR_Port_Dynamic;
FunctionalState SENSOR_Port_Enable;
uint32_t SENSOR_DynamicFrequency;
FunctionalState SENSOR_GlitchEnable;
uint32_t SENSOR_PUPU_Frequency;
uint32_t SENSOR_PUPU_DetectTime;
uint32_t SENSOR_PUPU_HoldTime;
FunctionalState SENSOR_PUPU_Enable;
FunctionalState SENSOR_Trig_Hold_Enable;
uint32_t SENSOR_Dynamic_Sample;
uint32_t SENSOR_Static_Sample;
}SENSOR_EXTInitTypeDef;
#define SENSOR_Port_S0 ((uint32_t)0x0001)
#define SENSOR_Port_S1 ((uint32_t)0x0002)
#define SENSOR_Port_S2 ((uint32_t)0x0004)
#define SENSOR_Port_S3 ((uint32_t)0x0008)
#define SENSOR_Port_S4 ((uint32_t)0x0010)
#define SENSOR_Port_S5 ((uint32_t)0x0020)
#define SENSOR_Port_S6 ((uint32_t)0x0040)
#define SENSOR_Port_S7 ((uint32_t)0x0080)
#define SENSOR_Port_All ((uint32_t)0x00FF)
#define SENSOR_Port_S01 (SENSOR_Port_S0 | SENSOR_Port_S1)
#define SENSOR_Port_S23 (SENSOR_Port_S2 | SENSOR_Port_S3)
#define SENSOR_Port_S45 (SENSOR_Port_S4 | SENSOR_Port_S5)
#define SENSOR_Port_S67 (SENSOR_Port_S6 | SENSOR_Port_S7)
#define IS_SENSOR_PORT(PORT) ((((PORT) & (uint32_t)0xFFFFFF00) == 0x00) && ((PORT) != (uint32_t)0x00))
/* <20>ⲿ<EFBFBD><E2B2BF>̬<EFBFBD><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> */
#define SENSOR_PUPU_Frequency_Default ((uint32_t)0x0000)
#define SENSOR_PUPU_Frequency_500ms ((uint32_t)0x0000)
#define SENSOR_PUPU_Frequency_1s ((uint32_t)0x0001)
#define IS_SENSOR_EXT_PUPU_FREQ(FREQ) ((FREQ) == SENSOR_PUPU_Frequency_500ms ||\
(FREQ) == SENSOR_PUPU_Frequency_1s)
/* <20>ⲿ<EFBFBD><E2B2BF>̬<EFBFBD><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define SENSOR_STATIC_SAMPLE_Default ((uint32_t)0x0001)
#define SENSOR_STATIC_SAMPLE_1 ((uint32_t)0x0000)
#define SENSOR_STATIC_SAMPLE_2 ((uint32_t)0x0001)
#define SENSOR_STATIC_SAMPLE_3 ((uint32_t)0x0002)
#define SENSOR_STATIC_SAMPLE_4 ((uint32_t)0x0003)
#define IS_SENSOR_EXT_STATIC_SAMPLE(COUNT) ((COUNT) >= SENSOR_STATIC_SAMPLE_1 &&\
(COUNT) <= SENSOR_STATIC_SAMPLE_4)
/* <20>ⲿ<EFBFBD><E2B2BF>̬<EFBFBD><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
#define SENSOR_DYNAMIC_SAMPLE_Default ((uint32_t)0x0002)
#define SENSOR_DYNAMIC_SAMPLE_1 ((uint32_t)0x0000)
#define SENSOR_DYNAMIC_SAMPLE_2 ((uint32_t)0x0001)
#define SENSOR_DYNAMIC_SAMPLE_3 ((uint32_t)0x0002)
#define SENSOR_DYNAMIC_SAMPLE_4 ((uint32_t)0x0003)
#define IS_SENSOR_EXT_DYNAMIC_SAMPLE(COUNT) ((COUNT) >= SENSOR_DYNAMIC_SAMPLE_1 &&\
(COUNT) <= SENSOR_DYNAMIC_SAMPLE_4)
/* <20>ⲿ<EFBFBD><E2B2BF>̬<EFBFBD><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>裬<EFBFBD><E8A3AC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Чʱ<D0A7><CAB1> */
#define SENSOR_PUPU_HoldTime_Default ((uint32_t)0x0002)
#define SENSOR_PUPU_HoldTime_1_2 ((uint32_t)0x0000)
#define SENSOR_PUPU_HoldTime_1_4 ((uint32_t)0x0001)
#define SENSOR_PUPU_HoldTime_1_8 ((uint32_t)0x0002)
#define SENSOR_PUPU_HoldTime_1_16 ((uint32_t)0x0003)
#define IS_SENSOR_EXT_PUPU_HOLD_TIME(TIME) ((TIME) == SENSOR_PUPU_HoldTime_1_2 ||\
(TIME) == SENSOR_PUPU_HoldTime_1_4 ||\
(TIME) == SENSOR_PUPU_HoldTime_1_8 ||\
(TIME) == SENSOR_PUPU_HoldTime_1_16)
/* <20><>̬<EFBFBD><CCAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5> */
#define SENSOR_DynamicFrequency_Default ((uint32_t)0x0003)
#define SENSOR_DynamicFrequency_31_25ms ((uint32_t)0x0000)
#define SENSOR_DynamicFrequency_125ms ((uint32_t)0x0001)
#define SENSOR_DynamicFrequency_500ms ((uint32_t)0x0002)
#define SENSOR_DynamicFrequency_1s ((uint32_t)0x0003)
#define IS_SENSOR_EXT_DYNAMIC_FREQ(FREQ) ((FREQ) == SENSOR_DynamicFrequency_Default ||\
(FREQ) == SENSOR_DynamicFrequency_31_25ms ||\
(FREQ) == SENSOR_DynamicFrequency_125ms ||\
(FREQ) == SENSOR_DynamicFrequency_500ms ||\
(FREQ) == SENSOR_DynamicFrequency_1s)
#define SENSOR_ANA_VOL_HIGH ((uint32_t)0x00000001)
#define SENSOR_ANA_VOL_LOW ((uint32_t)0x00000002)
#define SENSOR_ANA_TEMPER_HIGH ((uint32_t)0x00000004)
#define SENSOR_ANA_TEMPER_LOW ((uint32_t)0x00000008)
#define SENSOR_ANA_XTAL32K ((uint32_t)0x00000010)
#define SENSOR_ANA_MESH ((uint32_t)0x00000020)
#define SENSOR_ANA_VOLGLITCH ((uint32_t)0x00000040)
#define SENSOR_ANA_ALL ((uint32_t)0x0000007F)
#define IS_SENSOR_ANA(ANA) ((((ANA) & (uint32_t)0xFFFFFF80) == 0x00) && ((ANA) != (uint32_t)0x00))
#define SENSOR_LOCK_EXTS ((uint32_t)0x00000001)
#define SENSOR_LOCK_VOL_HIGH ((uint32_t)0x00000002)
#define SENSOR_LOCK_VOL_LOW ((uint32_t)0x00000004)
#define SENSOR_LOCK_TEMPER_HIGH ((uint32_t)0x00000008)
#define SENSOR_LOCK_TEMPER_LOW ((uint32_t)0x00000010)
#define SENSOR_LOCK_VOLGLITCH ((uint32_t)0x00000020)
#define SENSOR_LOCK_XTAL32K ((uint32_t)0x00000040)
#define SENSOR_LOCK_MESH ((uint32_t)0x00000080)
#define IS_SENSOR_LOCK(LOCK) ((((LOCK) & (uint32_t)0xFFFFFF00) == 0x00) && ((LOCK) != (uint32_t)0x00))
#define SENSOR_IT_EXTS ((uint32_t)0x00000FFF)
#define SENSOR_IT_VOL_HIGH ((uint32_t)0x00001000)
#define SENSOR_IT_VOL_LOW ((uint32_t)0x00002000)
#define SENSOR_IT_TEMPER_HIGH ((uint32_t)0x00004000)
#define SENSOR_IT_TEMPER_LOW ((uint32_t)0x00008000)
#define SENSOR_IT_GLITCH ((uint32_t)0x00010000)
#define SENSOR_IT_XTAL32K ((uint32_t)0x00020000)
#define SENSOR_IT_MESH ((uint32_t)0x00040000)
#define SENSOR_IT_SSC ((uint32_t)0x00100000)
#define IS_SENSOR_IT(IT) ((IT) == SENSOR_IT_EXTS || \
(IT) == SENSOR_IT_VOL_HIGH || \
(IT) == SENSOR_IT_VOL_LOW || \
(IT) == SENSOR_IT_TEMPER_HIGH || \
(IT) == SENSOR_IT_TEMPER_LOW || \
(IT) == SENSOR_IT_GLITCH || \
(IT) == SENSOR_IT_XTAL32K || \
(IT) == SENSOR_IT_MESH || \
(IT) == SENSOR_IT_SSC)
typedef enum
{
SENSOR_CPUReset = 0,
SENSOR_Interrupt = 1
}SENSOR_RespModeTypeDef;
#define IS_SENSOR_RESP_MODE(Mode) ((Mode) == SENSOR_CPUReset ||\
(Mode) == SENSOR_Interrupt)
uint32_t SENSOR_SetRand(uint32_t Rand);
uint32_t SENSOR_EXTInit(SENSOR_EXTInitTypeDef *SENSOR_EXTInitStruct);
uint32_t SENSOR_EXTPortCmd(uint32_t SENSOR_Port, FunctionalState NewState);
uint32_t SENSOR_EXTCmd(FunctionalState NewState);
FlagStatus SENSOR_EXTIsRuning(void);
uint32_t SENSOR_ANACmd(uint32_t SENSOR_ANA, FunctionalState NewState);
void SENSOR_Lock(uint32_t SENSOR_LOCK);
void SENSOR_AttackRespMode(SENSOR_RespModeTypeDef SENSOR_RespMode);
int32_t SENSOR_GetITStatus(uint32_t ITState);
int32_t SENSOR_GetITStatusReg(void);
void SENSOR_ClearITPendingBit(void);
FunctionalState SENSOR_GetEXTTrigPull(void);
FunctionalState SENSOR_SetEXTTrigPull(FunctionalState NewState);
FunctionalState SENSOR_GetEXTFilter(void);
FunctionalState SENSOR_SetEXTFilter(FunctionalState NewState);
#define SENSOR_STATIC_PULSE_PERIOD_500MS (0)
#define SENSOR_STATIC_PULSE_PERIOD_1S (1)
uint32_t SENSOR_GetEXTPulsePeriod(void);
uint32_t SENSOR_SetEXTPulsePeriod(uint32_t u32Period);
#define SENSOR_STATIC_PULSE_HOLD_1_2 (0)
#define SENSOR_STATIC_PULSE_HOLD_1_4 (1)
#define SENSOR_STATIC_PULSE_HOLD_1_8 (2)
#define SENSOR_STATIC_PULSE_HOLD_1_16 (3)
uint32_t SENSOR_GetEXTPulseHold(void);
uint32_t SENSOR_SetEXTPulseHold(uint32_t u32Hold);
FunctionalState SENSOR_GetEXTPulsePull(void);
FunctionalState SENSOR_SetEXTPulsePull(FunctionalState NewState);
#define SENSOR_SAMPLE_COUNT_1 (0)
#define SENSOR_SAMPLE_COUNT_2 (1)
#define SENSOR_SAMPLE_COUNT_3 (2)
#define SENSOR_SAMPLE_COUNT_4 (3)
uint32_t SENSOR_GetEXTStaticSample(void);
uint32_t SENSOR_SetEXTStaticSample(uint32_t u32Count);
uint32_t SENSOR_GetEXTDynamicSample(void);
uint32_t SENSOR_SetEXTDynamicSample(uint32_t u32Count);
uint32_t SENSOR_GetEXTDynamicFreq(void);
uint32_t SENSOR_SetEXTDynamicFreq(uint32_t u32Freq);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_SPI_H
#define __AIR105_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
#define SPI_DMACR_RDMAE_Pos (0)
#define SPI_DMACR_RDMAE_Mask (0x01U << SPI_DMACR_RDMAE_Pos)
#define SPI_DMACR_TDMAE_Pos (1)
#define SPI_DMACR_TDMAE_Mask (0x01U << SPI_DMACR_TDMAE_Pos)
/** @defgroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint32_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint32_t SPI_Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint32_t SPI_DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint32_t SPI_CPOL; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint32_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint32_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint32_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint32_t SPI_RXFIFOFullThreshold;
uint32_t SPI_TXFIFOEmptyThreshold;
}SPI_InitTypeDef;
/**
* @brief Texas Instruments Synchronous Serial Protocol (SSP) Init structure definition
*/
typedef struct
{
uint32_t SSP_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint32_t SSP_DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint32_t SSP_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint32_t SSP_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint32_t SSP_RXFIFOFullThreshold;
uint32_t SSP_TXFIFOEmptyThreshold;
}SSP_InitTypeDef;
/**
* @brief National Semiconductor Microwire (NSM) Init structure definition
*/
typedef struct
{
uint32_t NSM_Direction;
uint32_t NSM_TransferMode;
uint32_t NSM_DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint32_t NSM_ControlDataSize;
uint32_t NSM_NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint32_t NSM_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
FunctionalState NSM_HandShakingCmd;
uint32_t NSM_RXFIFOFullThreshold;
uint32_t NSM_TXFIFOEmptyThreshold;
}NSM_InitTypeDef;
/**
* @brief SPI DMA Init structure definition
*/
typedef struct
{
uint32_t SPI_DMAReq;
uint32_t SPI_DMAReceiveLevel;
uint32_t SPI_DMATransmitLevel;
FunctionalState SPI_DMAEnCmd;
}SPI_DMAInitTypeDef;
/** @defgroup SPI_data_direction
* @{
*/
#define SPI_Direction_2Lines_FullDuplex ((uint32_t)0x0000)
#define SPI_Direction_1Line_Tx ((uint32_t)0x0100)
#define SPI_Direction_1Line_Rx ((uint32_t)0x0200)
#define SPI_Direction_EEPROM_Read ((uint32_t)0x0300)
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
((MODE) == SPI_Direction_1Line_Tx) || \
((MODE) == SPI_Direction_1Line_Rx) || \
((MODE) == SPI_Direction_EEPROM_Read))
/**
* @}
*/
#define SPI_Mode_Master ((uint32_t)0x0001)
#define SPI_Mode_Slave ((uint32_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
((MODE) == SPI_Mode_Slave))
/** @defgroup SPI_data_size
* @{
*/
#define SPI_DataSize_8b ((uint32_t)0x0007)
#define SPI_DataSize_16b ((uint32_t)0x000F)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
((DATASIZE) == SPI_DataSize_8b))
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity
* @{
*/
#define SPI_CPOL_Low ((uint32_t)0x0000)
#define SPI_CPOL_High ((uint32_t)0x0080)
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
((CPOL) == SPI_CPOL_High))
/**
* @}
*/
/** @defgroup SPI_Clock_Phase
* @{
*/
#define SPI_CPHA_1Edge ((uint32_t)0x0000)
#define SPI_CPHA_2Edge ((uint32_t)0x0040)
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
((CPHA) == SPI_CPHA_2Edge))
/**
* @}
*/
#define SPI_NSS_0 ((uint32_t)0x0001)
#define SPI_NSS_Null ((uint32_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_0) || \
((NSS) == SPI_NSS_Null))
/** @defgroup SPI_BaudRate_Prescaler
* @{
*/
#define SPI_BaudRatePrescaler_2 ((uint32_t)0x0002)
#define SPI_BaudRatePrescaler_4 ((uint32_t)0x0004)
#define SPI_BaudRatePrescaler_8 ((uint32_t)0x0008)
#define SPI_BaudRatePrescaler_16 ((uint32_t)0x0010)
#define SPI_BaudRatePrescaler_32 ((uint32_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint32_t)0x0040)
#define SPI_BaudRatePrescaler_128 ((uint32_t)0x0080)
#define SPI_BaudRatePrescaler_256 ((uint32_t)0x0100)
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
((PRESCALER) == SPI_BaudRatePrescaler_256))
/**
* @}
*/
/** @defgroup SPI_RXFIFOFullThreshold
* @{
*/
#define SPI_RXFIFOFullThreshold_1 ((uint32_t)0x0000)
#define SPI_RXFIFOFullThreshold_2 ((uint32_t)0x0001)
#define SPI_RXFIFOFullThreshold_3 ((uint32_t)0x0002)
#define SPI_RXFIFOFullThreshold_4 ((uint32_t)0x0003)
#define SPI_RXFIFOFullThreshold_5 ((uint32_t)0x0004)
#define SPI_RXFIFOFullThreshold_6 ((uint32_t)0x0005)
#define SPI_RXFIFOFullThreshold_7 ((uint32_t)0x0006)
#define SPI_RXFIFOFullThreshold_8 ((uint32_t)0x0007)
#define SPI_RXFIFOFullThreshold_9 ((uint32_t)0x0008)
#define SPI_RXFIFOFullThreshold_10 ((uint32_t)0x0009)
#define SPI_RXFIFOFullThreshold_11 ((uint32_t)0x000A)
#define SPI_RXFIFOFullThreshold_12 ((uint32_t)0x000B)
#define SPI_RXFIFOFullThreshold_13 ((uint32_t)0x000C)
#define SPI_RXFIFOFullThreshold_14 ((uint32_t)0x000D)
#define SPI_RXFIFOFullThreshold_15 ((uint32_t)0x000E)
#define SPI_RXFIFOFullThreshold_16 ((uint32_t)0x000F)
#define IS_SPI_RX_FIFO_FULL_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RXFIFOFullThreshold_1) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_2) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_3) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_4) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_5) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_6) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_7) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_8) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_9) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_10) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_11) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_12) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_13) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_14) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_15) || \
((THRESHOLD) == SPI_RXFIFOFullThreshold_16))
/**
* @}
*/
/** @defgroup SPI_TXFIFOEmptyThreshold
* @{
*/
#define SPI_TXFIFOEmptyThreshold_0 ((uint32_t)0x0000)
#define SPI_TXFIFOEmptyThreshold_1 ((uint32_t)0x0001)
#define SPI_TXFIFOEmptyThreshold_2 ((uint32_t)0x0002)
#define SPI_TXFIFOEmptyThreshold_3 ((uint32_t)0x0003)
#define SPI_TXFIFOEmptyThreshold_4 ((uint32_t)0x0004)
#define SPI_TXFIFOEmptyThreshold_5 ((uint32_t)0x0005)
#define SPI_TXFIFOEmptyThreshold_6 ((uint32_t)0x0006)
#define SPI_TXFIFOEmptyThreshold_7 ((uint32_t)0x0007)
#define SPI_TXFIFOEmptyThreshold_8 ((uint32_t)0x0008)
#define SPI_TXFIFOEmptyThreshold_9 ((uint32_t)0x0009)
#define SPI_TXFIFOEmptyThreshold_10 ((uint32_t)0x000A)
#define SPI_TXFIFOEmptyThreshold_11 ((uint32_t)0x000B)
#define SPI_TXFIFOEmptyThreshold_12 ((uint32_t)0x000C)
#define SPI_TXFIFOEmptyThreshold_13 ((uint32_t)0x000D)
#define SPI_TXFIFOEmptyThreshold_14 ((uint32_t)0x000E)
#define SPI_TXFIFOEmptyThreshold_15 ((uint32_t)0x000F)
#define IS_SPI_TX_FIFO_EMPTY_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_TXFIFOEmptyThreshold_0) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_1) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_2) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_3) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_4) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_5) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_6) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_7) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_8) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_9) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_10) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_11) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_12) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_13) || \
((THRESHOLD) == SPI_TXFIFOEmptyThreshold_14) || \
((THRESHOLD) <= SPI_TXFIFOEmptyThreshold_15))
/**
* @}
*/
/** @defgroup SPI_DMAReceiveLevel
* @{
*/
#define SPI_DMAReceiveLevel_1 ((uint32_t)0x0000)
#define SPI_DMAReceiveLevel_2 ((uint32_t)0x0001)
#define SPI_DMAReceiveLevel_3 ((uint32_t)0x0002)
#define SPI_DMAReceiveLevel_4 ((uint32_t)0x0003)
#define SPI_DMAReceiveLevel_5 ((uint32_t)0x0004)
#define SPI_DMAReceiveLevel_6 ((uint32_t)0x0005)
#define SPI_DMAReceiveLevel_7 ((uint32_t)0x0006)
#define SPI_DMAReceiveLevel_8 ((uint32_t)0x0007)
#define SPI_DMAReceiveLevel_9 ((uint32_t)0x0008)
#define SPI_DMAReceiveLevel_10 ((uint32_t)0x0009)
#define SPI_DMAReceiveLevel_11 ((uint32_t)0x000A)
#define SPI_DMAReceiveLevel_12 ((uint32_t)0x000B)
#define SPI_DMAReceiveLevel_13 ((uint32_t)0x000C)
#define SPI_DMAReceiveLevel_14 ((uint32_t)0x000D)
#define SPI_DMAReceiveLevel_15 ((uint32_t)0x000E)
#define SPI_DMAReceiveLevel_16 ((uint32_t)0x000F)
#define IS_SPI_DMA_RECEIVE_LEVEL(LEVEL) ((((int32_t)(LEVEL)) >= SPI_DMAReceiveLevel_1) && \
(((int32_t)(LEVEL)) <= SPI_DMAReceiveLevel_16))
/**
* @}
*/
/** @defgroup SPI_DMATransmitLevel
* @{
*/
#define SPI_DMATransmitLevel_0 ((uint32_t)0x0000)
#define SPI_DMATransmitLevel_1 ((uint32_t)0x0001)
#define SPI_DMATransmitLevel_2 ((uint32_t)0x0002)
#define SPI_DMATransmitLevel_3 ((uint32_t)0x0003)
#define SPI_DMATransmitLevel_4 ((uint32_t)0x0004)
#define SPI_DMATransmitLevel_5 ((uint32_t)0x0005)
#define SPI_DMATransmitLevel_6 ((uint32_t)0x0006)
#define SPI_DMATransmitLevel_7 ((uint32_t)0x0007)
#define SPI_DMATransmitLevel_8 ((uint32_t)0x0008)
#define SPI_DMATransmitLevel_9 ((uint32_t)0x0009)
#define SPI_DMATransmitLevel_10 ((uint32_t)0x000A)
#define SPI_DMATransmitLevel_11 ((uint32_t)0x000B)
#define SPI_DMATransmitLevel_12 ((uint32_t)0x000C)
#define SPI_DMATransmitLevel_13 ((uint32_t)0x000D)
#define SPI_DMATransmitLevel_14 ((uint32_t)0x000E)
#define SPI_DMATransmitLevel_15 ((uint32_t)0x000F)
#define IS_SPI_DMA_TRANSMIT_LEVEL(LEVEL) ((((int32_t)(LEVEL)) >= SPI_DMATransmitLevel_0) && \
(((int32_t)(LEVEL)) <= SPI_DMATransmitLevel_15))
/**
* @}
*/
/** @defgroup SPI_DMA_transfer_requests
* @{
*/
#define SPI_DMAReq_Rx ((uint32_t)0x0001)
#define SPI_DMAReq_Tx ((uint32_t)0x0002)
#define IS_SPI_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFC) == (uint32_t)0x00) && \
((DMAREQ) != (uint32_t)0x00))
/**
* @}
*/
/** @defgroup SPI_Interrupt Mask and Status Flag
* @{
*/
#define SPI_IT_TXE ((uint32_t)0x0001) //clear by hardware
#define SPI_IT_TXOVF ((uint32_t)0x0002) //clear by read TXOICR register
#define SPI_IT_RXF ((uint32_t)0x0010) //clear by hardware
#define SPI_IT_RXOVF ((uint32_t)0x0008) //clear by read RXOICR register
#define SPI_IT_RXUDF ((uint32_t)0x0004) //clear by read RXURCR register
#define SPI_IT_MMC ((uint32_t)0x0020) //clear by read MSTICR register
#define SPI_IT_All ((uint32_t)0x002E)
#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TXE) || \
((IT) == SPI_IT_TXOVF) || \
((IT) == SPI_IT_RXF) || \
((IT) == SPI_IT_RXUDF) || \
((IT) == SPI_IT_RXOVF) || \
((IT) == SPI_IT_MMC))
#define SPI_FLAG_BSY ((uint32_t)0x0001)
#define SPI_FLAG_TXNF ((uint32_t)0x0002) //clear by hardware
#define SPI_FLAG_TXE ((uint32_t)0x0004) //clear by hardware
#define SPI_FLAG_RXNE ((uint32_t)0x0008) //clear by hardware
#define SPI_FLAG_RXF ((uint32_t)0x0010) //clear by hardware
#define SPI_FLAG_TXERR ((uint32_t)0x0020) //read clear
#define SPI_FLAG_DCERR ((uint32_t)0x0040) //read clear
#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_SR_RFNE) || \
((FLAG) == SPI_SR_RFF) || \
((FLAG) == SPI_SR_TFE) || \
((FLAG) == SPI_SR_TFNF) || \
((FLAG) == SPI_SR_BUSY))
/**
* @}
*/
/** @defgroup NSM_Direction
* @{
*/
#define NSM_Direction_Data_Transmit ((uint32_t)(0x0001))
#define NSM_Direction_Data_Receive ((uint32_t)(0x0002))
#define IS_NSM_DIRECTION_MODE(MODE) (((MODE) == NSM_Direction_Data_Transmit) || \
((MODE) == NSM_Direction_Data_Receive))
/**
* @}
*/
/** @defgroup NSM_TransferMode
* @{
*/
#define NSM_TransferMode_Non_Sequential ((uint32_t)(0x0001))
#define NSM_TransferMode_Sequential ((uint32_t)(0x0002))
#define IS_NSM_TRANSFER_MODE(MODE) (((MODE) == NSM_TransferMode_Non_Sequential) || \
((MODE) == NSM_TransferMode_Sequential))
/**
* @}
*/
/** @defgroup NSM_DataSize
* @{
*/
#define NSM_DataSize_8b ((uint32_t)0x0007)
#define NSM_DataSize_16b ((uint32_t)0x000F)
#define IS_NSM_DATASIZE(DATASIZE) (((DATASIZE) == NSM_DataSize_8b) || \
((DATASIZE) == NSM_DataSize_16b))
/**
* @}
*/
/** @defgroup NSM_ControlDataSize
* @{
*/
#define NSM_ControlDataSize_8b ((uint32_t)0x0007)
#define NSM_ControlDataSize_16b ((uint32_t)0x000F)
#define IS_NSM_CONTROL_DATASIZE(DATASIZE) (((DATASIZE) == NSM_ControlDataSize_8b) || \
((DATASIZE) == NSM_ControlDataSize_16b))
/**
* @}
*/
void SPI_DeInit(SPI_TypeDef* SPIx);
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
void SPI_DMAInit(SPI_TypeDef* SPIx, SPI_DMAInitTypeDef* SPI_DMAInitStruct);
void SPI_DMAStructInit(SPI_DMAInitTypeDef* SPI_DMAInitStruct);
void SPI_DMACmd(SPI_TypeDef* SPIx, uint32_t SPI_DMAReq, FunctionalState NewState);
void SPI_ITConfig(SPI_TypeDef* SPIx, uint32_t SPI_IT, FunctionalState NewState);
void SPI_SendData(SPI_TypeDef* SPIx, uint16_t Data);
uint16_t SPI_ReceiveData(SPI_TypeDef* SPIx);
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint32_t SPI_DataSize);
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint32_t SPI_Direction);
ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint32_t SPI_IT);
void SPI_ClearITPendingBit(SPI_TypeDef* SPIx, uint32_t SPI_IT);
FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint32_t SPI_FLAG);
uint32_t SPI_GetFlagStatusReg(SPI_TypeDef* SPIx);
FlagStatus SPI_IsBusy(SPI_TypeDef* SPIx);
FlagStatus SPI_IsTXErr(SPI_TypeDef* SPIx);
FlagStatus SPI_IsDataCollisionErr(SPI_TypeDef* SPIx);
void SSP_Init(SPI_TypeDef* SPIx, SSP_InitTypeDef* SSP_InitStruct);
void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct);
void NSM_Init(SPI_TypeDef* SPIx, NSM_InitTypeDef* NSM_InitStruct);
void NSM_StructInit(NSM_InitTypeDef* NSM_InitStruct);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /*__MSSCPU_SPI_H */
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_SSC_H
#define __AIR105_SSC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
#define SSC_ITSysXTAL12M BIT(18) //ϵͳ<CFB5><CDB3>12Mʱ<4D>ӱ<EFBFBD>־
#define SSC_ITSysGlitch BIT(17) //<2F><><EFBFBD><EFBFBD>Դë<D4B4>̱<EFBFBD>־
#define SSC_ITSysVolHigh BIT(16) //<2F><><EFBFBD><EFBFBD>Դ<EFBFBD><D4B4>ѹ<EFBFBD><D1B9>־
#define SSC_ITSysVolLow BIT(15) //<2F><><EFBFBD><EFBFBD>ԴǷѹ<C7B7><D1B9>־
typedef struct
{
FunctionalState ParityCheck; //<2F><>żУ<C5BC><D0A3>ʹ<EFBFBD><CAB9>
}SSC_InitTypeDef;
/*
* <EFBFBD><EFBFBD>BPK<EFBFBD><EFBFBD>Ϊ4<EFBFBD><EFBFBD>ÿ<EFBFBD><EFBFBD>256<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ϊ<EFBFBD><EFBFBD>λ<EFBFBD><EFBFBD><EFBFBD>ö<EFBFBD>дȨ<EFBFBD><EFBFBD>
* SSC_BPKAccessCtrBlock_0Ϊ<EFBFBD><EFBFBD>ʼ0<EFBFBD><EFBFBD>ַ<EFBFBD><EFBFBD>
*/
#define SSC_BPKAccessCtrBlock_0 (0x01)
#define SSC_BPKAccessCtrBlock_1 (0x02)
#define SSC_BPKAccessCtrBlock_All (0x03)
typedef enum
{
SSC_BPKReadOnly = 0x01, //BPK<50><4B>ֻ<EFBFBD><D6BB>
SSC_BPKWriteOnly = 0x02, //BPK<50><4B>ֻд
SSC_BPKReadWrite = 0x03 //BPK<50><4B><EFBFBD>д
}SSC_BPKAccessCtrlTypeDef;
#define IS_BPK_ACCESS_CTRL(CTRL) (((CTRL) == SSC_BPKReadOnly) || ((CTRL) == SSC_BPKWriteOnly) || \
((CTRL) == SSC_BPKReadWrite))
#define SSC_SENSOR_XTAL12M ((uint32_t)0x00000001)
#define SSC_SENSOR_VOL_LOW ((uint32_t)0x00000002)
#define SSC_SENSOR_VOL_HIGH ((uint32_t)0x00000004)
#define SSC_SENSOR_VOLGLITCH ((uint32_t)0x00000008)
#define IS_SSC_SENSOR(SENSOR) ((((SENSOR) & (uint32_t)0xFFFFFFF0) == 0x00) && ((SENSOR) != (uint32_t)0x00))
typedef enum
{
SSC_SENSOR_CPUReset = 0,
SSC_SENSOR_Interrupt = 1
}SSC_SENSOR_RespModeTypeDef;
#define IS_SSC_SENSOR_RESP_MODE(Mode) ((Mode) == SSC_SENSOR_CPUReset ||\
(Mode) == SSC_SENSOR_Interrupt)
/**
* @method SSC_Init
* @brief SSC<EFBFBD><EFBFBD>ȫ<EFBFBD><EFBFBD><EFBFBD>Գ<EFBFBD>ʼ<EFBFBD><EFBFBD>
* @param SSC_InitTypeDef SSC_InitStruct
* @retval void
*/
void SSC_Init(SSC_InitTypeDef *SSC_InitStruct);
/**
* @method SSC_GetITStatus
* @brief SSC<EFBFBD><EFBFBD>ȫ<EFBFBD>ж<EFBFBD>״̬
* @param uint32_t SSC_IT
* @retval ITStatus
*/
ITStatus SSC_GetITStatus(uint32_t SSC_IT);
/**
* @method SSC_ClearITPendingBit
* @brief SSC<EFBFBD><EFBFBD>ȫ<EFBFBD>ж<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param uint32_t SSC_IT
* @retval void
*/
void SSC_ClearITPendingBit( uint32_t SSC_IT);
/**
* @method SSC_SetDataRAMScrambler
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>RAM<EFBFBD><EFBFBD><EFBFBD><EFBFBD>
* @param uint32_t Scrambler
* @retval void
*/
void SSC_SetDataRAMScrambler(uint32_t Scrambler);
/**
* @method SSC_BPKAccessCtrConfig
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>BPK<EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ȩ<EFBFBD><EFBFBD>
* @param uint32_t SSC_BPKAccessCtrBlock
* @param SSC_BPKAccessCtrlTypeDef SSC_BPKAccessCtr
* @retval void
*/
void SSC_BPKAccessCtrlConfig(uint32_t SSC_BPKAccessCtrBlock, SSC_BPKAccessCtrlTypeDef SSC_BPKAccessCtr);
/**
* @method SSC_SENSOR_Enable
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳSensor
* @param SSC_SENSOR
* @retval
*/
uint32_t SSC_SENSORCmd(uint32_t SSC_SENSOR, FunctionalState NewState);
/**
* @method SSC_SENSORLock
* @brief <EFBFBD><EFBFBD><EFBFBD><EFBFBD>ϵͳSensor<EFBFBD><EFBFBD><EFBFBD><EFBFBD>״̬
* @param SSC_SENSOR
* @retval
*/
void SSC_SENSORLock(uint32_t SSC_SENSOR);
/**
* @method SSC_SENSOR_AttackRespMode
* @brief ϵͳSensor<EFBFBD><EFBFBD>Ӧ<EFBFBD><EFBFBD>ʽ
* @param SSC_SENSOR_RespMode
* @retval
*/
void SSC_SENSORAttackRespMode(SSC_SENSOR_RespModeTypeDef SSC_SENSOR_RespMode);
void SSC_SENSORKeyClearCmd(uint32_t SSC_SENSOR, FunctionalState KeyClearEn);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_SYSCTRL_H
#define __AIR105_SYSCTRL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
#define SYSCTRL_FREQ_SEL_POWERMODE_Pos (24)
#define SYSCTRL_FREQ_SEL_POWERMODE_Mask (0x07 << SYSCTRL_FREQ_SEL_POWERMODE_Pos)
#define SYSCTRL_FREQ_SEL_POWERMODE_CLOSE_CPU (0x00 << SYSCTRL_FREQ_SEL_POWERMODE_Pos)
#define SYSCTRL_FREQ_SEL_POWERMODE_CLOSE_CPU_MEM (0x01 << SYSCTRL_FREQ_SEL_POWERMODE_Pos)
/** @defgroup SYSCTRL_Exported_Types
* @{
*/
typedef struct
{
uint32_t PLL_Frequency; /*!< returns PLL frequency expressed in Hz */
uint32_t CPU_Frequency; /*!< returns CPU frequency expressed in Hz */
uint32_t HCLK_Frequency; /*!< returns HCLK frequency expressed in Hz */
uint32_t PCLK_Frequency; /*!< returns PCLK frequency expressed in Hz */
}SYSCTRL_ClocksTypeDef;
typedef enum
{
SleepMode_CpuOff = 0, /*!< CPU Sleep */
SleepMode_DeepSleep, /*!< Deep Sleep */
SleepMode_Invalid
}SleepMode_TypeDef;
#define IS_ALL_SLEEP_MODE(MODE) ((MODE) < SleepMode_Invalid)
typedef enum
{
SELECT_EXT12M,
SELECT_INC12M
} SYSCLK_SOURCE_TypeDef;
#define IS_SYSCLK_SOURCE(FREQ) (((FREQ) == SELECT_EXT12M) || \
((FREQ) == SELECT_INC12M))
typedef enum
{
SYSCTRL_PLL_108MHz = (uint32_t)0x01,
SYSCTRL_PLL_120MHz = (uint32_t)0x02,
SYSCTRL_PLL_132MHz = (uint32_t)0x03,
SYSCTRL_PLL_144MHz = (uint32_t)0x04,
SYSCTRL_PLL_156MHz = (uint32_t)0x05,
SYSCTRL_PLL_168MHz = (uint32_t)0x06,
SYSCTRL_PLL_180MHz = (uint32_t)0x07,
SYSCTRL_PLL_192MHz = (uint32_t)0x08,
SYSCTRL_PLL_204MHz = (uint32_t)0x09
}SYSCTRL_PLL_TypeDef;
#define IS_PLL_FREQ(FREQ) (((FREQ) == SYSCTRL_PLL_108MHz) || \
((FREQ) == SYSCTRL_PLL_120MHz) || \
((FREQ) == SYSCTRL_PLL_132MHz) || \
((FREQ) == SYSCTRL_PLL_144MHz) || \
((FREQ) == SYSCTRL_PLL_156MHz) || \
((FREQ) == SYSCTRL_PLL_168MHz) || \
((FREQ) == SYSCTRL_PLL_180MHz) || \
((FREQ) == SYSCTRL_PLL_192MHz) || \
((FREQ) == SYSCTRL_PLL_204MHz))
/**
* @}
*/
#define SYSCTRL_PLL_Div_None ((uint32_t)0x00)
#define SYSCTRL_PLL_Div2 ((uint32_t)0x01)
#define SYSCTRL_PLL_Div4 ((uint32_t)0x10)
#define IS_GET_SYSCTRL_PLL_DIV(DIV) (((DIV) == SYSCTRL_PLL_Div_None) || \
((DIV) == SYSCTRL_PLL_Div2) || \
((DIV) == SYSCTRL_PLL_Div4))
#define SYSCTRL_HCLK_Div_None ((uint32_t)0x00)
#define SYSCTRL_HCLK_Div2 ((uint32_t)0x01)
#define IS_GET_SYSCTRL_HCLK_DIV(DIV) (((DIV) == SYSCTRL_HCLK_Div_None) || \
((DIV) == SYSCTRL_HCLK_Div2))
#define SYSCTRL_PCLK_Div2 ((uint32_t)0x01)
#define SYSCTRL_PCLK_Div4 ((uint32_t)0x02)
#define IS_GET_SYSCTRL_PCLK_DIV(DIV) (((DIV) == SYSCTRL_PCLK_Div2) || \
((DIV) == SYSCTRL_PCLK_Div4))
#define SYSCTRL_CHIP_SN_ADDR ((uint32_t)0x40008804)
#define SYSCTRL_CHIP_SN_LEN ((uint32_t)0x10)
#define SYSCTRL_USB_DOWNLOAD_FLAG ((uint32_t)0X55)
void SYSCTRL_AHBPeriphClockCmd(uint32_t SYSCTRL_AHBPeriph, FunctionalState NewState);
void SYSCTRL_AHBPeriphResetCmd(uint32_t SYSCTRL_AHBPeriph, FunctionalState NewState);
void SYSCTRL_APBPeriphClockCmd(uint32_t SYSCTRL_APBPeriph, FunctionalState NewState);
void SYSCTRL_APBPeriphResetCmd(uint32_t SYSCTRL_APBPeriph, FunctionalState NewState);
void SYSCTRL_EnterSleep(SleepMode_TypeDef SleepMode);
void SYSCTRL_SYSCLKSourceSelect(SYSCLK_SOURCE_TypeDef source_select);
void SYSCTRL_PLLConfig(SYSCTRL_PLL_TypeDef PLL_Freq);
void SYSCTRL_PLLDivConfig(uint32_t PLL_Div);
void SYSCTRL_HCLKConfig(uint32_t HCLK_Div);
void SYSCTRL_PCLKConfig(uint32_t PCLK_Div);
void SYSCTRL_GetClocksFreq(SYSCTRL_ClocksTypeDef* SYSCTRL_Clocks);
void SYSCTRL_GetChipSN(unsigned char *ChipSN);
void SYSCTRL_SoftReset(void);
void SYSCTRL_EnterUSBDownload(void);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_TIMER_H
#define __AIR105_TIMER_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/* Exported types ------------------------------------------------------------*/
typedef enum
{
TIM_0 = 0,
TIM_1,
TIM_2,
TIM_3,
TIM_4,
TIM_5,
TIM_6,
TIM_7,
}TIM_NumTypeDef;
typedef struct
{
TIM_NumTypeDef TIMx;
uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFFFFFF. */
}TIM_InitTypeDef;
typedef struct
{
TIM_NumTypeDef TIMx;
uint32_t TIM_LowLevelPeriod;
uint32_t TIM_HighLevelPeriod;
}TIM_PWMInitTypeDef;
typedef enum
{
TIM_Mode_General = 0,
TIM_Mode_PWM = 1
}TIM_ModeTypeDef;
#define IS_TIM_MODE(MODE) (MODE == TIM_Mode_General || MODE == TIM_Mode_PWM)
void TIM_DeInit(TIM_Module_TypeDef *TIMMx);
void TIM_Init(TIM_Module_TypeDef* TIMMx, TIM_InitTypeDef* TIM_InitStruct);
void TIM_PWMInit(TIM_Module_TypeDef* TIMMx, TIM_PWMInitTypeDef* TIM_PWMInitStruct);
void TIM_Cmd(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx, FunctionalState NewState);
void TIM_ModeConfig(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx, TIM_ModeTypeDef TIM_Mode);
void TIM_SetPeriod(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx, uint32_t Period);
void TIM_SetPWMPeriod(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx, uint32_t PWM_LowLevelPeriod, uint32_t PWM_HighLevelPeriod);
void TIM_ITConfig(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx, FunctionalState NewState);
void TIM_ClearITPendingBit(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx);
void TIM_PWMSinglePulseConfig(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx, FunctionalState NewState);
void TIM_PWMReloadSinglePulse(TIM_Module_TypeDef *TIMMx, TIM_NumTypeDef TIMx);
ITStatus TIM_GetITStatus(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx);
uint32_t TIM_GetAllITStatus(TIM_Module_TypeDef* TIMMx);
ITStatus TIM_GetRawITStatus(TIM_Module_TypeDef* TIMMx, TIM_NumTypeDef TIMx);
uint32_t TIM_GetAllRawITStatus(TIM_Module_TypeDef* TIMMx);
uint32_t TIM_GetCounter(TIM_Module_TypeDef *TIMMx, TIM_NumTypeDef TIMx);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_TRNG_H
#define __AIR105_TRNG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/** @defgroup RNG_Exported_Types
* @{
*/
typedef enum{
TRNG0
} TRNG_ChannelTypeDef;
#define IS_TRNG_CHANNEL(CHANNEL) (((CHANNEL) == TRNG0))
#define TRNG_IT_RNG0_S128 ((uint32_t)0x00000001)
#define TRNG_IT_RNG0_ATTACK ((uint32_t)0x00000004)
#define IS_TRNG_GET_IT(IT) (((IT) == TRNG_IT_RNG0_S128) || \
((IT) == TRNG_IT_RNG0_ATTACK))
/** @defgroup RNG_Exported_Functions
* @{
*/
void TRNG_Start(TRNG_ChannelTypeDef TRNGx);
void TRNG_Stop(TRNG_ChannelTypeDef TRNGx);
uint32_t TRNG_Get(uint32_t rand[4], TRNG_ChannelTypeDef TRNGx);
void TRNG_SetPseudoRandom(uint32_t PseudoRandom);
void TRNG_DirectOutANA(TRNG_ChannelTypeDef TRNGx, FunctionalState NewState);
void TRNG_ITConfig(FunctionalState NewState);
ITStatus TRNG_GetITStatus(uint32_t TRNG_IT);
void TRNG_ClearITPendingBit(uint32_t TRNG_IT);
#ifdef __cplusplus
}
#endif
#endif
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_UART_H
#define __AIR105_UART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
/**
* @brief UART Init Structure definition
*/
typedef struct
{
uint32_t UART_BaudRate; /*!< This member configures the UART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (UART_InitStruct->UART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint32_t UART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref UART_Word_Length */
uint32_t UART_StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref UART_Stop_Bits */
uint32_t UART_Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref UART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
} UART_InitTypeDef;
/**
* @}
*/
#define IS_UART_PERIPH(PERIPH) (((PERIPH) == UART0) || \
((PERIPH) == UART1) || \
((PERIPH) == UART2) || \
((PERIPH) == UART3))
/**
* @brief UART FIFO Init Structure definition
*/
typedef struct
{
FunctionalState FIFO_Enable;
uint32_t FIFO_DMA_Mode;
uint32_t FIFO_RX_Trigger;
uint32_t FIFO_TX_Trigger;
uint32_t FIFO_TX_TriggerIntEnable;
}UART_FIFOInitTypeDef;
/**
* @}
*/
/** @defgroup UART_Word_Length
* @{
*/
#define UART_WordLength_5b (0x00000000)
#define UART_WordLength_6b (0x00000001)
#define UART_WordLength_7b (0x00000002)
#define UART_WordLength_8b (0x00000003)
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_5b) || \
((LENGTH) == UART_WordLength_6b) || \
((LENGTH) == UART_WordLength_7b) || \
((LENGTH) == UART_WordLength_8b))
/**
* @}
*/
/** @defgroup UART_Stop_Bits
* @{
*/
#define UART_StopBits_1 (0x00000000)
#define UART_StopBits_1_5 (0x00000004)
#define UART_StopBits_2 (0x00000004)
#define IS_UART_STOPBITS(STOPBITS, DATALENGTH) (((STOPBITS) == UART_StopBits_1) || \
((STOPBITS) == UART_StopBits_1_5 && DATALENGTH == UART_WordLength_5b) || \
((STOPBITS) == UART_StopBits_2 && DATALENGTH != UART_WordLength_5b))
/**
* @}
*/
/** @defgroup UART_Parity
* @{
*/
#define UART_Parity_No (0x00000000)
#define UART_Parity_Even (0x00000018)
#define UART_Parity_Odd (0x00000008)
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
((PARITY) == UART_Parity_Even) || \
((PARITY) == UART_Parity_Odd))
/**
* @}
*/
/** @defgroup UART_Mode
* @{
*/
#define UART_Mode_Rx ((uint16_t)0x0001)
#define UART_Mode_Tx ((uint16_t)0x0002)
#define IS_UART_MODE(MODE) ((((MODE) & (uint16_t)0xFFFC) == 0x00) && ((MODE) != (uint16_t)0x00))
/**
* @}
*/
/** @defgroup UART_Set_Check_define
* @{
*/
#define IS_UART_DATA(DATA) ((DATA) <= 0x000001FF)
#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))
/**
* @}
*/
/** @defgroup UART_Interrupt_definition
* @{
*/
#define UART_IT_RX_RECVD (UART_IER_ERBFI)
#define UART_IT_TX_EMPTY (UART_IER_ETBEI)
#define UART_IT_LINE_STATUS (UART_IER_ELSI)
#define UART_IT_MODEM_STATUS (UART_IER_EDSSI)
/**
* @}
*/
/** @defgroup UART_Interrupt_identity
* @{
*/
#define UART_IT_ID_MODEM_STATUS ((uint32_t)0x0000)
#define UART_IT_ID_NO_INTERRUPT ((uint32_t)0x0001)
#define UART_IT_ID_TX_EMPTY ((uint32_t)0x0002)
#define UART_IT_ID_RX_RECVD ((uint32_t)0x0004)
#define UART_IT_ID_LINE_STATUS ((uint32_t)0x0006)
#define UART_IT_ID_BUSY_DETECT ((uint32_t)0x0007)
#define UART_IT_ID_CHAR_TIMEOUT ((uint32_t)0x000C)
/**
* @}
*/
/** @defgroup UART_FIFO_Control_define
* @{
*/
#define UART_FIFO_DEPTH (16)
#define UART_FIFO_RX ((uint32_t)0x0000)
#define UART_FIFO_TX ((uint32_t)0x0001)
#define UART_FIFO_DMA_Mode_0 ((uint32_t)0x0000)
#define UART_FIFO_DMA_Mode_1 ((uint32_t)0x0001)
#define UART_FIFO_RX_Trigger_1_Char ((uint32_t)0x0000)
#define UART_FIFO_RX_Trigger_1_4_Full ((uint32_t)0x0001)
#define UART_FIFO_RX_Trigger_1_2_Full ((uint32_t)0x0002)
#define UART_FIFO_RX_Trigger_2_CharLessFull ((uint32_t)0x0003)
#define UART_FIFO_TX_Trigger_Empty ((uint32_t)0x0000)
#define UART_FIFO_TX_Trigger_2_Chars ((uint32_t)0x0001)
#define UART_FIFO_TX_Trigger_1_4_Full ((uint32_t)0x0002)
#define UART_FIFO_TX_Trigger_1_2_Full ((uint32_t)0x0003)
/**
* @}
*/
/** @defgroup UART_Line_Status_Flag_define
* @{
*/
#define UART_LINE_STATUS_RX_RECVD (UART_LSR_DR)
#define UART_LINE_STATUS_RX_OVERRUN_ERROR (UART_LSR_OE)
#define UART_LINE_STATUS_RX_PARITY_ERROR (UART_LSR_PE)
#define UART_LINE_STATUS_RX_FRAMING_ERROR (UART_LSR_FE)
#define UART_LINE_STATUS_RX_BREAK_INTERRUPT (UART_LSR_BI)
#define UART_LINE_STATUS_TX_HOLDING_REGISTER_EMPTY (UART_LSR_THRE)
#define UART_LINE_STATUS_TX_EMPTY (UART_LSR_TEMT)
#define UART_LINE_STATUS_RX_FIFO_ERROR (UART_LSR_PFE)
/**
* @}
*/
/** @defgroup UART_Modem_Status_Flag_define
* @{
*/
#define UART_MODEM_STATUS_CTS_CHANGED (UART_MSR_DCTS)
#define UART_MODEM_STATUS_DSR_CHANGED (UART_MSR_DDSR)
#define UART_MODEM_STATUS_RI_CHANGED (UART_MSR_TERI)
#define UART_MODEM_STATUS_DCD_CHANGED (UART_MSR_DDCD)
#define UART_MODEM_STATUS_CTS (UART_MSR_CTS)
#define UART_MODEM_STATUS_DSR (UART_MSR_DSR)
#define UART_MODEM_STATUS_RI (UART_MSR_RI)
#define UART_MODEM_STATUS_DCD (UART_MSR_DCD)
/**
* @}
*/
/** @defgroup UART_Status_Flag_define
* @{
*/
#define UART_STATUS_BUSY (UART_USR_BUSY)
#define UART_STATUS_TX_FIFO_NOT_FULL (UART_USR_TFNF)
#define UART_STATUS_TX_FIFO_EMPTY (UART_USR_TFE)
#define UART_STATUS_RX_FIFO_NOT_EMPTY (UART_USR_RFNE)
#define UART_STATUS_RX_FIFO_FULL (UART_USR_RFF)
/**
* @}
*/
void UART_DeInit(UART_TypeDef* UARTx);
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
void UART_ITConfig(UART_TypeDef* UARTx, uint32_t UART_IT, FunctionalState NewState);
void UART_SendData(UART_TypeDef* UARTx, uint8_t Data);
uint8_t UART_ReceiveData(UART_TypeDef* UARTx);
void UART_FIFOInit(UART_TypeDef* UARTx, UART_FIFOInitTypeDef* UART_FIFOInitStruct);
void UART_FIFOStructInit(UART_FIFOInitTypeDef* UART_FIFOInitStruct);
void UART_FIFOReset(UART_TypeDef* UARTx, uint32_t UART_FIFO);
void UART_FIFOCmd(UART_TypeDef* UARTx,FunctionalState NewState);
void UART_SetRTS(UART_TypeDef* UARTx);
void UART_ResetRTS(UART_TypeDef* UARTx);
void UART_SetDTR(UART_TypeDef* UARTx);
void UART_ResetDTR(UART_TypeDef* UARTx);
void UART_SendBreak(UART_TypeDef* UARTx);
void UART_AutoFlowCtrlCmd(UART_TypeDef* UARTx, FunctionalState NewState);
void UART_IrDACmd(UART_TypeDef* UARTx, FunctionalState NewState);
uint32_t UART_GetLineStatus(UART_TypeDef* UARTx);
uint32_t UART_GetModemStatus(UART_TypeDef* UARTx);
uint32_t UART_GetITIdentity(UART_TypeDef* UARTx);
Boolean UART_IsTXEmpty(UART_TypeDef* UARTx);
Boolean UART_IsTXHoldingRegisterEmpty(UART_TypeDef* UARTx);
Boolean UART_IsRXFIFOFull(UART_TypeDef* UARTx);
Boolean UART_IsRXFIFONotEmpty(UART_TypeDef* UARTx);
Boolean UART_IsTXFIFOEmpty(UART_TypeDef* UARTx);
Boolean UART_IsTXFIFONotFull(UART_TypeDef* UARTx);
Boolean UART_IsBusy(UART_TypeDef* UARTx);
void UART_DMAGenerateSoftAck(UART_TypeDef* UARTx);
void UART_TXHaltCmd(UART_TypeDef* UARTx, FunctionalState NewStatus);
void UART_FIFOAccessModeCmd(UART_TypeDef* UARTx, FunctionalState NewStatus);
uint8_t UART_FIFOTxRead(UART_TypeDef* UARTx);
#ifdef __cplusplus
}
#endif
#endif // __AIR105_UART_H
/************************** (C) COPYRIGHT Megahunt *****END OF FILE****/

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __AIR105_WDT_H
#define __AIR105_WDT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
typedef enum
{
WDT_Mode_CPUReset = 0,
WDT_Mode_Interrupt = 1
}WDT_ModeTypeDef;
void WDT_SetReload(uint32_t Reload);
void WDT_ReloadCounter(void);
void WDT_Enable(void);
void WDT_ModeConfig(WDT_ModeTypeDef WDT_Mode);
ITStatus WDT_GetITStatus(void);
void WDT_ClearITPendingBit(void);
#ifdef __cplusplus
}
#endif
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __APP_INC_H__
#define __APP_INC_H__
#include "bl_inc.h"
#include "core_hwtimer.h"
#include "core_spi.h"
#include "core_adc.h"
#include "core_dac.h"
#include "core_wdt.h"
#include "core_usb_ll_driver.h"
#include "core_keyboard.h"
#include "core_dcmi.h"
#include "core_rng.h"
#endif

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __BL_INC_H__
#define __BL_INC_H__
#include "global_config.h"
#include "air105.h"
#include "air105_conf.h"
#include "bsp_common.h"
#include "platform_define.h"
#include "resource_map.h"
#include "core_dma.h"
#include "core_tick.h"
#include "core_debug.h"
#include "core_flash.h"
#include "core_gpio.h"
#include "core_timer.h"
#include "core_otp.h"
#include "core_uart.h"
#include "core_rtc.h"
#include "core_i2c.h"
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __BSP_COMMON_H__
#define __BSP_COMMON_H__
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <stdarg.h>
#include "cmsis_gcc.h"
typedef struct
{
uint32_t param_max_num;
uint32_t param_max_len;
uint32_t param_num;
int8_t *param_str;
}CmdParam;
typedef struct
{
uint8_t Sec;
uint8_t Min;
uint8_t Hour;
uint8_t Week;//表示日期0~6,sun~sat，表示预约时，bit0~bit6,sun~sat
}Time_UserDataStruct;
typedef struct
{
uint16_t Year;
uint8_t Mon;
uint8_t Day;
}Date_UserDataStruct;
typedef union
{
uint32_t dwTime;
Time_UserDataStruct Time;
}Time_Union;
typedef union
{
uint32_t dwDate;
Date_UserDataStruct Date;
}Date_Union;
typedef struct
{
uint8_t *Data;
uint32_t Len;
uint32_t Offset;
uint32_t MaxLength;
uint32_t DataSize;
}Loop_Buffer;
typedef struct
{
uint8_t *Data;
uint32_t Pos;
uint32_t MaxLen;
}Buffer_Struct;
typedef union
{
void *p;
char *pc8;
uint8_t *pu8;
uint16_t *pu16;
uint32_t *pu32;
uint32_t u32;
uint8_t u8[4];
uint16_t u16[2];
}PV_Union;
enum
{
ERROR_NONE,
ERROR_NO_SUCH_ID,
ERROR_PERMISSION_DENIED,
ERROR_PARAM_INVALID,
ERROR_PARAM_OVERFLOW,
ERROR_DEVICE_BUSY,
ERROR_OPERATION_FAILED,
ERROR_BUFFER_FULL,
ERROR_NO_MEMORY,
ERROR_CMD_NOT_SUPPORT,
ERROR_NO_DATA,
ERROR_NO_FLASH,
ERROR_NO_TIMER,
ERROR_TIMEOUT,
ERROR_SSL_HANDSHAKE,
ERROR_PROTOCL,
ERROR_ID_INVALID,
ERROR_MID_INVALID,
ERROR_RETRY_TOO_MUCH,
ERROR_CMD_BLOCK,
LIST_FIND = 1,
LIST_PASS = 0,
LIST_DEL = -1,
DMA_CB_DONE = 0,
UART_CB_TX_BUFFER_DONE,
UART_CB_TX_ALL_DONE,
UART_CB_RX_NEW,
UART_CB_RX_TIMEOUT,
UART_CB_RX_BUFFER_FULL,
UART_CB_ERROR,
UART_CB_CONNECTED, //串口工具对方已经打开
DMA_CB_ERROR = 0xffffffff,
CORE_EVENT_ID_START = 0,
CORE_EVENT_ID_ANY = 0,
CORE_EVENT_TIMEOUT,
CORE_TIMER_TIMEOUT = 0x00010000,
SERVICE_EVENT_ID_START = 0x00100000,
USER_EVENT_ID_START = 0x10000000,
INVALID_EVENT_ID = 0xffffffff,
};
#define INVALID_HANDLE_VALUE ((void *)0xffffffff)
#define INVALID_PARAM (0xffffffff)
#define CRC32_GEN (0x04C11DB7)
#define CRC32_START (0xffffffff)
#define CRC16_CCITT_GEN (0x1021)
#define CRC16_MODBUS_GEN (0x8005)
#define CRC16_START (0xffff)
#define CRC16_IBM_SEED (0xffff)
#define CRC16_CCITT_SEED (0x1D0F)
#define HANDLE void *
#define MIN(X,Y) (((X) < (Y))?(X):(Y))
typedef void (* TaskFun_t)( void * );
typedef void(* CBDataFun_t)(uint8_t *Data, uint32_t Len);
typedef int32_t(*CBFuncEx_t)(void *pData, void *pParam);
typedef uint64_t LongInt;
typedef struct
{
CBFuncEx_t CB;
union {
void *pParam; //用户回调模式
uint32_t MaxCnt; //设置捕获模式时的最大tick，捕获时的tick
}uParam;
union {
struct {
uint8_t Level; //IO输入输出电平，捕获模式下中断时IO电平
uint8_t PullMode; //IO上下拉控制
} IOArg;
struct {
uint8_t ExtiMode; //中断模式
uint8_t PullMode; //IO上下拉控制
} ExitArg;
uint16_t Time; //delay时间，us
} uArg;
uint8_t Operation; //操作类型
uint8_t Arg1; //IO操作时为IOpin，delay操作时则为微调值，0~47，48为1us
}OPQueue_CmdStruct;
__attribute__((weak)) uint8_t OS_CheckInIrq(void);
uint32_t OS_EnterCritical(void);
void OS_ExitCritical(uint32_t Critical);
void *OS_Malloc(uint32_t Size);
void *OS_Zalloc(uint32_t Size);
void OS_Free(void *p);
void *OS_Realloc(void *buf, uint32_t size);
void OS_MemInfo(uint32_t *curalloc, uint32_t *totfree, uint32_t *maxfree);
int32_t OS_InitBuffer(Buffer_Struct *Buf, uint32_t Size);
void OS_DeInitBuffer(Buffer_Struct *Buf);
int32_t OS_ReInitBuffer(Buffer_Struct *Buf, uint32_t Size);
int32_t OS_ReSizeBuffer(Buffer_Struct *Buf, uint32_t Size);
int32_t OS_BufferWrite(Buffer_Struct *Buf, void *Data, uint32_t Len);
int32_t OS_BufferWriteLimit(Buffer_Struct *Buf, void *Data, uint32_t Len);
void OS_BufferRemove(Buffer_Struct *Buf, uint32_t Len);
void Buffer_StaticInit(Buffer_Struct *Buf, void *Src, uint32_t MaxLen);
int32_t Buffer_StaticWrite(Buffer_Struct *Buf, void *Data, uint32_t Len);
void Buffer_Remove(Buffer_Struct *Buf, uint32_t Len);
void LoopBuffer_Init(Loop_Buffer *Buf, void *Src, uint32_t MaxLen, uint32_t DataSize);
uint32_t LoopBuffer_Query(Loop_Buffer *Buf, void *Src, uint32_t Len);
uint32_t LoopBuffer_Read(Loop_Buffer *Buf, void *Src, uint32_t Len);
void LoopBuffer_Del(Loop_Buffer *Buf, uint32_t Len);
uint32_t LoopBuffer_Write(Loop_Buffer *Buf, void *Src, uint32_t Len);
int32_t BSP_SetBit(uint8_t *Data, uint32_t Sn, uint8_t Value);
int32_t BSP_GetBit(uint8_t *Data, uint32_t Sn, uint8_t *Value);
uint8_t BSP_TestBit(uint8_t *Data, uint32_t Sn);
uint8_t XorCheck(void *Src, uint32_t Len, uint8_t CheckStart);
uint8_t SumCheck(uint8_t *Data, uint32_t Len);
uint16_t CRC16Cal(void *Data, uint16_t Len, uint16_t CRC16Last, uint16_t CRCRoot, uint8_t IsReverse);
uint32_t AsciiToU32(uint8_t *Src, uint32_t Len);
void CRC32_CreateTable(uint32_t *Tab, uint32_t Gen);
uint32_t CRC32_Cal(uint32_t * CRC32_Table, uint8_t *Buf, uint32_t Size, uint32_t CRC32Last);
uint32_t CmdParseParam(int8_t* pStr, CmdParam *CmdParam, int8_t Cut);
uint8_t IsLeapYear(uint32_t Year);
LongInt UTC2Tamp(Date_UserDataStruct *Date, Time_UserDataStruct *Time);
uint32_t Tamp2UTC(LongInt Sec, Date_UserDataStruct *Date, Time_UserDataStruct *Time, uint32_t LastDDay);
/*
* 转义解包
* 标识Flag，即包头包尾加入Flag
* 数据中遇到Code F1 -> Flag
* 数据中遇到Code F2 -> Code
* 数据中遇到Flag 出错返回0
*/
uint32_t TransferUnpack(uint8_t Flag, uint8_t Code, uint8_t F1, uint8_t F2, uint8_t *InBuf, uint32_t Len, uint8_t *OutBuf);
/*
* llist相关代码，大部分来自linux内核
*/
/**
* container_of - cast a member of a structure out to the containing structure
*
* @ptr: the pointer to the member.
* @type: the type of the container struct this is embedded in.
* @member: the name of the member within the struct.
*
*/
#define container_of(ptr, type, member) ({ \
const typeof( ((type *)0)->member ) *__mptr = (ptr); \
(type *)( (char *)__mptr - offsetof(type,member) );})
/*
* These are non-NULL pointers that will result in page faults
* under normal circumstances, used to verify that nobody uses
* non-initialized llist entries.
*/
#define LLIST_POISON1 (0)
#define LLIST_POISON2 (0)
/*
* Simple doubly linked llist implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole llists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
typedef struct llist_head_t{
struct llist_head_t *next, *prev;
}llist_head;
#define LLIST_HEAD_INIT(name) { &(name), &(name) }
#define LLIST_HEAD(name) \
llist_head name = LLIST_HEAD_INIT(name)
#define INIT_LLIST_HEAD(ptr) do { \
(ptr)->next = (ptr); (ptr)->prev = (ptr); \
} while (0)
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal llist manipulation where we know
* the prev/next entries already!
*/
void __llist_add(llist_head *p,
llist_head *prev,
llist_head *next);
/**
* llist_add - add a new entry
* @new: new entry to be added
* @head: llist head to add it after
*
* Insert a new entry after the specified head.
* This is good for implementing stacks.
*/
void llist_add(llist_head *p, llist_head *head);
/**
* llist_add_tail - add a new entry
* @new: new entry to be added
* @head: llist head to add it before
*
* Insert a new entry before the specified head.
* This is useful for implementing queues.
*/
void llist_add_tail(llist_head *p, llist_head *head);
/*
* Delete a llist entry by making the prev/next entries
* point to each other.
*
* This is only for internal llist manipulation where we know
* the prev/next entries already!
*/
void __llist_del(llist_head * prev, llist_head * next);
/**
* llist_del - deletes entry from llist.
* @entry: the element to delete from the llist.
* Note: llist_empty on entry does not return true after this, the entry is
* in an undefined state.
*/
void llist_del(llist_head *entry);
/**
* llist_del_init - deletes entry from llist and reinitialize it.
* @entry: the element to delete from the llist.
*/
void llist_del_init(llist_head *entry);
/**
* llist_move - delete from one llist and add as another's head
* @llist: the entry to move
* @head: the head that will precede our entry
*/
void llist_move(llist_head *llist, llist_head *head);
/**
* llist_move_tail - delete from one llist and add as another's tail
* @llist: the entry to move
* @head: the head that will follow our entry
*/
void llist_move_tail(llist_head *llist,
llist_head *head);
/**
* llist_empty - tests whether a llist is empty
* @head: the llist to test.
*/
int llist_empty(const llist_head *head);
uint32_t llist_num(const llist_head *head);
void *llist_traversal(llist_head *head, CBFuncEx_t cb, void *pData);
/**
* llist_entry - get the struct for this entry
* @ptr: the &llist_head pointer.
* @type: the type of the struct this is embedded in.
* @member: the name of the llist_struct within the struct.
*/
#define llist_entry(ptr, type, member) \
container_of(ptr, type, member)
uint8_t BytesGet8(const void *ptr);
void BytesPut8(void *ptr, uint8_t v);
uint16_t BytesGetBe16(const void *ptr);
void BytesPutBe16(void *ptr, uint16_t v);
uint32_t BytesGetBe32(const void *ptr);
void BytesPutBe32(void *ptr, uint32_t v);
uint16_t BytesGetLe16(const void *ptr);
void BytesPutLe16(void *ptr, uint16_t v);
uint32_t BytesGetLe32(const void *ptr);
void BytesPutLe32(void *ptr, uint32_t v);
uint64_t BytesGetLe64(const void *ptr);
void BytesPutLe64(void *ptr, uint64_t v);
uint8_t BytesGet8FromBuf(Buffer_Struct *Buf);
void BytesPut8ToBuf(Buffer_Struct *Buf, uint8_t v);
uint16_t BytesGetBe16FromBuf(Buffer_Struct *Buf);
void BytesPutBe16ToBuf(Buffer_Struct *Buf, uint16_t v);
uint32_t BytesGetBe32FromBuf(Buffer_Struct *Buf);
void BytesPutBe32ToBuf(Buffer_Struct *Buf, uint32_t v);
uint16_t BytesGetLe16FromBuf(Buffer_Struct *Buf);
void BytesPutLe16ToBuf(Buffer_Struct *Buf, uint16_t v);
uint32_t BytesGetLe32FromBuf(Buffer_Struct *Buf);
void BytesPutLe32ToBuf(Buffer_Struct *Buf, uint32_t v);
uint64_t BytesGetLe64FromBuf(Buffer_Struct *Buf);
void BytesPutLe64ToBuf(Buffer_Struct *Buf, uint64_t v);
float BytesGetFloatFromBuf(Buffer_Struct *Buf);
void BytesPutFloatToBuf(Buffer_Struct *Buf, float v);
double BytesGetDoubleFromBuf(Buffer_Struct *Buf);
void BytesPutDoubleToBuf(Buffer_Struct *Buf, double v);
/*************************************************************************/
#define malloc OS_Malloc
#define free OS_Free
#define realloc OS_Realloc
#define zalloc OS_Zalloc
#define calloc OS_Calloc
#endif

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_ADC_H__
#define __CORE_ADC_H__
#define ADC_VALUE_ERROR (0xffffffff)
void ADC_GlobalInit(void);
/**
* @brief 通道开关，在globalinit时只打开了0，0也无法被关闭，目前已经废弃，ADC_GetChannelValue的时候临时打开
*
* @param Channel 通道号
* @param OnOff 开关
*/
void ADC_ChannelOnOff(uint8_t Channel, uint8_t OnOff);
/**
* @brief 获取通道的原始ADC值，12bit，1.8V参考电压，通道0内部9:5分压，其他关闭
*
* @param Channel 通道号
* @return != ADC_VALUE_ERROR 为有效值
*/
uint32_t ADC_GetChannelValue(uint8_t Channel);
/**
* @brief 开关内部分压，1~5都是1:1 6就不确定了，手册和demo不一致
*
* @param OnOff 开关
*/
void ADC_IntelResistance(uint8_t OnOff);
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_DAC_H__
#define __CORE_DAC_H__
void DAC_Init(uint8_t Stream);
void DAC_Setup(uint32_t Freq, uint32_t OutRMode);
void DAC_Send(const uint16_t *Data, uint32_t Len, CBFuncEx_t Callback, void *pParam);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_DCMI_H__
#define __CORE_DCMI_H__
/**
* @brief 对摄像头做基本的初始化工作
*
* @param VsyncLevel 垂直同步极性 0： VSYNC 低电平有效 1： VSYNC 高电平有效
* @param HsyncLevel 水平同步极性 0： HSYNC 低电平有效 1： HSYNC 高电平有效
* @param PclkPOL Pixel时钟极性 0：下降沿有效 1：上升沿有效
* @param DataBits 数据位8~14
* @param FrameRate 帧率控制，0不控制，1减少为50%，2减少为25%
*/
void DCMI_Setup(uint8_t VsyncLevel, uint8_t HsyncLevel, uint8_t PclkPOL, uint8_t DataBit, uint32_t FrameRate);
/**
* @brief 摄像头捕获开关
*
* @param OnOff 0： 关 1： 开
* @param BufLen 缓存大小，注意单位是4byte，如果为0，看下面的参数自动生成，如果不为0，必须是行数据量的倍数，且能被总行数整除，比如320*240，16bit数据，那么就是320*2/4的N倍，比如8倍的1280
* @param ImageW 输出图像一行的像素点数
* @param ImageW 输出图像行数
* @param DataByte 1个像素点的数据量byte
* @param OutH 自动计算出的单次回调行数
*/
void DCMI_CaptureSwitch(uint8_t OnOff, uint32_t BufLen, uint32_t ImageW, uint32_t ImageH, uint8_t DataByte, uint32_t *OutH);
void DCMI_SetCallback(CBFuncEx_t CB, void *pData);
/**
* @brief 摄像头裁剪功能
*
* @param OnOff 0： 关 1： 开
* @param VStart 裁剪从第几行开始
* @param HStart 裁剪每行从第几个像素数据开始，如果是16bit数据，则要*2，依次类推
* @param VLen 裁剪保留的行数，最小1
* @param HLen 裁剪每行保留的像素数据，如果是16bit数据，则要*2，依次类推
*/
void DCMI_SetCROPConfig(uint8_t OnOff, uint32_t VStart, uint32_t HStart, uint32_t VLen, uint32_t HLen);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_DEBUG_H__
#define __CORE_DEBUG_H__
#include "stdint.h"
#include "bsp_common.h"
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_DMA_H__
#define __CORE_DMA_H__
enum
{
DMA1_STREAM_0,
DMA1_STREAM_1,
DMA1_STREAM_2,
DMA1_STREAM_3,
DMA1_STREAM_4,
DMA1_STREAM_5,
DMA1_STREAM_6,
DMA1_STREAM_7,
// DMA1_STREAM_QTY,
// DMA2_STREAM_0 = DMA1_STREAM_QTY,
// DMA2_STREAM_1,
// DMA2_STREAM_2,
// DMA2_STREAM_3,
// DMA2_STREAM_4,
// DMA2_STREAM_5,
// DMA2_STREAM_6,
// DMA2_STREAM_7,
DMA2_STREAM_QTY,
DMA_STREAM_QTY = DMA2_STREAM_QTY,
};
void DMA_GlobalInit(void);
void *DMA_TakeStream(uint8_t Stream);
int DMA_CheckStreamLock(uint8_t Stream);
void DMA_ReleaseStream(uint8_t Stream);
uint8_t DMA_CheckStreamBusy(uint8_t Stream);
int DMA_ConfigStream(uint8_t Stream, void *Config);
int DMA_StartStream(uint8_t Stream, const void *Data, uint32_t Len, CBFuncEx_t CB, void *pUserData, uint8_t NeedIrq);
/**
* @brief 强制启动DMA传输
* @param Stream DMA流序号
* @param Data DMA缓存
* @param Len DMA缓存长度
* @param CB 完成或者出错回调。完成时，回调函数参数pParam为0，出错为0xffffffff
* @param NeedIrq 是否需要中断
* @return 无
*/
void DMA_ForceStartStream(uint8_t Stream, const void *Data, uint32_t Len, CBFuncEx_t CB, void *pUserData, uint8_t NeedIrq);
void DMA_ClearStreamFlag(uint8_t Stream);
void DMA_StopStream(uint8_t Stream);
uint32_t DMA_GetRemainingDataLength(uint8_t Stream);
uint32_t DMA_GetDataLength(uint8_t Stream, uint32_t FirstAddress);
void DMA_BaseConfig(void *Config);
void DMA_PrintGlobalReg(void);
void DMA_PrintReg(uint8_t Stream);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_FLASH_H__
#define __CORE_FLASH_H__
int Flash_EraseSector(uint32_t address, uint8_t NeedCheck);
int Flash_ProgramData(uint32_t address, uint32_t *Data, uint32_t Len, uint8_t NeedCheck);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_GPIO_H__
#define __CORE_GPIO_H__
#include "bsp_common.h"
/**
* @brief GPIO全局初始化
*
* @param Fun 中断回调函数，回调时，PIN序号是pData，void *->uint32_t
*/
void GPIO_GlobalInit(CBFuncEx_t Fun);
/**
* @brief GPIO初始化
*
* @param Pin Pin序号
* @param IsInput 是否为输入功能，1是，0否
* @param InitValue 初始电平，1高，0低，只对输出有效
*/
void GPIO_Config(uint32_t Pin, uint8_t IsInput, uint8_t InitValue);
/**
* @brief GPIO上下拉控制
*
* @param Pin Pin序号
* @param IsPull 是否需要上下拉
* @param IsUp 是否上拉
*/
void GPIO_PullConfig(uint32_t Pin, uint8_t IsPull, uint8_t IsUp);
/**
* @brief GPIO外部中断初始化
*
* @param Pin Pin序号
* @param IsLevel 是否是电平中断，0边沿型，1电平型
* @param IsRiseHigh 上升沿或者高电平
* @param IsFallLow 下降沿或者低电平
*/
void GPIO_ExtiConfig(uint32_t Pin, uint8_t IsLevel, uint8_t IsRiseHigh, uint8_t IsFallLow);
/**
* @brief GPIO复用功能
*
* @param Pin Pin序号
* @param Function 复用功能，这个需要根据芯片实际情况决定，当前是0~3，注意GPIO功能是1
*/
void GPIO_Iomux(uint32_t Pin, uint32_t Function);
/**
* @brief GPIO输出电平
*
* @param Pin Pin序号
* @param Level 1高电平，0低电平
*/
void GPIO_Output(uint32_t Pin, uint8_t Level);
/**
* @brief 读取GPIO输入电平
*
* @param Pin Pin序号
* @return 1高电平， 0低电平，其他无效
*/
uint8_t GPIO_Input(uint32_t Pin);
/**
* @brief GPIO同一端口多个pin输出电平，针对类似STM32GPIO分布有效
*
* @param Port 端口号
* @param Pins Pin序号组合
* @param Level 1高电平，0低电平
*/
void GPIO_OutputMulti(uint32_t Port, uint32_t Pins, uint32_t Level);
/**
* @brief 读取GPIO同一端口多个pin输入电平
*
* @param Port 端口号
* @return
*/
uint32_t GPIO_InputMulti(uint32_t Port);
void GPIO_ExtiSetHWTimerCB(CBFuncEx_t CB, void *pParam);
void GPIO_ODConfig(uint32_t Pin, uint8_t InitValue);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_HWTIMER_H__
#define __CORE_HWTIMER_H__
/**
* @brief 硬件定时器按照周期和占空比设置成PWM并启动
*
* @param HWTimerID 硬件定时器ID
* @param Period 周期，最大24M，
* @param Duty 占空比，0.1%，只有50KHz以下才能达到这个精度，500KHz到1%
* @param IsOnePulse 只触发一次脉冲
*/
void HWTimer_SetPWM(uint8_t HWTimerID, uint32_t Period, uint16_t Duty, uint8_t IsOnePulse);
/**
* @brief 硬件定时器按照高低电平分辨率设置成PWM并启动，时钟48M
*
* @param HWTimerID 硬件定时器ID
* @param HighCnt 高电平时钟周期数
* @param LowCnt 低电平时钟周期数
* @param IsOnePulse 只触发一次脉冲
*/
void HWTimer_StartPWM(uint8_t HWTimerID, uint32_t HighCnt, uint32_t LowCnt, uint8_t IsOnePulse);
/**
* @brief 硬件定时器关闭
*
* @param HWTimerID 硬件定时器ID
*/
void HWTimer_Stop(uint8_t HWTimerID);
/**
* @brief 初始化IO操作序列，会完全清除之前保留的操作序列
*
* @param HWTimerID 硬件定时器ID
* @param nCount 操作步骤总数
* @param Repeat 重复次数
* @param InputByte IO读取的次数，注意每8次1个byte，不足8个也算1个byte
* @param CmdDoneCB 全部完成后回调函数
* @param pCmdDoneParam 回调函数的用户参数
*
*/
void HWTimer_InitOperationQueue(uint8_t HWTimerID, uint32_t nCount, uint32_t Repeat, uint32_t InputByte, CBFuncEx_t CmdDoneCB, void *pCmdDoneParam);
/**
* @brief 加入IO操作序列
*
* @param HWTimerID 硬件定时器ID
* @param pCmd IO操作
*/
void HWTimer_AddOperation(uint8_t HWTimerID, OPQueue_CmdStruct *pCmd);
/**
* @brief 启动IO操作序列
*
* @param HWTimerID 硬件定时器ID
*/
void HWTimer_StartOperationQueue(uint8_t HWTimerID);
/**
* @brief 清空IO操作序列，需要重新AddOperation，但是不需要init
*
* @param HWTimerID 硬件定时器ID
*/
void HWTimer_ClearOperationQueue(uint8_t HWTimerID);
/**
* @brief 完全释放IO操作序列，下次使用需要重新init，必须在HWTimer_CheckOperationQueueDone确认完成的情况下调用
*
* @param HWTimerID 硬件定时器ID
*/
void HWTimer_FreeOperationQueue(uint8_t HWTimerID);
/**
* @brief 在OP_QUEUE_CMD_CB时，需要在CB里调用本函数来安全的结束序列操作，只能在OP_QUEUE_CMD_CB时调用
*
* @param HWTimerID 硬件定时器ID
*/
void HWTimer_AddEndCmdInOperationQueue(uint8_t HWTimerID);
/**
* @brief 检查IO操作序列是否完成
*
* @param HWTimerID 硬件定时器ID
* @return =0未完成，其他已完成
*/
uint8_t HWTimer_CheckOperationQueueDone(uint8_t HWTimerID);
/**
* @brief 获取IO操作序列中IO读取的值
*
* @param HWTimerID 硬件定时器ID
* @param Value copy的空间
* @return 获取的byte数，和init时InputByte一致
*/
int HWTimer_GetOperationQueueInputResult(uint8_t HWTimerID, uint8_t *Value);
/**
* @brief 获取IO操作序列中捕获状态
*
* @param HWTimerID 硬件定时器ID
* @param CB 捕获回调函数
* @param CB 捕获回调函数的用户参数
* @return 捕获次数
*/
uint32_t HWTimer_GetOperationQueueCaptureResult(uint8_t HWTimerID, CBFuncEx_t CB, void *pParam);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_I2C_H__
#define __CORE_I2C_H__
#include "bsp_common.h"
typedef struct
{
uint8_t Data[2];
}I2C_CommonRegDataStruct;
void I2C_GlobalInit(void);
/**
* @brief i2c主机配置
*
* @param I2CID I2C通道号
* @param Speed 速度，只有100000和400000
*/
void I2C_MasterSetup(uint8_t I2CID, uint32_t Speed);
/*
* @brief i2c传输前配置，如果配置和上次一致，则不用设置
*
* @param I2CID I2C通道号
* @param ChipAddress I2C设备地址
* @param ChipAddressLen I2C设备地址长度 ，1或者2
* @param CB 完成后回调函数
* @param pParam 完成后回调函数中的pParam
*/
void I2C_Prepare(uint8_t I2CID, uint16_t ChipAddress, uint8_t ChipAddressLen, CBFuncEx_t CB, void *pParam);
/**
* @brief i2c主机传输，兼容直接读写和先写寄存器地址后读数据
*
* @param I2CID I2C通道号
* @param Operate 操作类型
* I2C_OP_READ_REG = 0, //i2c通用读寄存器，一写一读，自动带start信号
I2C_OP_READ, //i2c通用读，只读
I2C_OP_WRITE, //i2c通用写，只写
* @param RegAddress 寄存器地址，在通用读写时忽略
* @param Data 读写数据缓存，直接使用用户的空间，在完成前不可以释放空间
* @param Len 读写数据长度
* @param Toms 传输单个字节超时时间，单位ms
*/
void I2C_MasterXfer(uint8_t I2CID, uint8_t Operate, uint8_t RegAddress, uint8_t *Data, uint32_t Len, uint16_t Toms);
/**
* @brief i2c主机传输，多个单一寄存器写入
*
* @param I2CID I2C通道号
* @param RegQueue 寄存器序列
* @param TotalNum 序列长度
* @param Toms 传输单个字节超时时间，单位ms
* @param IsBlock 是否要阻塞
* @return =0 传输成功，其他失败 IsBlock=1才有效，IsBlock=0直接返回0
*/
int32_t I2C_MasterWriteRegQueue(uint8_t I2CID, I2C_CommonRegDataStruct *RegQueue, uint32_t TotalNum, uint16_t Toms, uint8_t IsBlock);
/**
* @brief i2c主机传输结果查询
*
* @param I2CID I2C通道号
* @param Result 传输结果 =0成功，其他失败，只有return != 0才有效
* @return =0 传输还未完成 其他已完成
*/
int I2C_WaitResult(uint8_t I2CID, int32_t *Result);
int32_t I2C_BlockWrite(uint8_t I2CID, uint8_t ChipAddress, const uint8_t *Data, uint32_t Len, uint16_t Toms, CBFuncEx_t CB, void *pParam);
int32_t I2C_BlockRead(uint8_t I2CID, uint8_t ChipAddress, uint8_t *Reg, uint8_t *Data, uint32_t Len, uint16_t Toms, CBFuncEx_t CB, void *pParam);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_IRQ_H__
#define __CORE_IRQ_H__
/**
* @brief 设置中断回调函数
*
* @param Irq 中断号 0~IRQ_LINE_MAX
* @param Handler 中断回调函数，如 void Irq_Handler(uint32_t IrqLine, void *pData); 可以多个中断号对应1个中断函数，回调时传入中断号和用户数据
*/
void ISR_SetHandler(int32_t Irq, void *Handler);
/**
* @brief 设置中断优先级
*
* @param Irq 中断号 0~IRQ_LINE_MAX
* @param PriorityLevel 优先级范围根据芯片实际情况决定
*/
void ISR_SetPriority(int32_t Irq, uint32_t PriorityLevel);
void ISR_OnOff(int32_t Irq, uint32_t OnOff);
void ISR_Clear(int32_t Irq);
void ISR_PrintCallback(int32_t Irq);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_KEYBOARD_H__
#define __CORE_KEYBOARD_H__
/**
* @brief 键盘扫描配置
*
* @param PinConfigMap 硬盘扫描通道配置，bit0~bit8对应通道0到8,0为输入,1为输出，开发板配置为0x0f0
* @param Debounce 按键滤波，目前强制为7
0： 5ms~75ms；
1： 17.5ms~75ms；
2： 27.5ms~75ms；
3： 37.5 ms~75ms；
4： 45ms~75ms；
5： 50ms~75ms；
6： 60ms~75ms；
7： 70ms~75ms。
* @param CB 按键中断回调，pData为按键参数32bit，pParam为用户数据，按键参数中bit16=1按下0释放，bit0~3，输入通道值，bit4~bit7，输出通道值
* @param pParam 按键中断回调用户数据
*/
void KB_Setup(uint16_t PinConfigMap, uint16_t Debounce, CBFuncEx_t CB, void *pParam);
void KB_Stop(void);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_OTP_H__
#define __CORE_OTP_H__
/**
* @brief 写OTP区
*
* @param Address 写入首地址，注意从0开始，一共3KB，必须4字节对齐
* @param Data 写入数据，必须4字节对齐
* @param Len 写入数据长度，单位4字节，比如写入128字节，这里填32
*/
void OTP_Write(uint32_t Address, const uint32_t *Data, uint32_t Len);
/**
* @brief 读OTP区
*
* @param Address 首地址，注意从0开始，一共3KB
* @param Data 缓存数据
* @param Len 读出长度
*/
void OTP_Read(uint32_t Address, uint8_t *Data, uint32_t Len);
/**
* @brief 锁定全部OTP区，变成只读，只能重启恢复
*
*/
void OTP_Lock(void);
void OTP_GetSn(uint8_t *ChipSN);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_RNG_H__
#define __CORE_RNG_H__
void RNG_Init(void);
/**
* @brief 获取随机数
*
* @param Buf，一次获取4个32bit数据
*/
void RNG_GetData(uint32_t Buf[4]);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_RTC_H__
#define __CORE_RTC_H__
#include "bsp_common.h"
void RTC_GlobalInit(void);
void RTC_SetDateTime(Date_UserDataStruct *pDate, Time_UserDataStruct *pTime, uint8_t isForce);
void RTC_GetDateTime(Date_UserDataStruct *pDate, Time_UserDataStruct *pTime);
uint64_t RTC_GetUTC(void);
void RTC_SetStamp(uint32_t Stamp);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_SERVICE_H__
#define __CORE_SERVICE_H__
#include "bsp_common.h"
typedef struct
{
uint32_t Speed;
uint32_t x1;
uint32_t y1;
uint32_t x2;
uint32_t y2;
uint32_t xoffset;
uint32_t yoffset;
uint32_t Size;
uint32_t DCDelay;
uint8_t *Data;
uint8_t SpiID;
uint8_t Mode;
uint8_t CSPin;
uint8_t DCPin;
uint8_t ColorMode;
}LCD_DrawStruct;
void Core_ServiceInit(void);
void Core_LCDDraw(LCD_DrawStruct *Draw);
void Core_CameraDraw(LCD_DrawStruct *Draw);
void Core_DecodeQR(uint8_t *ImageData, uint16_t ImageW, uint16_t ImageH, CBDataFun_t CB);
uint32_t Core_LCDDrawCacheLen(void);
void Core_USBDefaultDeviceStart(uint8_t USB_ID);
void Core_USBAction(uint8_t USB_ID, uint8_t Action, void *pParam);
void Core_PrintMemInfo(void);
void Core_PrintServiceStack(void);
void Core_DebugMem(uint8_t HeapID, const char *FuncName, uint32_t Line);
uint8_t Core_GetSleepFlag(void);
void Core_SetSleepEnable(uint8_t OnOff);
void Core_VUartInit(uint8_t UartID, uint32_t BaudRate, uint8_t IsRxCacheEnable, uint8_t DataBits, uint8_t Parity, uint8_t StopBits, CBFuncEx_t CB);
void Core_VUartDeInit(uint8_t UartID);
void Core_VUartSetRxTimeout(uint8_t UartID, uint32_t TimeoutUS);
void Core_VUartSetCb(uint8_t UartID, CBFuncEx_t CB);
uint32_t Core_VUartRxBufferRead(uint8_t UartID, uint8_t *Data, uint32_t Len);
int32_t Core_VUartBufferTx(uint8_t UartID, const uint8_t *Data, uint32_t Len);
void Core_VUartBufferTxStop(uint8_t UartID);
void Core_VHIDInit(uint8_t USB_ID, CBFuncEx_t CB);
void Core_VHIDUploadData(uint8_t USB_ID, uint8_t *Data, uint16_t Len);
void Core_VHIDUploadStop(uint8_t USB_ID);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_SPI_H__
#define __CORE_SPI_H__
#include "bsp_common.h"
void SPI_MasterInit(uint8_t SpiID, uint8_t DataBit, uint8_t Mode, uint32_t Speed, CBFuncEx_t CB, void *pUserData);
int32_t SPI_Transfer(uint8_t SpiID, const uint8_t *TxData, uint8_t *RxData, uint32_t Len, uint8_t UseDMA);
/*
* polling传输，不发生线程调度
*/
int32_t SPI_BlockTransfer(uint8_t SpiID, const uint8_t *TxData, uint8_t *RxData, uint32_t Len);
/*
* 类似spiflash的cmd+data型传输用，先发WLen数据，忽略Rx数据，再接收RLen数据
*/
int32_t SPI_FlashBlockTransfer(uint8_t SpiID, const uint8_t *TxData, uint32_t WLen, uint8_t *RxData, uint32_t RLen);
void SPI_DMATxInit(uint8_t SpiID, uint8_t Stream, uint32_t Channel);
void SPI_DMARxInit(uint8_t SpiID, uint8_t Stream, uint32_t Channel);
void SPI_TransferStop(uint8_t UartID);
uint8_t SPI_IsTransferBusy(uint8_t UartID);
void SPI_SetNewConfig(uint8_t SpiID, uint32_t Speed, uint8_t NewMode);
void SPI_SetCallbackFun(uint8_t SpiID, CBFuncEx_t CB, void *pUserData);
void SPI_SetTxOnlyFlag(uint8_t SpiID, uint8_t OnOff);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_TASK_H__
#define __CORE_TASK_H__
typedef struct
{
uint32_t ID;
uint32_t Param1;
uint32_t Param2;
uint32_t Param3;
}Task_EventStruct;
#define OS_EVENT Task_EventStruct
HANDLE Task_Create(TaskFun_t EntryFunction, void *Param, uint32_t StackSize, uint32_t Priority, const char *Name);
void Task_SendEvent(HANDLE TaskHandle, uint32_t ID, uint32_t P1, uint32_t P2, uint32_t P3);
int32_t Task_GetEvent(HANDLE TaskHandle, uint32_t TargetEventID, Task_EventStruct *OutEvent, CBFuncEx_t Callback, uint64_t Tick);
int32_t Task_GetEventByMS(HANDLE TaskHandle, uint32_t TargetEventID, Task_EventStruct *OutEvent, CBFuncEx_t Callback, uint32_t ms);
HANDLE Task_GetCurrent(void);
void Task_DelayTick(uint64_t Tick);
void Task_DelayUS(uint32_t US);
void Task_DelayMS(uint32_t MS);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_TICK_H__
#define __CORE_TICK_H__
uint64_t GetSysTick(void);
void SysTickDelay(uint32_t Tick);
void SysTickDelayUntil(uint64_t StartTick, uint32_t Tick);
void CoreTick_Init(void);
uint64_t GetSysTickMS(void);
uint64_t GetSysTickUS(void);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_TIMER_H__
#define __CORE_TIMER_H__
typedef enum
{
TIMER_SN_START = 0,
TIMER_SN_MAX,
}STATIC_TIMER_ENUM;
typedef struct Timer_InfoStruct Timer_t;
/*********************************TimerList*****************************************/
void Timer_Init(void);
//void Timer_Task(void *Param);
//void Timer_Run(void);
Timer_t * Timer_Create(CBFuncEx_t CB, void *Param, void *NotifyTask);
Timer_t * Timer_GetStatic(uint32_t Sn, CBFuncEx_t CB, void *Param, void *NotifyTask);
int Timer_Start(Timer_t *Timer, uint64_t Tick, uint8_t IsRepeat);
int Timer_StartMS(Timer_t *Timer, uint32_t MS, uint8_t IsRepeat);
int Timer_StartUS(Timer_t *Timer, uint32_t US, uint8_t IsRepeat);
void Timer_Stop(Timer_t *Timer);
void Timer_Release(Timer_t *Timer);
uint32_t Timer_NextToRest(void);
uint8_t Timer_IsRunning(Timer_t *Timer);
void Timer_PrintAll(void);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_UART_H__
#define __CORE_UART_H__
#include "bsp_common.h"
/**
* @brief 对串口做基本的初始化工作，不开启任何中断和DMA
*
* @param UartID 串口号 0~MAX，对应USART1~UARTX，0默认用于log输出
* @param BaudRate 波特率
* @param IsRxCacheEnable 是否打开RX缓存功能，打开后，只有接收超时中断才会返回，否则每次数据到来都会返回
* @param DataBits 数据位5~8
* @param Parity 奇偶校验，可选下列
* UART_PARITY_NONE,
UART_PARITY_ODD,
UART_PARITY_EVEN,
* @param StopBits 停止位
* UART_STOP_BIT1,
UART_STOP_BIT1_5,
UART_STOP_BIT2,
* @param CB 回调函数，用于通知是否有新数据达到，DMA TX或者RX完成，是否有错误
*/
void Uart_BaseInit(uint8_t UartID, uint32_t BaudRate, uint8_t IsRxCacheEnable, uint8_t DataBits, uint8_t Parity, uint8_t StopBits, CBFuncEx_t CB);
void Uart_SetCb(uint8_t UartID, CBFuncEx_t CB);
void Uart_DeInit(uint8_t UartID);
/**
* @brief 串口做阻塞输出，一般用于bootloader或者紧急场合
*
* @param UartID 串口号 0~MAX，对应USART1~UARTX，0默认用于log输出
* @param Data
* @param Len
*/
void Uart_BlockTx(uint8_t UartID, uint8_t *Data, uint32_t Len);
void Uart_NoBlockTx(uint8_t UartID, uint8_t Data);
void Uart_EnableRxIrq(uint8_t UartID);
void Uart_EnableTxDoneIrq(uint8_t UartID);
/**
* @brief 串口的DMA配置
*
* @param UartID 串口号 0~5
* @param Stream DMA流序号
* @param Channel DMA通道
* @return >0 成功返回中断号，其他失败
*/
int Uart_DMATxInit(uint8_t UartID, uint8_t Stream, uint32_t Channel);
int Uart_DMARxInit(uint8_t UartID, uint8_t Stream, uint32_t Channel);
/**
* @brief 串口做DMA非阻塞输出，只能用于APP
*
* @param UartID 串口号 0~5
* @param Stream DMA流序号
* @param Data
* @param Len
*/
void Uart_DMATx(uint8_t UartID, uint8_t Stream, const uint8_t *Data, uint32_t Len);
void Uart_DMARx(uint8_t UartID, uint8_t Stream, uint8_t *Data, uint32_t Len);
uint32_t Uart_RxBufferRead(uint8_t UartID, uint8_t *Data, uint32_t Len);
void Uart_RxBufferCB(uint8_t UartID, CBFuncEx_t CB);
uint32_t Uart_FifoRead(uint8_t UartID, uint8_t *Data);
/**
* @brief 串口做FIFO非阻塞输出
*
* @param UartID 串口号 0~5
* @param Data
* @param Len
* @return <0 失败 =0 所有数据传入fifo，不再回调buffer_done，直接回调all_done >0 还有数据没有传入fifo
*/
int32_t Uart_BufferTx(uint8_t UartID, const uint8_t *Data, uint32_t Len);
void Uart_BufferTxStop(uint8_t UartID);
void Uart_PrintReg(uint8_t UartID);
void Uart_ChangeBR(uint8_t UartID, uint32_t BaudRate);
uint32_t Uart_GetLastError(uint8_t UartID);
void Uart_GlobalInit(void);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_USB_LL_DRIVER_H__
#define __CORE_USB_LL_DRIVER_H__
void USB_GlobalInit(void);
void USB_PowerOnOff(HANDLE hUSB, uint8_t OnOff);
void USB_Stop(HANDLE hUSB);
void USB_ResetStart(HANDLE hUSB);
void USB_ResetEnd(HANDLE hUSB);
void USB_SetWorkMode(HANDLE hUSB, uint8_t Mode);
void USB_SetDeviceAddress(HANDLE hUSB, uint8_t Address);
int USB_InitEpCfg(HANDLE hUSB);
int USB_ReInitEpCfg(HANDLE hUSB);
void USB_Start(HANDLE hUSB);
void USB_TxPacket(HANDLE hUSB, uint8_t EpIndex, const uint8_t *Data, uint16_t Len);
void USB_DeviceXfer(HANDLE hUSB, uint8_t EpIndex);
void USB_DeviceXferStop(HANDLE hUSB, uint8_t EpIndex);
void USB_EpIntOnOff(HANDLE hUSB, uint8_t EpIndex, uint8_t IsToDevice, uint8_t OnOff);
void USB_SetDeviceNoDataSetup(HANDLE hUSB);
void USB_FlushFifo(HANDLE hUSB, uint8_t EpIndex, uint8_t IsRxFifo);
void USB_SetDeviceEPStatus (HANDLE hUSB, uint8_t Index, uint8_t IsToDevice, uint8_t Status);
uint8_t USB_GetDeviceEPStatus (HANDLE hUSB, uint8_t Index, uint8_t IsToDevice);
int32_t USB_SetISOCHDelay(HANDLE hUSB, uint16_t DelayNS);
int32_t USB_ExitLatency(HANDLE hUSB, uint8_t Config[6]);
void USB_ResumeStart(HANDLE hUSB);
void USB_ResumeEnd(HANDLE hUSB);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __CORE_WDT_H__
#define __CORE_WDT_H__
void WDT_SetTimeout(uint32_t ms);
void WDT_Feed(void);
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "bsp_common.h"

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __GLOBAL_CONFIG_H__
#define __GLOBAL_CONFIG_H__
#ifndef HSE_VALUE
#define HSE_VALUE ((uint32_t)12000000) /*!< Value of the HSE oscillator in Hz */
#endif
//#define __DEBUG__
#define IRQ_LINE_OFFSET (16) //如果想要用sys_tick,改成15
#define IRQ_LINE_MAX (52)
#define CORE_TICK_BASE (1000)
#define HW_TICK_BASE (48000000)
#define __WDT_TO_MS__ (15000)
#define __FLASH_SECTOR_SIZE__ (0x00001000)
#define __FLASH_PAGE_SIZE__ (0x00000100)
#define __CORE_FLASH_SECTOR_NUM__ (768) //__FLASH_BASE_ADDR__ + __CORE_FLASH_SECTOR_NUM__ * __FLASH_SECTOR_SIZE__，是脚本区， 3M开始
#define __SCRIPT_FLASH_SECTOR_NUM__ (128) //__SCRIPT_FLASH_SECTOR_NUM__ * __FLASH_SECTOR_SIZE__，是脚本区长度，512K，剩余512K是文件区
#define __FLASH_BASE_ADDR__ (0x01000000)
#define __RAMRUN_ISR_ADDR__ (0x20004000)
#define __SRAM_BASE_ADDR__ (0x20000000)
#define __APP_START_MAGIC__ (0x5ae1f0b5)
#ifndef __BUILD_OS__
#define __FUNC_IN_RAM__
#else
#define __FUNC_IN_RAM__ __attribute__((section (".RamFunc")))
#endif
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __IO_MAP_H__
#define __IO_MAP_H__
#define DBG_UART_TX_PIN HAL_GPIO_1
#define DBG_UART_TX_AF 0
#define DBG_UART_RX_PIN HAL_GPIO_0
#define DBG_UART_RX_AF 0
//#define FLASH_SPI_TX_PORT GPIOB
//#define FLASH_SPI_TX_PIN LL_GPIO_PIN_5
//#define FLASH_SPI_TX_AF LL_GPIO_AF_5
//#define FLASH_SPI_RX_PORT GPIOB
//#define FLASH_SPI_RX_PIN LL_GPIO_PIN_4
//#define FLASH_SPI_RX_AF LL_GPIO_AF_5
//#define FLASH_SPI_CLK_PORT GPIOB
//#define FLASH_SPI_CLK_PIN LL_GPIO_PIN_3
//#define FLASH_SPI_CLK_AF LL_GPIO_AF_5
//#define FLASH_SPI_CS_PORT GPIOE
//#define FLASH_SPI_CS_PIN LL_GPIO_PIN_2
//#define FLASH_SPI_CS_AF LL_GPIO_AF_0
//
//
//#define UART2_TX_PORT GPIOA
//#define UART2_TX_PIN LL_GPIO_PIN_9
//#define UART2_TX_AF LL_GPIO_AF_7
//#define UART2_RX_PORT GPIOA
//#define UART2_RX_PIN LL_GPIO_PIN_9
//#define UART2_RX_AF LL_GPIO_AF_7
//
//#define UART3_TX_PORT GPIOA
//#define UART3_TX_PIN LL_GPIO_PIN_9
//#define UART3_TX_AF LL_GPIO_AF_7
//#define UART3_RX_PORT GPIOA
//#define UART3_RX_PIN LL_GPIO_PIN_9
//#define UART3_RX_AF LL_GPIO_AF_7
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __MISC_H
#define __MISC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "air105.h"
typedef struct
{
uint32_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete SCPU Devices IRQ Channels list, please
refer to cpu.h file) */
uint32_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint32_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitTypeDef;
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x01000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
((VECTTAB) == NVIC_VectTab_FLASH))
#define NVIC_PriorityGroup_0 ((uint32_t)0x07) /*!< 0 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PriorityGroup_1 ((uint32_t)0x06) /*!< 1 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PriorityGroup_2 ((uint32_t)0x05) /*!< 2 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PriorityGroup_3 ((uint32_t)0x04) /*!< 3 bits for pre-emption priority
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
((GROUP) == NVIC_PriorityGroup_1) || \
((GROUP) == NVIC_PriorityGroup_2) || \
((GROUP) == NVIC_PriorityGroup_3))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/** @defgroup MISC_SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
//void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT MEGAHUNT *****END OF FILE****/

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __PLATFORM_DEFINE_H__
#define __PLATFORM_DEFINE_H__
enum
{
UART_DATA_BIT5 = 5,
UART_DATA_BIT6 = 6,
UART_DATA_BIT7 = 7,
UART_DATA_BIT8 = 8,
UART_PARITY_NONE = 0,
UART_PARITY_ODD,
UART_PARITY_EVEN,
UART_STOP_BIT1 = 0,
UART_STOP_BIT1_5,
UART_STOP_BIT2,
I2C_OP_READ_REG = 0, //i2c通用读寄存器，一写一读，自动带start信号
I2C_OP_READ, //i2c通用读，只读
I2C_OP_WRITE, //i2c通用写，只写
OP_QUEUE_CMD_END = 0,
OP_QUEUE_CMD_ONE_TIME_DELAY, //只有一次delay
OP_QUEUE_CMD_CONTINUE_DELAY, //连续delay，配合OP_QUEUE_CMD_REPEAT_DELAY使用
OP_QUEUE_CMD_REPEAT_DELAY, //重复OP_QUEUE_CMD_CONTINUE_DELAY
OP_QUEUE_CMD_SET_GPIO_DIR_OUT,
OP_QUEUE_CMD_SET_GPIO_DIR_IN,
OP_QUEUE_CMD_GPIO_OUT,
OP_QUEUE_CMD_GPIO_IN,
OP_QUEUE_CMD_CB,
OP_QUEUE_CMD_CAPTURE_SET,
OP_QUEUE_CMD_CAPTURE,
OP_QUEUE_CMD_CAPTURE_END,
OP_QUEUE_CMD_IO_PULL_NONE = 0,
OP_QUEUE_CMD_IO_PULL_UP,
OP_QUEUE_CMD_IO_PULL_DOWN,
OP_QUEUE_CMD_IO_EXTI_BOTH = 0, //双边沿中断
OP_QUEUE_CMD_IO_EXTI_UP, //上升沿中断
OP_QUEUE_CMD_IO_EXTI_DOWN, //下降沿中断
COLOR_MODE_RGB_565 = 0,
COLOR_MODE_GRAY,
COLOR_MODE_YCBCR_422_UYVY,
COLOR_MODE_YCBCR_422_YUYV,
CORE_OTA_MODE_FULL = 0,
CORE_OTA_MODE_DIFF,
CORE_OTA_IN_FLASH = 0,
CORE_OTA_OUT_SPI_FLASH,
CORE_OTA_IN_FILE,
};
enum
{
USB_ID0 = 0,
USB_MAX,
I2C_ID0 = 0,
I2C_MAX,
UART_ID0 = 0,
UART_ID1,
UART_ID2,
UART_ID3,
// UART_ID4,
// UART_ID5,
UART_MAX,
VIRTUAL_UART0 = 0,
VIRTUAL_UART_MAX,
HSPI_ID0 = 0,
SPI_ID0,
SPI_ID1,
SPI_ID2,
SPI_ID3,
SPI_MAX,
SPI_MODE_0 = 0,
SPI_MODE_1,
SPI_MODE_2,
SPI_MODE_3,
HW_TIMER0 = 0,
HW_TIMER1,
HW_TIMER2,
HW_TIMER3,
HW_TIMER4,
HW_TIMER5,
HW_TIMER_MAX,
ADC_CHANNEL_0 = 0,
ADC_CHANNEL_1,
ADC_CHANNEL_2,
ADC_CHANNEL_3,
ADC_CHANNEL_4,
ADC_CHANNEL_5,
ADC_CHANNEL_6,
ADC_CHANNEL_MAX,
HAL_GPIO_0 = 0,
HAL_GPIO_1,
HAL_GPIO_2,
HAL_GPIO_3,
HAL_GPIO_4,
HAL_GPIO_5,
HAL_GPIO_6,
HAL_GPIO_7,
HAL_GPIO_8,
HAL_GPIO_9,
HAL_GPIO_10,
HAL_GPIO_11,
HAL_GPIO_12,
HAL_GPIO_13,
HAL_GPIO_14,
HAL_GPIO_15,
HAL_GPIO_16,
HAL_GPIO_17,
HAL_GPIO_18,
HAL_GPIO_19,
HAL_GPIO_20,
HAL_GPIO_21,
HAL_GPIO_22,
HAL_GPIO_23,
HAL_GPIO_24,
HAL_GPIO_25,
HAL_GPIO_26,
HAL_GPIO_27,
HAL_GPIO_28,
HAL_GPIO_29,
HAL_GPIO_30,
HAL_GPIO_31,
HAL_GPIO_32,
HAL_GPIO_33,
HAL_GPIO_34,
HAL_GPIO_35,
HAL_GPIO_36,
HAL_GPIO_37,
HAL_GPIO_38,
HAL_GPIO_39,
HAL_GPIO_40,
HAL_GPIO_41,
HAL_GPIO_42,
HAL_GPIO_43,
HAL_GPIO_44,
HAL_GPIO_45,
HAL_GPIO_46,
HAL_GPIO_47,
HAL_GPIO_48,
HAL_GPIO_49,
HAL_GPIO_50,
HAL_GPIO_51,
HAL_GPIO_52,
HAL_GPIO_53,
HAL_GPIO_54,
HAL_GPIO_55,
HAL_GPIO_56,
HAL_GPIO_57,
HAL_GPIO_58,
HAL_GPIO_59,
HAL_GPIO_60,
HAL_GPIO_61,
HAL_GPIO_62,
HAL_GPIO_63,
HAL_GPIO_64,
HAL_GPIO_65,
HAL_GPIO_66,
HAL_GPIO_67,
HAL_GPIO_68,
HAL_GPIO_69,
HAL_GPIO_70,
HAL_GPIO_71,
HAL_GPIO_72,
HAL_GPIO_73,
HAL_GPIO_74,
HAL_GPIO_75,
HAL_GPIO_76,
HAL_GPIO_77,
HAL_GPIO_78,
HAL_GPIO_79,
HAL_GPIO_80,
HAL_GPIO_81,
HAL_GPIO_82,
HAL_GPIO_83,
HAL_GPIO_84,
HAL_GPIO_85,
HAL_GPIO_86,
HAL_GPIO_87,
HAL_GPIO_88,
HAL_GPIO_89,
HAL_GPIO_90,
HAL_GPIO_91,
HAL_GPIO_92,
HAL_GPIO_93,
HAL_GPIO_94,
HAL_GPIO_95,
HAL_GPIO_MAX,
HAL_GPIO_NONE = HAL_GPIO_MAX, //大于等于HAL_GPIO_NONE，说明不存在
};
enum
{
GPIOA_00 = 0,
GPIOA_01,
GPIOA_02,
GPIOA_03,
GPIOA_04,
GPIOA_05,
GPIOA_06,
GPIOA_07,
GPIOA_08,
GPIOA_09,
GPIOA_10,
GPIOA_11,
GPIOA_12,
GPIOA_13,
GPIOA_14,
GPIOA_15,
GPIOB_00,
GPIOB_01,
GPIOB_02,
GPIOB_03,
GPIOB_04,
GPIOB_05,
GPIOB_06,
GPIOB_07,
GPIOB_08,
GPIOB_09,
GPIOB_10,
GPIOB_11,
GPIOB_12,
GPIOB_13,
GPIOB_14,
GPIOB_15,
GPIOC_00,
GPIOC_01,
GPIOC_02,
GPIOC_03,
GPIOC_04,
GPIOC_05,
GPIOC_06,
GPIOC_07,
GPIOC_08,
GPIOC_09,
GPIOC_10,
GPIOC_11,
GPIOC_12,
GPIOC_13,
GPIOC_14,
GPIOC_15,
GPIOD_00,
GPIOD_01,
GPIOD_02,
GPIOD_03,
GPIOD_04,
GPIOD_05,
GPIOD_06,
GPIOD_07,
GPIOD_08,
GPIOD_09,
GPIOD_10,
GPIOD_11,
GPIOD_12,
GPIOD_13,
GPIOD_14,
GPIOD_15,
GPIOE_00,
GPIOE_01,
GPIOE_02,
GPIOE_03,
GPIOE_04,
GPIOE_05,
GPIOE_06,
GPIOE_07,
GPIOE_08,
GPIOE_09,
GPIOE_10,
GPIOE_11,
GPIOE_12,
GPIOE_13,
GPIOE_14,
GPIOE_15,
GPIOF_00,
GPIOF_01,
GPIOF_02,
GPIOF_03,
GPIOF_04,
GPIOF_05,
GPIOF_06,
GPIOF_07,
GPIOF_08,
GPIOF_09,
GPIOF_10,
GPIOF_11,
GPIOF_12,
GPIOF_13,
GPIOF_14,
GPIOF_15,
GPIO_MAX,
GPIO_NONE = GPIO_MAX, //大于等于GPIO_NONE，说明不存在
};
#endif

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/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-08-23 balanceTWK first version
*/
#ifndef __PULSE_ENCODER_CONFIG_H__
#define __PULSE_ENCODER_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef BSP_USING_PULSE_ENCODER1
#ifndef PULSE_ENCODER1_CONFIG
#define PULSE_ENCODER1_CONFIG \
{ \
.tim_handler.Instance = TIM1, \
.encoder_irqn = TIM1_UP_TIM10_IRQn, \
.name = "pulse1" \
}
#endif /* PULSE_ENCODER1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER1 */
#ifdef BSP_USING_PULSE_ENCODER2
#ifndef PULSE_ENCODER2_CONFIG
#define PULSE_ENCODER2_CONFIG \
{ \
.tim_handler.Instance = TIM2, \
.encoder_irqn = TIM2_IRQn, \
.name = "pulse2" \
}
#endif /* PULSE_ENCODER2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER2 */
#ifdef BSP_USING_PULSE_ENCODER3
#ifndef PULSE_ENCODER3_CONFIG
#define PULSE_ENCODER3_CONFIG \
{ \
.tim_handler.Instance = TIM3, \
.encoder_irqn = TIM3_IRQn, \
.name = "pulse3" \
}
#endif /* PULSE_ENCODER3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER3 */
#ifdef BSP_USING_PULSE_ENCODER4
#ifndef PULSE_ENCODER4_CONFIG
#define PULSE_ENCODER4_CONFIG \
{ \
.tim_handler.Instance = TIM4, \
.encoder_irqn = TIM4_IRQn, \
.name = "pulse4" \
}
#endif /* PULSE_ENCODER4_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER4 */
#ifdef __cplusplus
}
#endif
#endif /* __PULSE_ENCODER_CONFIG_H__ */

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/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __RESOURCE_MAP_H__
#define __RESOURCE_MAP_H__
#include "io_map.h"
#define CORE_TICK_TIM 7
#define CORE_TICK_IRQ TIM0_7_IRQn
#define CORE_TICK_1US (48)
#define CORE_TICK_1MS (48000)
#define CORE_TICK_1S (48000000)
#define CORE_TICK_IRQ_LEVEL 1
#define HWTIMER_IRQ_LEVEL 0
#define SYS_TIMER_TIM 6
#define SYS_TIMER_IRQ TIM0_6_IRQn
#define SYS_TIMER_1US (48)
#define SYS_TIMER_1MS (48000)
#define SYS_TIMER_1S (48000000)
#define SYS_TIMER_IRQ_LEVEL 6
#define DBG_UART_ID UART_ID0
#define DBG_UART_BR 1500000
#define BL_UART_BR 3000000
#define DBG_UART_IRQ_LEVEL 6
#define DBG_UART_TX_DMA_STREAM DMA1_STREAM_2
#define DBG_UART_RX_DMA_STREAM DMA1_STREAM_2
#define DBG_UART_TX_DMA_CHANNEL SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART0_TX
#define DBG_UART_RX_DMA_CHANNEL SYSCTRL_PHER_CTRL_DMA_CHx_IF_UART0_RX
#define EFLASH_QSPI_TX_DMA_STREAM DMA1_STREAM_1
#define DAC_TX_DMA_STREAM DMA1_STREAM_0
#define DCMI_RX_DMA_STREAM DMA1_STREAM_3
#define FLASH_SPI_TX_DMA_STREAM DMA1_STREAM_4
#define FLASH_SPI_RX_DMA_STREAM DMA1_STREAM_5
#define LCD_SPI_TX_DMA_STREAM DMA1_STREAM_6
#define LCD_SPI_RX_DMA_STREAM DMA1_STREAM_7
#define LUATOS_TASK_PRO (configMAX_PRIORITIES - 2)
#define HW_TASK_PRO (configMAX_PRIORITIES - 1)
#define SERVICE_TASK_PRO (configMAX_PRIORITIES - 4)
#endif

63
bsp/airm2m/air105/libraries/HAL_Driver/Inc/system_air105.h Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (c) 2022 OpenLuat & AirM2M
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of
* this software and associated documentation files (the "Software"), to deal in
* the Software without restriction, including without limitation the rights to
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
* the Software, and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef __SYSTEM_AIR105_H_ /* ToDo: replace '<Device>' with your device name */
#define __SYSTEM_AIR105_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "air105.h"
#define assert_param(x)
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_<Device>_H */

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