fix the include file error
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@759 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
parent
490767223e
commit
0df924ddaa
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@ -13,375 +13,375 @@
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*/
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*/
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#include <rthw.h>
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtthread.h>
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#include "lpc214x.h"
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#include "LPC24xx.h"
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#include "board.h"
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#include "board.h"
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/* serial hardware register */
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#define REG8(d) (*((volatile unsigned char *)(d)))
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#define REG32(d) (*((volatile unsigned long *)(d)))
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#define UART_RBR(base) REG8(base + 0x00)
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#define UART_THR(base) REG8(base + 0x00)
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#define UART_IER(base) REG32(base + 0x04)
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#define UART_IIR(base) REG32(base + 0x08)
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#define UART_FCR(base) REG8(base + 0x08)
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#define UART_LCR(base) REG8(base + 0x0C)
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#define UART_MCR(base) REG8(base + 0x10)
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#define UART_LSR(base) REG8(base + 0x14)
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#define UART_MSR(base) REG8(base + 0x18)
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#define UART_SCR(base) REG8(base + 0x1C)
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#define UART_DLL(base) REG8(base + 0x00)
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#define UART_DLM(base) REG8(base + 0x04)
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#define UART_ACR(base) REG32(base + 0x20)
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#define UART_FDR(base) REG32(base + 0x28)
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#define UART_TER(base) REG8(base + 0x30)
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/* LPC serial device */
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struct rt_lpcserial
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{
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/* inherit from device */
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struct rt_device parent;
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rt_uint32_t hw_base;
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rt_uint32_t irqno;
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rt_uint32_t baudrate;
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/* reception field */
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rt_uint16_t save_index, read_index;
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rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
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};
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#ifdef RT_USING_UART1
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struct rt_lpcserial serial1;
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#endif
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#ifdef RT_USING_UART2
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struct rt_lpcserial serial2;
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#endif
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void rt_hw_serial_init(void);
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/* serial hardware register */
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#define REG8(d) (*((volatile unsigned char *)(d)))
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#define REG32(d) (*((volatile unsigned long *)(d)))
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#define U0PINS 0x00000005
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#define UART_RBR(base) REG8(base + 0x00)
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#define UART_THR(base) REG8(base + 0x00)
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void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial)
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#define UART_IER(base) REG32(base + 0x04)
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{
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#define UART_IIR(base) REG32(base + 0x08)
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UNUSED rt_uint32_t iir;
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#define UART_FCR(base) REG8(base + 0x08)
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#define UART_LCR(base) REG8(base + 0x0C)
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RT_ASSERT(lpc_serial != RT_NULL)
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#define UART_MCR(base) REG8(base + 0x10)
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#define UART_LSR(base) REG8(base + 0x14)
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if (UART_LSR(lpc_serial->hw_base) & 0x01)
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#define UART_MSR(base) REG8(base + 0x18)
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#define UART_SCR(base) REG8(base + 0x1C)
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#define UART_DLL(base) REG8(base + 0x00)
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#define UART_DLM(base) REG8(base + 0x04)
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#define UART_ACR(base) REG32(base + 0x20)
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#define UART_FDR(base) REG32(base + 0x28)
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#define UART_TER(base) REG8(base + 0x30)
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/* LPC serial device */
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struct rt_lpcserial
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{
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/* inherit from device */
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struct rt_device parent;
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rt_uint32_t hw_base;
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rt_uint32_t irqno;
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rt_uint32_t baudrate;
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/* reception field */
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rt_uint16_t save_index, read_index;
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rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
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};
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#ifdef RT_USING_UART1
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struct rt_lpcserial serial1;
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#endif
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#ifdef RT_USING_UART2
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struct rt_lpcserial serial2;
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#endif
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void rt_hw_serial_init(void);
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#define U0PINS 0x00000005
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void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial)
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{
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UNUSED rt_uint32_t iir;
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RT_ASSERT(lpc_serial != RT_NULL)
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if (UART_LSR(lpc_serial->hw_base) & 0x01)
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{
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{
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rt_base_t level;
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rt_base_t level;
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while (UART_LSR(lpc_serial->hw_base) & 0x01)
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while (UART_LSR(lpc_serial->hw_base) & 0x01)
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{
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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/* read character */
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lpc_serial->rx_buffer[lpc_serial->save_index] =
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UART_RBR(lpc_serial->hw_base);
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lpc_serial->save_index ++;
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if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
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lpc_serial->save_index = 0;
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/* if the next position is read index, discard this 'read char' */
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if (lpc_serial->save_index == lpc_serial->read_index)
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{
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lpc_serial->read_index ++;
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if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
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lpc_serial->read_index = 0;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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}
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/* invoke callback */
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if(lpc_serial->parent.rx_indicate != RT_NULL)
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{
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{
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lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
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/* disable interrupt */
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}
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level = rt_hw_interrupt_disable();
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}
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/* read character */
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/* clear interrupt source */
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lpc_serial->rx_buffer[lpc_serial->save_index] =
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iir = UART_IIR(lpc_serial->hw_base);
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UART_RBR(lpc_serial->hw_base);
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lpc_serial->save_index ++;
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/* acknowledge Interrupt */
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if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
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VICVectAddr = 0;
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lpc_serial->save_index = 0;
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}
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/* if the next position is read index, discard this 'read char' */
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#ifdef RT_USING_UART1
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if (lpc_serial->save_index == lpc_serial->read_index)
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{
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lpc_serial->read_index ++;
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if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
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lpc_serial->read_index = 0;
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}
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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}
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/* invoke callback */
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if(lpc_serial->parent.rx_indicate != RT_NULL)
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{
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lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
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}
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}
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/* clear interrupt source */
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iir = UART_IIR(lpc_serial->hw_base);
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/* acknowledge Interrupt */
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VICVectAddr = 0;
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}
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#ifdef RT_USING_UART1
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void rt_hw_uart_isr_1(int irqno)
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void rt_hw_uart_isr_1(int irqno)
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{
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{
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/* get lpc serial device */
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/* get lpc serial device */
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rt_hw_uart_isr(&serial1);
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rt_hw_uart_isr(&serial1);
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}
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}
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#endif
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#endif
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#ifdef RT_USING_UART2
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#ifdef RT_USING_UART2
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void rt_hw_uart_isr_2(int irqno)
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void rt_hw_uart_isr_2(int irqno)
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{
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{
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/* get lpc serial device */
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/* get lpc serial device */
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rt_hw_uart_isr(&serial2);
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rt_hw_uart_isr(&serial2);
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}
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}
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#endif
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#endif
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/**
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/**
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* @addtogroup LPC214x
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* @addtogroup LPC214x
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*/
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*/
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/*@{*/
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/*@{*/
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static rt_err_t rt_serial_init (rt_device_t dev)
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static rt_err_t rt_serial_init (rt_device_t dev)
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{
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{
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return RT_EOK;
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return RT_EOK;
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}
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}
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static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
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static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
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{
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{
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struct rt_lpcserial* lpc_serial;
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struct rt_lpcserial* lpc_serial;
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lpc_serial = (struct rt_lpcserial*) dev;
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lpc_serial = (struct rt_lpcserial*) dev;
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RT_ASSERT(lpc_serial != RT_NULL);
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RT_ASSERT(lpc_serial != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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{
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/* init UART rx interrupt */
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/* init UART rx interrupt */
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UART_IER(lpc_serial->hw_base) = 0x01;
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UART_IER(lpc_serial->hw_base) = 0x01;
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/* install ISR */
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/* install ISR */
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if (lpc_serial->irqno == UART0_INT)
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if (lpc_serial->irqno == UART0_INT)
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{
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{
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#ifdef RT_USING_UART1
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#ifdef RT_USING_UART1
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rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_1, RT_NULL);
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rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_1, RT_NULL);
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#endif
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#endif
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}
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}
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else
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else
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{
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{
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#ifdef RT_USING_UART2
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#ifdef RT_USING_UART2
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rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_2, RT_NULL);
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rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_2, RT_NULL);
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#endif
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#endif
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}
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}
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rt_hw_interrupt_umask(lpc_serial->irqno);
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rt_hw_interrupt_umask(lpc_serial->irqno);
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}
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}
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return RT_EOK;
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return RT_EOK;
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}
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}
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static rt_err_t rt_serial_close(rt_device_t dev)
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static rt_err_t rt_serial_close(rt_device_t dev)
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{
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{
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struct rt_lpcserial* lpc_serial;
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struct rt_lpcserial* lpc_serial;
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lpc_serial = (struct rt_lpcserial*) dev;
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lpc_serial = (struct rt_lpcserial*) dev;
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RT_ASSERT(lpc_serial != RT_NULL);
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RT_ASSERT(lpc_serial != RT_NULL);
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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{
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/* disable UART rx interrupt */
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/* disable UART rx interrupt */
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UART_IER(lpc_serial->hw_base) = 0x00;
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UART_IER(lpc_serial->hw_base) = 0x00;
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}
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}
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return RT_EOK;
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return RT_EOK;
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}
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}
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static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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{
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{
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return RT_EOK;
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return RT_EOK;
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}
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}
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static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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{
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rt_uint8_t* ptr;
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rt_uint8_t* ptr;
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struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
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struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
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RT_ASSERT(lpc_serial != RT_NULL);
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RT_ASSERT(lpc_serial != RT_NULL);
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/* point to buffer */
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/* point to buffer */
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ptr = (rt_uint8_t*) buffer;
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ptr = (rt_uint8_t*) buffer;
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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if (dev->flag & RT_DEVICE_FLAG_INT_RX)
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{
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{
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while (size)
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while (size)
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{
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{
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/* interrupt receive */
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/* interrupt receive */
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rt_base_t level;
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rt_base_t level;
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/* disable interrupt */
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/* disable interrupt */
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level = rt_hw_interrupt_disable();
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level = rt_hw_interrupt_disable();
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if (lpc_serial->read_index != lpc_serial->save_index)
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if (lpc_serial->read_index != lpc_serial->save_index)
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{
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{
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*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
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*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
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lpc_serial->read_index ++;
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lpc_serial->read_index ++;
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if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
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if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
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lpc_serial->read_index = 0;
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lpc_serial->read_index = 0;
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}
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}
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else
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else
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{
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{
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/* no data in rx buffer */
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/* no data in rx buffer */
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/* enable interrupt */
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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rt_hw_interrupt_enable(level);
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break;
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break;
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}
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}
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/* enable interrupt */
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/* enable interrupt */
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rt_hw_interrupt_enable(level);
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rt_hw_interrupt_enable(level);
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ptr ++; size --;
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ptr ++; size --;
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}
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}
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
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}
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}
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else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
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else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
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{
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{
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/* not support right now */
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/* not support right now */
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RT_ASSERT(0);
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RT_ASSERT(0);
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}
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}
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/* polling mode */
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/* polling mode */
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while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
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while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
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{
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{
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/* Read Character */
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/* Read Character */
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*ptr = UART_RBR(lpc_serial->hw_base);
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*ptr = UART_RBR(lpc_serial->hw_base);
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ptr ++;
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ptr ++;
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size --;
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size --;
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}
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}
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return (rt_size_t)ptr - (rt_size_t)buffer;
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return (rt_size_t)ptr - (rt_size_t)buffer;
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}
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}
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static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
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{
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{
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struct rt_lpcserial* lpc_serial;
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struct rt_lpcserial* lpc_serial;
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char *ptr;
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char *ptr;
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lpc_serial = (struct rt_lpcserial*) dev;
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lpc_serial = (struct rt_lpcserial*) dev;
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||||||
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
|
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
|
||||||
{
|
{
|
||||||
/* not support */
|
/* not support */
|
||||||
RT_ASSERT(0);
|
RT_ASSERT(0);
|
||||||
}
|
}
|
||||||
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
|
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
|
||||||
{
|
{
|
||||||
/* not support */
|
/* not support */
|
||||||
RT_ASSERT(0);
|
RT_ASSERT(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* polling write */
|
/* polling write */
|
||||||
ptr = (char *)buffer;
|
ptr = (char *)buffer;
|
||||||
|
|
||||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
||||||
{
|
{
|
||||||
/* stream mode */
|
/* stream mode */
|
||||||
while (size)
|
while (size)
|
||||||
{
|
{
|
||||||
if (*ptr == '\n')
|
if (*ptr == '\n')
|
||||||
{
|
{
|
||||||
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
|
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
|
||||||
UART_THR(lpc_serial->hw_base) = '\r';
|
UART_THR(lpc_serial->hw_base) = '\r';
|
||||||
}
|
}
|
||||||
|
|
||||||
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
|
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
|
||||||
UART_THR(lpc_serial->hw_base) = *ptr;
|
UART_THR(lpc_serial->hw_base) = *ptr;
|
||||||
|
|
||||||
ptr ++;
|
ptr ++;
|
||||||
size --;
|
size --;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
while (size)
|
while (size)
|
||||||
{
|
{
|
||||||
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
|
while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
|
||||||
UART_THR(lpc_serial->hw_base) = *ptr;
|
UART_THR(lpc_serial->hw_base) = *ptr;
|
||||||
|
|
||||||
ptr ++;
|
ptr ++;
|
||||||
size --;
|
size --;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||||
}
|
}
|
||||||
|
|
||||||
void rt_hw_serial_init(void)
|
void rt_hw_serial_init(void)
|
||||||
{
|
{
|
||||||
struct rt_lpcserial* lpc_serial;
|
struct rt_lpcserial* lpc_serial;
|
||||||
|
|
||||||
#ifdef RT_USING_UART1
|
#ifdef RT_USING_UART1
|
||||||
lpc_serial = &serial1;
|
lpc_serial = &serial1;
|
||||||
|
|
||||||
lpc_serial->parent.type = RT_Device_Class_Char;
|
lpc_serial->parent.type = RT_Device_Class_Char;
|
||||||
|
|
||||||
lpc_serial->hw_base = 0xE000C000;
|
lpc_serial->hw_base = 0xE000C000;
|
||||||
lpc_serial->baudrate = 115200;
|
lpc_serial->baudrate = 115200;
|
||||||
lpc_serial->irqno = UART0_INT;
|
lpc_serial->irqno = UART0_INT;
|
||||||
|
|
||||||
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
|
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
|
||||||
lpc_serial->read_index = lpc_serial->save_index = 0;
|
lpc_serial->read_index = lpc_serial->save_index = 0;
|
||||||
|
|
||||||
/* Enable UART0 RxD and TxD pins */
|
/* Enable UART0 RxD and TxD pins */
|
||||||
PINSEL0 |= 0x05;
|
PINSEL0 |= 0x05;
|
||||||
|
|
||||||
/* 8 bits, no Parity, 1 Stop bit */
|
/* 8 bits, no Parity, 1 Stop bit */
|
||||||
UART_LCR(lpc_serial->hw_base) = 0x83;
|
UART_LCR(lpc_serial->hw_base) = 0x83;
|
||||||
|
|
||||||
/* Setup Baudrate */
|
/* Setup Baudrate */
|
||||||
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
|
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
|
||||||
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
|
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
|
||||||
|
|
||||||
/* DLAB = 0 */
|
/* DLAB = 0 */
|
||||||
UART_LCR(lpc_serial->hw_base) = 0x03;
|
UART_LCR(lpc_serial->hw_base) = 0x03;
|
||||||
|
|
||||||
lpc_serial->parent.init = rt_serial_init;
|
lpc_serial->parent.init = rt_serial_init;
|
||||||
lpc_serial->parent.open = rt_serial_open;
|
lpc_serial->parent.open = rt_serial_open;
|
||||||
lpc_serial->parent.close = rt_serial_close;
|
lpc_serial->parent.close = rt_serial_close;
|
||||||
lpc_serial->parent.read = rt_serial_read;
|
lpc_serial->parent.read = rt_serial_read;
|
||||||
lpc_serial->parent.write = rt_serial_write;
|
lpc_serial->parent.write = rt_serial_write;
|
||||||
lpc_serial->parent.control = rt_serial_control;
|
lpc_serial->parent.control = rt_serial_control;
|
||||||
lpc_serial->parent.private = RT_NULL;
|
lpc_serial->parent.private = RT_NULL;
|
||||||
|
|
||||||
rt_device_register(&lpc_serial->parent,
|
rt_device_register(&lpc_serial->parent,
|
||||||
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef RT_USING_UART2
|
#ifdef RT_USING_UART2
|
||||||
lpc_serial = &serial2;
|
lpc_serial = &serial2;
|
||||||
|
|
||||||
lpc_serial->parent.type = RT_Device_Class_Char;
|
lpc_serial->parent.type = RT_Device_Class_Char;
|
||||||
|
|
||||||
lpc_serial->hw_base = 0xE0010000;
|
lpc_serial->hw_base = 0xE0010000;
|
||||||
lpc_serial->baudrate = 115200;
|
lpc_serial->baudrate = 115200;
|
||||||
lpc_serial->irqno = UART1_INT;
|
lpc_serial->irqno = UART1_INT;
|
||||||
|
|
||||||
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
|
rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
|
||||||
lpc_serial->read_index = lpc_serial->save_index = 0;
|
lpc_serial->read_index = lpc_serial->save_index = 0;
|
||||||
|
|
||||||
/* Enable UART1 RxD and TxD pins */
|
/* Enable UART1 RxD and TxD pins */
|
||||||
PINSEL0 |= 0x05 << 16;
|
PINSEL0 |= 0x05 << 16;
|
||||||
|
|
||||||
/* 8 bits, no Parity, 1 Stop bit */
|
/* 8 bits, no Parity, 1 Stop bit */
|
||||||
UART_LCR(lpc_serial->hw_base) = 0x83;
|
UART_LCR(lpc_serial->hw_base) = 0x83;
|
||||||
|
|
||||||
/* Setup Baudrate */
|
/* Setup Baudrate */
|
||||||
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
|
UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
|
||||||
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
|
UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
|
||||||
|
|
||||||
/* DLAB = 0 */
|
/* DLAB = 0 */
|
||||||
UART_LCR(lpc_serial->hw_base) = 0x03;
|
UART_LCR(lpc_serial->hw_base) = 0x03;
|
||||||
|
|
||||||
lpc_serial->parent.init = rt_serial_init;
|
lpc_serial->parent.init = rt_serial_init;
|
||||||
lpc_serial->parent.open = rt_serial_open;
|
lpc_serial->parent.open = rt_serial_open;
|
||||||
lpc_serial->parent.close = rt_serial_close;
|
lpc_serial->parent.close = rt_serial_close;
|
||||||
lpc_serial->parent.read = rt_serial_read;
|
lpc_serial->parent.read = rt_serial_read;
|
||||||
lpc_serial->parent.write = rt_serial_write;
|
lpc_serial->parent.write = rt_serial_write;
|
||||||
lpc_serial->parent.control = rt_serial_control;
|
lpc_serial->parent.control = rt_serial_control;
|
||||||
lpc_serial->parent.private = RT_NULL;
|
lpc_serial->parent.private = RT_NULL;
|
||||||
|
|
||||||
rt_device_register(&lpc_serial->parent,
|
rt_device_register(&lpc_serial->parent,
|
||||||
"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
/*@}*/
|
/*@}*/
|
||||||
|
|
|
||||||
|
|
@ -118,10 +118,10 @@ void rt_hw_trap_resv(struct rt_hw_register *regs)
|
||||||
extern rt_isr_handler_t isr_table[];
|
extern rt_isr_handler_t isr_table[];
|
||||||
void rt_hw_trap_irq()
|
void rt_hw_trap_irq()
|
||||||
{
|
{
|
||||||
rt_isr_handler_t isr_func;
|
rt_isr_handler_t isr_func;
|
||||||
|
|
||||||
isr_func = (rt_isr_handler_t) VICVectAddr;
|
isr_func = (rt_isr_handler_t) VICVectAddr;
|
||||||
isr_func(0);
|
isr_func(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void rt_hw_trap_fiq()
|
void rt_hw_trap_fiq()
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue