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Merge pull request #4483 from iysheng/just_rtc 

[bsp][ab32vg1] Fix sizeof(time_t) no match with this chip
This commit is contained in:
Bernard Xiong 2021-03-23 20:10:29 +08:00 committed by GitHub
parent 5ded4a1f52 d8e906e6c8
commit 0da431750d
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GPG Key ID: 4AEE18F83AFDEB23
4 changed files with 39 additions and 19 deletions
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7
bsp/bluetrum/ab32vg1-ab-prougen/board/Kconfig
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@ -167,11 +167,16 @@ menu "On-chip Peripheral Drivers"
default n default n
endif endif
config BSP_USING_ONCHIP_RTC menuconfig BSP_USING_ONCHIP_RTC
bool "Enable RTC" bool "Enable RTC"
select RT_USING_RTC select RT_USING_RTC
select RT_USING_LIBC select RT_USING_LIBC
default n default n
if BSP_USING_ONCHIP_RTC
config RTC_USING_INTERNAL_CLK
bool "Using internal clock RTC"
default y
endif
menuconfig BSP_USING_ADC menuconfig BSP_USING_ADC
bool "Enable ADC" bool "Enable ADC"

2
bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py
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@ -41,7 +41,7 @@ if PLATFORM == 'gcc':
# DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant' # DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32 -fsingle-precision-constant'
DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32' DEVICE = ' -mcmodel=medany -march=rv32imc -mabi=ilp32'
# CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields' # CFLAGS = DEVICE + ' -fno-common -ffunction-sections -fdata-sections -fstrict-volatile-bitfields'
CFLAGS = DEVICE CFLAGS = DEVICE + ' -D_USE_LONG_TIME_T'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds' LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T link.lds'
CPATH = '' CPATH = ''

47
bsp/bluetrum/libraries/hal_drivers/drv_rtc.c
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@ -6,6 +6,7 @@
* Change Logs: * Change Logs:
* Date Author Notes * Date Author Notes
* 2021-01-28 greedyhao first version * 2021-01-28 greedyhao first version
* 2021-03-19 iysheng modify just set time first power up
*/ */
#include "board.h" #include "board.h"
@ -95,30 +96,44 @@ uint8_t irtc_sfr_read(uint32_t cmd)
IRTC_EXIT_CRITICAL(); IRTC_EXIT_CRITICAL();
} }
static void _init_rtc_clock(void)
{
uint8_t rtccon0;
uint8_t rtccon2;
rtccon0 = irtc_sfr_read(RTCCON0_CMD);
rtccon2 = irtc_sfr_read(RTCCON2_CMD);
#ifdef RTC_USING_INTERNAL_CLK
rtccon0 &= ~RTC_CON0_XOSC32K_ENABLE;
rtccon0 |= RTC_CON0_INTERNAL_32K;
rtccon2 | RTC_CON2_32K_SELECT;
#else
rtccon0 |= RTC_CON0_XOSC32K_ENABLE;
rtccon0 &= ~RTC_CON0_INTERNAL_32K;
rtccon2 & ~RTC_CON2_32K_SELECT;
#endif
irtc_sfr_write(RTCCON0_CMD, rtccon0);
irtc_sfr_write(RTCCON2_CMD, rtccon2);
}
void hal_rtc_init(void) void hal_rtc_init(void)
{ {
time_t sec = 0; time_t sec = 0;
struct tm tm_new = {0}; struct tm tm_new = {0};
uint8_t temp;
uint8_t temp = irtc_sfr_read(RTCCON0_CMD); _init_rtc_clock();
temp &= ~RTC_CON0_XOSC32K_ENABLE;
temp |= RTC_CON0_EXTERNAL_32K;
irtc_sfr_write(RTCCON0_CMD, temp);
temp = irtc_sfr_read(RTCCON2_CMD);
irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT);
temp = irtc_sfr_read(RTCCON0_CMD); temp = irtc_sfr_read(RTCCON0_CMD);
if (temp & BIT(7)) { if (temp & RTC_CON0_PWRUP_FIRST) {
temp &= ~BIT(7); temp &= ~RTC_CON0_PWRUP_FIRST;
irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */ irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */
tm_new.tm_mday = 29;
tm_new.tm_mon = 1 - 1;
tm_new.tm_year = 2021 - 1900;
sec = timegm(&tm_new);
irtc_time_write(RTCCNT_CMD, sec);
} }
tm_new.tm_mday = 29;
tm_new.tm_mon = 1 - 1;
tm_new.tm_year = 2021 - 1900;
sec = timegm(&tm_new);
irtc_time_write(RTCCNT_CMD, sec);
} }
/************** HAL End *******************/ /************** HAL End *******************/

2
bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/include/ab32vg1_hal_rtc.h
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@ -34,7 +34,7 @@ enum
// RTCCON0 // RTCCON0
#define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */ #define RTC_CON0_PWRUP_FIRST (0x01u << 7) /*!< RTC first power up flag */
#define RTC_CON0_EXTERNAL_32K (0x01u << 6) /*!< External 32K select */ #define RTC_CON0_INTERNAL_32K (0x01u << 6) /*!< Internal 32K select */
#define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */ #define RTC_CON0_VDD_ENABLE (0x01u << 5) /*!< RTC VDD12 enable */
#define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */ #define RTC_CON0_BG_ENABLE (0x01u << 4) /*!< BG enable */
#define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */ #define RTC_CON0_LVD_OUTPUT_ENABLE (0x01u << 3) /*!< LVD output enable */