libs/rt-thread-official
libs
/
rt-thread-official
mirror of https://github.com/RT-Thread/rt-thread.git
4
0
Fork 0
Code Issues Releases Wiki Activity

Sync upstream (#6793) 

Co-authored-by: Wayne Lin <wclin@nuvoton.com>
This commit is contained in:
Wayne 2022-12-29 15:15:13 +08:00 committed by GitHub
parent 882a0af94e
commit 0d1c709fa5
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
203 changed files with 11994 additions and 34486 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
bsp/nuvoton/README.md
View File

@ -14,3 +14,4 @@ Current supported BSP shown in below table:
| NuMaker-M467HJ | CORTEX-M4 | [numaker-m467hj](numaker-m467hj) |
| NuMaker-IoT-M467 | CORTEX-M4 | [numaker-iot-m467](numaker-iot-m467) |
| NuMaker-HMI-MA35D1 | CORTEX-A35, CORTEX-M4 | [numaker-hmi-ma35d1](numaker-hmi-ma35d1), [ma35-rtp](ma35-rtp) |
| NuMaker-IOT-MA35D1 | CORTEX-A35, CORTEX-M4 | [numaker-iot-ma35d1](numaker-iot-ma35d1), [ma35-rtp](ma35-rtp) |

12
bsp/nuvoton/libraries/m460/rtt_port/drv_pdma.c
View File

@ -154,12 +154,6 @@ static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] =
{ PDMA_SPI9_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_SPI10_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C0_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C1_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C2_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C3_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2C4_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2S0_TX, eMemCtl_SrcInc_DstFix },
{ PDMA_I2S1_TX, eMemCtl_SrcInc_DstFix },
@ -215,12 +209,6 @@ static const nu_pdma_periph_ctl_t g_nu_pdma_peripheral_ctl_pool[ ] =
{ PDMA_EPWM1_P2_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_EPWM1_P3_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C0_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C1_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C2_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C3_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2C4_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2S0_RX, eMemCtl_SrcFix_DstInc },
{ PDMA_I2S1_RX, eMemCtl_SrcFix_DstInc },

92
bsp/nuvoton/libraries/m480/StdDriver/src/nu_rtc.c
View File

@ -67,15 +67,15 @@ void RTC_Open(S_RTC_TIME_DATA_T *sPt)
{
RTC->INIT = RTC_INIT_KEY;
if(RTC->INIT != RTC_INIT_ACTIVE_Msk)
if (RTC->INIT != RTC_INIT_ACTIVE_Msk)
{
RTC->INIT = RTC_INIT_KEY;
while(RTC->INIT != RTC_INIT_ACTIVE_Msk)
while (RTC->INIT != RTC_INIT_ACTIVE_Msk)
{
}
}
if(sPt == 0)
if (sPt == 0)
{
}
else
@ -110,14 +110,14 @@ void RTC_Close(void)
void RTC_32KCalibration(int32_t i32FrequencyX10000)
{
uint64_t u64Compensate;
int32_t i32RegInt,i32RegFra ;
int32_t i32RegInt, i32RegFra ;
if(!(SYS->CSERVER & 0x1))
if (!(SYS->CSERVER & 0x1))
{
u64Compensate = (uint64_t)(0x2710000000000);
u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000);
if(u64Compensate >= (uint64_t)0x400000)
if (u64Compensate >= (uint64_t)0x400000)
{
u64Compensate = (uint64_t)0x3FFFFF;
}
@ -128,23 +128,23 @@ void RTC_32KCalibration(int32_t i32FrequencyX10000)
else
{
/* Compute Integer and Fraction for RTC register*/
i32RegInt = (i32FrequencyX10000/10000) - 32752;
i32RegFra = ((((i32FrequencyX10000%10000)) * 64) + 5000) / 10000;
i32RegInt = (i32FrequencyX10000 / 10000) - 32752;
i32RegFra = ((((i32FrequencyX10000 % 10000)) * 64) + 5000) / 10000;
if(i32RegFra >= 0x40)
if (i32RegFra >= 0x40)
{
i32RegFra = 0x0;
i32RegInt++;
}
/* Judge Integer part is reasonable */
if ( (i32RegInt < 0) | (i32RegInt > 31) )
if ((i32RegInt < 0) | (i32RegInt > 31))
{
return;
}
RTC_WaitAccessEnable();
RTC->FREQADJ = (uint32_t)((i32RegInt<<8) | i32RegFra);
RTC->FREQADJ = (uint32_t)((i32RegInt << 8) | i32RegFra);
}
}
@ -204,13 +204,13 @@ void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt)
sPt->u32Day = u32Tmp + g_u32loDay;
/* Compute 12/24 hour */
if(sPt->u32TimeScale == RTC_CLOCK_12)
if (sPt->u32TimeScale == RTC_CLOCK_12)
{
u32Tmp = (g_u32hiHour * 10ul);
u32Tmp += g_u32loHour;
sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
if(sPt->u32Hour >= 21ul)
if (sPt->u32Hour >= 21ul)
{
sPt->u32AmPm = RTC_PM;
sPt->u32Hour -= 20ul;
@ -301,13 +301,13 @@ void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
sPt->u32Day = u32Tmp + g_u32loDay;
/* Compute 12/24 hour */
if(sPt->u32TimeScale == RTC_CLOCK_12)
if (sPt->u32TimeScale == RTC_CLOCK_12)
{
u32Tmp = (g_u32hiHour * 10ul);
u32Tmp += g_u32loHour;
sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */
if(sPt->u32Hour >= 21ul)
if (sPt->u32Hour >= 21ul)
{
sPt->u32AmPm = RTC_PM;
sPt->u32Hour -= 20ul;
@ -366,7 +366,7 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCAL, u32RegTIME;
if(sPt == 0ul)
if (sPt == NULL)
{
}
else
@ -375,14 +375,14 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
if(sPt->u32TimeScale == RTC_CLOCK_12)
if (sPt->u32TimeScale == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
/*-------------------------------------------------------------------------------------------------*/
/* Important, range of 12-hour PM mode is 21 up to 32 */
/*-------------------------------------------------------------------------------------------------*/
if(sPt->u32AmPm == RTC_PM)
if (sPt->u32AmPm == RTC_PM)
{
sPt->u32Hour += 20ul;
}
@ -447,7 +447,7 @@ void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCALM, u32RegTALM;
if(sPt == 0)
if (sPt == NULL)
{
}
else
@ -456,14 +456,14 @@ void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
if(sPt->u32TimeScale == RTC_CLOCK_12)
if (sPt->u32TimeScale == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
/*-------------------------------------------------------------------------------------------------*/
/* Important, range of 12-hour PM mode is 21 up to 32 */
/*-------------------------------------------------------------------------------------------------*/
if(sPt->u32AmPm == RTC_PM)
if (sPt->u32AmPm == RTC_PM)
{
sPt->u32Hour += 20ul;
}
@ -549,7 +549,7 @@ void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint3
uint32_t u32RegTIME;
/* Important, range of 12-hour PM mode is 21 up to 32 */
if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
{
u32Hour += 20ul;
}
@ -565,7 +565,7 @@ void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint3
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
if(u32TimeMode == RTC_CLOCK_12)
if (u32TimeMode == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
}
@ -624,7 +624,7 @@ void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second,
uint32_t u32RegTALM;
/* Important, range of 12-hour PM mode is 21 up to 32 */
if((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
if ((u32TimeMode == RTC_CLOCK_12) && (u32AmPm == RTC_PM))
{
u32Hour += 20ul;
}
@ -640,7 +640,7 @@ void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second,
/* Set RTC 24/12 hour setting and Day of the Week */
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
if(u32TimeMode == RTC_CLOCK_12)
if (u32TimeMode == RTC_CLOCK_12)
{
RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk;
}
@ -861,15 +861,15 @@ void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, ui
RTC_WaitAccessEnable();
u32Reg = RTC->TAMPCTL;
u32TmpReg = ( RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
(u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos) );
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) |
(u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos));
for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
for (i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
{
if(u32TamperSelect & (0x1ul << i))
if (u32TamperSelect & (0x1ul << i))
{
u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk|RTC_TAMPCTL_TAMP0LV_Msk|RTC_TAMPCTL_TAMP0DBEN_Msk) << (i*4ul));
u32Reg |= (u32TmpReg << (i*4ul));
u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (i * 4ul));
u32Reg |= (u32TmpReg << (i * 4ul));
}
}
@ -904,11 +904,11 @@ void RTC_StaticTamperDisable(uint32_t u32TamperSelect)
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk);
for(i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
for (i = 0ul; i < MAX_TAMPER_PIN_NUM; i++)
{
if(u32TamperSelect & (0x1ul << i))
if (u32TamperSelect & (0x1ul << i))
{
u32Reg &= ~(u32TmpReg << (i*4ul));
u32Reg &= ~(u32TmpReg << (i * 4ul));
}
}
@ -958,7 +958,7 @@ void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32
u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk);
u32Reg |= ((u32Pair1Source & 0x1ul) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1ul) << RTC_TAMPCTL_DYN2ISS_Pos);
if(u32DebounceEn)
if (u32DebounceEn)
{
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk |
RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
@ -968,22 +968,22 @@ void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
}
for(i = 0ul; i < MAX_PAIR_NUM; i++)
for (i = 0ul; i < MAX_PAIR_NUM; i++)
{
if(u32PairSel & (0x1ul << i))
if (u32PairSel & (0x1ul << i))
{
u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i*8ul));
u32Reg |= (u32TmpReg << (i*8ul));
u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i * 8ul));
u32Reg |= (u32TmpReg << (i * 8ul));
}
}
if((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT))
if ((u32Pair1Source) && (u32PairSel & RTC_PAIR1_SELECT))
{
u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk;
u32Reg |= u32Tamper2Debounce;
}
if((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT))
if ((u32Pair2Source) && (u32PairSel & RTC_PAIR2_SELECT))
{
u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk;
u32Reg |= u32Tamper4Debounce;
@ -1015,23 +1015,23 @@ void RTC_DynamicTamperDisable(uint32_t u32PairSel)
RTC_WaitAccessEnable();
u32Reg = RTC->TAMPCTL;
if((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT))
if ((u32Reg & RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & RTC_PAIR1_SELECT))
{
u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk;
}
if((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT))
if ((u32Reg & RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & RTC_PAIR2_SELECT))
{
u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk;
}
u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk);
for(i = 0ul; i < MAX_PAIR_NUM; i++)
for (i = 0ul; i < MAX_PAIR_NUM; i++)
{
if(u32PairSel & (0x1ul << i))
if (u32PairSel & (0x1ul << i))
{
u32Reg &= ~(u32TmpReg << ((i*8ul)));
u32Reg &= ~(u32TmpReg << ((i * 8ul)));
}
}

8
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/ma35d1.h
View File

@ -239,9 +239,9 @@ typedef enum IRQn
/****** Platform Exceptions Numbers ***************************************************/
LVD_IRQn = 32, /*!< Low Voltage detection Interrupt */
A35PMU_IRQn = 33, /*!< A35 PMU Interrupt */
HSEM_IRQn = 34, /*!< Hardware Semaphore Interrupt */
HWSEM0_IRQn = 34, /*!< Hardware Semaphore Interrupt */
CKFAIL_IRQn = 35, /*!< Clock failed Interrupt */
WRHO_IRQn = 36, /*!< Wormhole Interrupt */
WHC0_IRQn = 36, /*!< Wormhole Interrupt */
RTC_IRQn = 37, /*!< Real Time Clock Interrupt */
TAMPER_IRQn = 38, /*!< Tamper detection Interrupt */
WDT0_IRQn = 39, /*!< Watchdog timer 0 Interrupt */
@ -266,7 +266,7 @@ typedef enum IRQn
SSPCC_IRQn = 58, /*!< SSPCC Interrupt */
GFX_IRQn = 59, /*!< GFX GC520L Interrupt (Graphic Engine) */
VDE_IRQn = 60, /*!< Video Decoder (VC8000) Interrupt */
WRHO1_IRQn = 61, /*!< WRHO 1 Interrupt */
WHC1_IRQn = 61, /*!< WRHO 1 Interrupt */
SDH0_IRQn = 62, /*!< SDH 0 Interrupt */
SDH1_IRQn = 63, /*!< SDH 1 Interrupt */
HSUSBD_IRQn = 64, /*!< USB 2.0 High-Speed Device Interrupt */
@ -468,6 +468,7 @@ typedef enum IRQn
#include "sdh_reg.h"
#include "ccap_reg.h"
#include "nfi_reg.h"
/** @addtogroup PERIPHERAL_MEM_MAP Peripheral Memory Base
Memory Mapped Structure for Peripherals
@ -781,6 +782,7 @@ typedef enum IRQn
#define CCAP0 ((CCAP_T*) CCAP0_BASE)
#define CCAP1 ((CCAP_T*) CCAP1_BASE)
#define NFI ((NFI_T*) NAND_BASE)
/*@}*/ /* end of group ERIPHERAL_DECLARATION */
/** @addtogroup IO_ROUTINE I/O Routines

913
bsp/nuvoton/libraries/ma35/Device/Nuvoton/MA35D1/Include/nfi_reg.h
View File

@ -1803,50 +1803,27 @@ typedef struct
* |[31:0] |Data |NAND Flash Redundant Area Word n
* | | |This field indicates a 32-bit data of redundant area.
*/
__IO uint32_t BUFFER0; /*!< [0x0000] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER1; /*!< [0x0004] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER2; /*!< [0x0008] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER3; /*!< [0x000c] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER4; /*!< [0x0010] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER5; /*!< [0x0014] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER6; /*!< [0x0018] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER7; /*!< [0x001c] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER8; /*!< [0x0020] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER9; /*!< [0x0024] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER10; /*!< [0x0028] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER11; /*!< [0x002c] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER12; /*!< [0x0030] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER13; /*!< [0x0034] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER14; /*!< [0x0038] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER15; /*!< [0x003c] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER16; /*!< [0x0040] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER17; /*!< [0x0044] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER18; /*!< [0x0048] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER19; /*!< [0x004c] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER20; /*!< [0x0050] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER21; /*!< [0x0054] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER22; /*!< [0x0058] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER23; /*!< [0x005c] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER24; /*!< [0x0060] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER25; /*!< [0x0064] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER26; /*!< [0x0068] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER27; /*!< [0x006c] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER28; /*!< [0x0070] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER29; /*!< [0x0074] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER30; /*!< [0x0078] NFI Embedded Buffer Word n */
__IO uint32_t BUFFER31; /*!< [0x007c] NFI Embedded Buffer Word n */
__I uint32_t RESERVE0[224];
__IO uint32_t BUFFER[32]; /*!< [0x0000] NFI Embedded Buffer Word n */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE0[224]; /*!< [0x0080~0x03FC] */
/** @endcond */
__IO uint32_t DMACTL; /*!< [0x0400] NFI DMA Control and Status Register */
__I uint32_t RESERVE1[1];
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE1[1]; /*!< [0x0404] */
/** @endcond */
__IO uint32_t DMASA; /*!< [0x0408] NFI DMA Transfer Starting Address Register */
__I uint32_t DMABCNT; /*!< [0x040c] NFI DMA Transfer Byte Count Register */
__IO uint32_t DMAINTEN; /*!< [0x0410] NFI DMA Interrupt Enable Control Register */
__I uint32_t DMAINTSTS; /*!< [0x0414] NFI DMA Interrupt Status Register */
__I uint32_t RESERVE2[250];
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE2[250]; /*!< [0x0418~0x07FC] */
/** @endcond */
__IO uint32_t GCTL; /*!< [0x0800] NFI Global Control and Status Register */
__IO uint32_t GINTEN; /*!< [0x0804] NFI Global Interrupt Control Register */
__I uint32_t GINTSTS; /*!< [0x0808] NFI Global Interrupt Status Register */
__I uint32_t RESERVE3[37];
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE3[37]; /*!< [0x080C~0x089C] */
/** @endcond */
__IO uint32_t NANDCTL; /*!< [0x08a0] NAND Flash Control Register */
__IO uint32_t NANDTMCTL; /*!< [0x08a4] NAND Flash Timing Control Register */
__IO uint32_t NANDINTEN; /*!< [0x08a8] NAND Flash Interrupt Enable Register */
@ -1856,151 +1833,22 @@ typedef struct
__IO uint32_t NANDDATA; /*!< [0x08b8] NAND Flash Data Port Register */
__IO uint32_t NANDRACTL; /*!< [0x08bc] NAND Flash Redundant Area Control Register */
__IO uint32_t NANDECTL; /*!< [0x08c0] NAND Flash Extend Control Register */
__I uint32_t RESERVE4[3];
__I uint32_t NANDECCES0; /*!< [0x08d0] NAND Flash ECC Error Status 0 Register */
__I uint32_t NANDECCES1; /*!< [0x08d4] NAND Flash ECC Error Status 1 Register */
__I uint32_t NANDECCES2; /*!< [0x08d8] NAND Flash ECC Error Status 2 Register */
__I uint32_t NANDECCES3; /*!< [0x08dc] NAND Flash ECC Error Status 3 Register */
__I uint32_t RESERVE5[8];
__I uint32_t NANDECCEA0; /*!< [0x0900] NAND Flash ECC Error Byte Address 0 Register */
__I uint32_t NANDECCEA1; /*!< [0x0904] NAND Flash ECC Error Byte Address 1 Register */
__I uint32_t NANDECCEA2; /*!< [0x0908] NAND Flash ECC Error Byte Address 2 Register */
__I uint32_t NANDECCEA3; /*!< [0x090c] NAND Flash ECC Error Byte Address 3 Register */
__I uint32_t NANDECCEA4; /*!< [0x0910] NAND Flash ECC Error Byte Address 4 Register */
__I uint32_t NANDECCEA5; /*!< [0x0914] NAND Flash ECC Error Byte Address 5 Register */
__I uint32_t NANDECCEA6; /*!< [0x0918] NAND Flash ECC Error Byte Address 6 Register */
__I uint32_t NANDECCEA7; /*!< [0x091c] NAND Flash ECC Error Byte Address 7 Register */
__I uint32_t NANDECCEA8; /*!< [0x0920] NAND Flash ECC Error Byte Address 8 Register */
__I uint32_t NANDECCEA9; /*!< [0x0924] NAND Flash ECC Error Byte Address 9 Register */
__I uint32_t NANDECCEA10; /*!< [0x0928] NAND Flash ECC Error Byte Address 10 Register */
__I uint32_t NANDECCEA11; /*!< [0x092c] NAND Flash ECC Error Byte Address 11 Register */
__I uint32_t RESERVE6[12];
__I uint32_t NANDECCED0; /*!< [0x0960] NAND Flash ECC Error Data Register 0 */
__I uint32_t NANDECCED1; /*!< [0x0964] NAND Flash ECC Error Data Register 1 */
__I uint32_t NANDECCED2; /*!< [0x0968] NAND Flash ECC Error Data Register 2 */
__I uint32_t NANDECCED3; /*!< [0x096c] NAND Flash ECC Error Data Register 3 */
__I uint32_t NANDECCED4; /*!< [0x0970] NAND Flash ECC Error Data Register 4 */
__I uint32_t NANDECCED5; /*!< [0x0974] NAND Flash ECC Error Data Register 5 */
__I uint32_t RESERVE7[34];
__IO uint32_t NANDRA0; /*!< [0x0a00] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA1; /*!< [0x0a04] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA2; /*!< [0x0a08] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA3; /*!< [0x0a0c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA4; /*!< [0x0a10] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA5; /*!< [0x0a14] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA6; /*!< [0x0a18] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA7; /*!< [0x0a1c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA8; /*!< [0x0a20] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA9; /*!< [0x0a24] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA10; /*!< [0x0a28] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA11; /*!< [0x0a2c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA12; /*!< [0x0a30] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA13; /*!< [0x0a34] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA14; /*!< [0x0a38] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA15; /*!< [0x0a3c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA16; /*!< [0x0a40] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA17; /*!< [0x0a44] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA18; /*!< [0x0a48] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA19; /*!< [0x0a4c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA20; /*!< [0x0a50] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA21; /*!< [0x0a54] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA22; /*!< [0x0a58] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA23; /*!< [0x0a5c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA24; /*!< [0x0a60] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA25; /*!< [0x0a64] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA26; /*!< [0x0a68] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA27; /*!< [0x0a6c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA28; /*!< [0x0a70] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA29; /*!< [0x0a74] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA30; /*!< [0x0a78] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA31; /*!< [0x0a7c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA32; /*!< [0x0a80] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA33; /*!< [0x0a84] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA34; /*!< [0x0a88] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA35; /*!< [0x0a8c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA36; /*!< [0x0a90] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA37; /*!< [0x0a94] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA38; /*!< [0x0a98] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA39; /*!< [0x0a9c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA40; /*!< [0x0aa0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA41; /*!< [0x0aa4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA42; /*!< [0x0aa8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA43; /*!< [0x0aac] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA44; /*!< [0x0ab0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA45; /*!< [0x0ab4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA46; /*!< [0x0ab8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA47; /*!< [0x0abc] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA48; /*!< [0x0ac0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA49; /*!< [0x0ac4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA50; /*!< [0x0ac8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA51; /*!< [0x0acc] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA52; /*!< [0x0ad0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA53; /*!< [0x0ad4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA54; /*!< [0x0ad8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA55; /*!< [0x0adc] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA56; /*!< [0x0ae0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA57; /*!< [0x0ae4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA58; /*!< [0x0ae8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA59; /*!< [0x0aec] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA60; /*!< [0x0af0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA61; /*!< [0x0af4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA62; /*!< [0x0af8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA63; /*!< [0x0afc] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA64; /*!< [0x0b00] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA65; /*!< [0x0b04] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA66; /*!< [0x0b08] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA67; /*!< [0x0b0c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA68; /*!< [0x0b10] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA69; /*!< [0x0b14] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA70; /*!< [0x0b18] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA71; /*!< [0x0b1c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA72; /*!< [0x0b20] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA73; /*!< [0x0b24] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA74; /*!< [0x0b28] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA75; /*!< [0x0b2c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA76; /*!< [0x0b30] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA77; /*!< [0x0b34] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA78; /*!< [0x0b38] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA79; /*!< [0x0b3c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA80; /*!< [0x0b40] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA81; /*!< [0x0b44] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA82; /*!< [0x0b48] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA83; /*!< [0x0b4c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA84; /*!< [0x0b50] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA85; /*!< [0x0b54] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA86; /*!< [0x0b58] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA87; /*!< [0x0b5c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA88; /*!< [0x0b60] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA89; /*!< [0x0b64] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA90; /*!< [0x0b68] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA91; /*!< [0x0b6c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA92; /*!< [0x0b70] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA93; /*!< [0x0b74] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA94; /*!< [0x0b78] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA95; /*!< [0x0b7c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA96; /*!< [0x0b80] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA97; /*!< [0x0b84] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA98; /*!< [0x0b88] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA99; /*!< [0x0b8c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA100; /*!< [0x0b90] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA101; /*!< [0x0b94] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA102; /*!< [0x0b98] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA103; /*!< [0x0b9c] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA104; /*!< [0x0ba0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA105; /*!< [0x0ba4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA106; /*!< [0x0ba8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA107; /*!< [0x0bac] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA108; /*!< [0x0bb0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA109; /*!< [0x0bb4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA110; /*!< [0x0bb8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA111; /*!< [0x0bbc] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA112; /*!< [0x0bc0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA113; /*!< [0x0bc4] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA114; /*!< [0x0bc8] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA115; /*!< [0x0bcc] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA116; /*!< [0x0bd0] NAND Flash Redundant Area Word n */
__IO uint32_t NANDRA117; /*!< [0x0bd4] NAND Flash Redundant Area Word n */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE4[3]; /*!< [0x08C4~0x08CC] */
/** @endcond */
__I uint32_t NANDECCES[4]; /*!< [0x08d0] NAND Flash ECC Error Status 0 Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE5[8]; /*!< [0x08E0~0x08FC] */
/** @endcond */
__I uint32_t NANDECCEA[12]; /*!< [0x0900] NAND Flash ECC Error Byte Address 0 Register */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE6[12]; /*!< [0x0930~0x095C] */
/** @endcond */
__I uint32_t NANDECCED[6]; /*!< [0x0960] NAND Flash ECC Error Data Register 0 */
/** @cond HIDDEN_SYMBOLS */
__I uint32_t RESERVE7[34]; /*!< [0x0978~0x09FC] */
/** @endcond */
__IO uint32_t NANDRA[118]; /*!< [0x0a00] NAND Flash Redundant Area Word n */
} NFI_T;
/**
@ -2008,101 +1856,8 @@ typedef struct
Constant Definitions for NFI Controller
@{ */
#define NFI_BUFFER0_Data_Pos (0) /*!< NFI_T::BUFFER0: Data Position */
#define NFI_BUFFER0_Data_Msk (0xfffffffful << NFI_BUFFER0_Data_Pos) /*!< NFI_T::BUFFER0: Data Mask */
#define NFI_BUFFER1_Data_Pos (0) /*!< NFI_T::BUFFER1: Data Position */
#define NFI_BUFFER1_Data_Msk (0xfffffffful << NFI_BUFFER1_Data_Pos) /*!< NFI_T::BUFFER1: Data Mask */
#define NFI_BUFFER2_Data_Pos (0) /*!< NFI_T::BUFFER2: Data Position */
#define NFI_BUFFER2_Data_Msk (0xfffffffful << NFI_BUFFER2_Data_Pos) /*!< NFI_T::BUFFER2: Data Mask */
#define NFI_BUFFER3_Data_Pos (0) /*!< NFI_T::BUFFER3: Data Position */
#define NFI_BUFFER3_Data_Msk (0xfffffffful << NFI_BUFFER3_Data_Pos) /*!< NFI_T::BUFFER3: Data Mask */
#define NFI_BUFFER4_Data_Pos (0) /*!< NFI_T::BUFFER4: Data Position */
#define NFI_BUFFER4_Data_Msk (0xfffffffful << NFI_BUFFER4_Data_Pos) /*!< NFI_T::BUFFER4: Data Mask */
#define NFI_BUFFER5_Data_Pos (0) /*!< NFI_T::BUFFER5: Data Position */
#define NFI_BUFFER5_Data_Msk (0xfffffffful << NFI_BUFFER5_Data_Pos) /*!< NFI_T::BUFFER5: Data Mask */
#define NFI_BUFFER6_Data_Pos (0) /*!< NFI_T::BUFFER6: Data Position */
#define NFI_BUFFER6_Data_Msk (0xfffffffful << NFI_BUFFER6_Data_Pos) /*!< NFI_T::BUFFER6: Data Mask */
#define NFI_BUFFER7_Data_Pos (0) /*!< NFI_T::BUFFER7: Data Position */
#define NFI_BUFFER7_Data_Msk (0xfffffffful << NFI_BUFFER7_Data_Pos) /*!< NFI_T::BUFFER7: Data Mask */
#define NFI_BUFFER8_Data_Pos (0) /*!< NFI_T::BUFFER8: Data Position */
#define NFI_BUFFER8_Data_Msk (0xfffffffful << NFI_BUFFER8_Data_Pos) /*!< NFI_T::BUFFER8: Data Mask */
#define NFI_BUFFER9_Data_Pos (0) /*!< NFI_T::BUFFER9: Data Position */
#define NFI_BUFFER9_Data_Msk (0xfffffffful << NFI_BUFFER9_Data_Pos) /*!< NFI_T::BUFFER9: Data Mask */
#define NFI_BUFFER10_Data_Pos (0) /*!< NFI_T::BUFFER10: Data Position */
#define NFI_BUFFER10_Data_Msk (0xfffffffful << NFI_BUFFER10_Data_Pos) /*!< NFI_T::BUFFER10: Data Mask */
#define NFI_BUFFER11_Data_Pos (0) /*!< NFI_T::BUFFER11: Data Position */
#define NFI_BUFFER11_Data_Msk (0xfffffffful << NFI_BUFFER11_Data_Pos) /*!< NFI_T::BUFFER11: Data Mask */
#define NFI_BUFFER12_Data_Pos (0) /*!< NFI_T::BUFFER12: Data Position */
#define NFI_BUFFER12_Data_Msk (0xfffffffful << NFI_BUFFER12_Data_Pos) /*!< NFI_T::BUFFER12: Data Mask */
#define NFI_BUFFER13_Data_Pos (0) /*!< NFI_T::BUFFER13: Data Position */
#define NFI_BUFFER13_Data_Msk (0xfffffffful << NFI_BUFFER13_Data_Pos) /*!< NFI_T::BUFFER13: Data Mask */
#define NFI_BUFFER14_Data_Pos (0) /*!< NFI_T::BUFFER14: Data Position */
#define NFI_BUFFER14_Data_Msk (0xfffffffful << NFI_BUFFER14_Data_Pos) /*!< NFI_T::BUFFER14: Data Mask */
#define NFI_BUFFER15_Data_Pos (0) /*!< NFI_T::BUFFER15: Data Position */
#define NFI_BUFFER15_Data_Msk (0xfffffffful << NFI_BUFFER15_Data_Pos) /*!< NFI_T::BUFFER15: Data Mask */
#define NFI_BUFFER16_Data_Pos (0) /*!< NFI_T::BUFFER16: Data Position */
#define NFI_BUFFER16_Data_Msk (0xfffffffful << NFI_BUFFER16_Data_Pos) /*!< NFI_T::BUFFER16: Data Mask */
#define NFI_BUFFER17_Data_Pos (0) /*!< NFI_T::BUFFER17: Data Position */
#define NFI_BUFFER17_Data_Msk (0xfffffffful << NFI_BUFFER17_Data_Pos) /*!< NFI_T::BUFFER17: Data Mask */
#define NFI_BUFFER18_Data_Pos (0) /*!< NFI_T::BUFFER18: Data Position */
#define NFI_BUFFER18_Data_Msk (0xfffffffful << NFI_BUFFER18_Data_Pos) /*!< NFI_T::BUFFER18: Data Mask */
#define NFI_BUFFER19_Data_Pos (0) /*!< NFI_T::BUFFER19: Data Position */
#define NFI_BUFFER19_Data_Msk (0xfffffffful << NFI_BUFFER19_Data_Pos) /*!< NFI_T::BUFFER19: Data Mask */
#define NFI_BUFFER20_Data_Pos (0) /*!< NFI_T::BUFFER20: Data Position */
#define NFI_BUFFER20_Data_Msk (0xfffffffful << NFI_BUFFER20_Data_Pos) /*!< NFI_T::BUFFER20: Data Mask */
#define NFI_BUFFER21_Data_Pos (0) /*!< NFI_T::BUFFER21: Data Position */
#define NFI_BUFFER21_Data_Msk (0xfffffffful << NFI_BUFFER21_Data_Pos) /*!< NFI_T::BUFFER21: Data Mask */
#define NFI_BUFFER22_Data_Pos (0) /*!< NFI_T::BUFFER22: Data Position */
#define NFI_BUFFER22_Data_Msk (0xfffffffful << NFI_BUFFER22_Data_Pos) /*!< NFI_T::BUFFER22: Data Mask */
#define NFI_BUFFER23_Data_Pos (0) /*!< NFI_T::BUFFER23: Data Position */
#define NFI_BUFFER23_Data_Msk (0xfffffffful << NFI_BUFFER23_Data_Pos) /*!< NFI_T::BUFFER23: Data Mask */
#define NFI_BUFFER24_Data_Pos (0) /*!< NFI_T::BUFFER24: Data Position */
#define NFI_BUFFER24_Data_Msk (0xfffffffful << NFI_BUFFER24_Data_Pos) /*!< NFI_T::BUFFER24: Data Mask */
#define NFI_BUFFER25_Data_Pos (0) /*!< NFI_T::BUFFER25: Data Position */
#define NFI_BUFFER25_Data_Msk (0xfffffffful << NFI_BUFFER25_Data_Pos) /*!< NFI_T::BUFFER25: Data Mask */
#define NFI_BUFFER26_Data_Pos (0) /*!< NFI_T::BUFFER26: Data Position */
#define NFI_BUFFER26_Data_Msk (0xfffffffful << NFI_BUFFER26_Data_Pos) /*!< NFI_T::BUFFER26: Data Mask */
#define NFI_BUFFER27_Data_Pos (0) /*!< NFI_T::BUFFER27: Data Position */
#define NFI_BUFFER27_Data_Msk (0xfffffffful << NFI_BUFFER27_Data_Pos) /*!< NFI_T::BUFFER27: Data Mask */
#define NFI_BUFFER28_Data_Pos (0) /*!< NFI_T::BUFFER28: Data Position */
#define NFI_BUFFER28_Data_Msk (0xfffffffful << NFI_BUFFER28_Data_Pos) /*!< NFI_T::BUFFER28: Data Mask */
#define NFI_BUFFER29_Data_Pos (0) /*!< NFI_T::BUFFER29: Data Position */
#define NFI_BUFFER29_Data_Msk (0xfffffffful << NFI_BUFFER29_Data_Pos) /*!< NFI_T::BUFFER29: Data Mask */
#define NFI_BUFFER30_Data_Pos (0) /*!< NFI_T::BUFFER30: Data Position */
#define NFI_BUFFER30_Data_Msk (0xfffffffful << NFI_BUFFER30_Data_Pos) /*!< NFI_T::BUFFER30: Data Mask */
#define NFI_BUFFER31_Data_Pos (0) /*!< NFI_T::BUFFER31: Data Position */
#define NFI_BUFFER31_Data_Msk (0xfffffffful << NFI_BUFFER31_Data_Pos) /*!< NFI_T::BUFFER31: Data Mask */
#define NFI_BUFFER_Data_Pos (0) /*!< NFI_T::BUFFER0: Data Position */
#define NFI_BUFFER_Data_Msk (0xfffffffful << NFI_BUFFER0_Data_Pos) /*!< NFI_T::BUFFER0: Data Mask */
#define NFI_DMACTL_DMACEN_Pos (0) /*!< NFI_T::DMACTL: DMACEN Position */
#define NFI_DMACTL_DMACEN_Msk (0x1ul << NFI_DMACTL_DMACEN_Pos) /*!< NFI_T::DMACTL: DMACEN Mask */
@ -2185,6 +1940,9 @@ typedef struct
#define NFI_NANDCTL_CS0_Pos (25) /*!< NFI_T::NANDCTL: CS0 Position */
#define NFI_NANDCTL_CS0_Msk (0x1ul << NFI_NANDCTL_CS0_Pos) /*!< NFI_T::NANDCTL: CS0 Mask */
#define NFI_NANDCTL_CS1_Pos (26) /*!< NFI_T::NANDCTL: CS1 Position */
#define NFI_NANDCTL_CS1_Msk (0x1ul << NFI_NANDCTL_CS1_Pos) /*!< NFI_T::NANDCTL: CS1 Mask */
#define NFI_NANDTMCTL_LOWID_Pos (0) /*!< NFI_T::NANDTMCTL: LOWID Position */
#define NFI_NANDTMCTL_LOWID_Msk (0xfful << NFI_NANDTMCTL_LOWID_Pos) /*!< NFI_T::NANDTMCTL: LOWID Mask */
@ -2245,599 +2003,32 @@ typedef struct
#define NFI_NANDECTL_WP_Pos (0) /*!< NFI_T::NANDECTL: WP Position */
#define NFI_NANDECTL_WP_Msk (0x1ul << NFI_NANDECTL_WP_Pos) /*!< NFI_T::NANDECTL: WP Mask */
#define NFI_NANDECCES0_F1STAT_Pos (0) /*!< NFI_T::NANDECCES0: F1STAT Position */
#define NFI_NANDECCES0_F1STAT_Msk (0x3ul << NFI_NANDECCES0_F1STAT_Pos) /*!< NFI_T::NANDECCES0: F1STAT Mask */
#define NFI_NANDECCES_F1STAT_Pos (0) /*!< NFI_T::NANDECCES: F1STAT Position */
#define NFI_NANDECCES_F1STAT_Msk (0x3ul << NFI_NANDECCES_F1STAT_Pos) /*!< NFI_T::NANDECCES: F1STAT Mask */
#define NFI_NANDECCES0_F1ECNT_Pos (2) /*!< NFI_T::NANDECCES0: F1ECNT Position */
#define NFI_NANDECCES0_F1ECNT_Msk (0x1ful << NFI_NANDECCES0_F1ECNT_Pos) /*!< NFI_T::NANDECCES0: F1ECNT Mask */
#define NFI_NANDECCES_F1ECNT_Pos (2) /*!< NFI_T::NANDECCES: F1ECNT Position */
#define NFI_NANDECCES_F1ECNT_Msk (0x1ful << NFI_NANDECCES_F1ECNT_Pos) /*!< NFI_T::NANDECCES: F1ECNT Mask */
#define NFI_NANDECCES0_F2STAT_Pos (8) /*!< NFI_T::NANDECCES0: F2STAT Position */
#define NFI_NANDECCES0_F2STAT_Msk (0x3ul << NFI_NANDECCES0_F2STAT_Pos) /*!< NFI_T::NANDECCES0: F2STAT Mask */
#define NFI_NANDECCES_F2STAT_Pos (8) /*!< NFI_T::NANDECCES: F2STAT Position */
#define NFI_NANDECCES_F2STAT_Msk (0x3ul << NFI_NANDECCES_F2STAT_Pos) /*!< NFI_T::NANDECCES: F2STAT Mask */
#define NFI_NANDECCES0_F2ECNT_Pos (10) /*!< NFI_T::NANDECCES0: F2ECNT Position */
#define NFI_NANDECCES0_F2ECNT_Msk (0x1ful << NFI_NANDECCES0_F2ECNT_Pos) /*!< NFI_T::NANDECCES0: F2ECNT Mask */
#define NFI_NANDECCES_F2ECNT_Pos (10) /*!< NFI_T::NANDECCES: F2ECNT Position */
#define NFI_NANDECCES_F2ECNT_Msk (0x1ful << NFI_NANDECCES_F2ECNT_Pos) /*!< NFI_T::NANDECCES: F2ECNT Mask */
#define NFI_NANDECCES0_F3STAT_Pos (16) /*!< NFI_T::NANDECCES0: F3STAT Position */
#define NFI_NANDECCES0_F3STAT_Msk (0x3ul << NFI_NANDECCES0_F3STAT_Pos) /*!< NFI_T::NANDECCES0: F3STAT Mask */
#define NFI_NANDECCES_F3STAT_Pos (16) /*!< NFI_T::NANDECCES: F3STAT Position */
#define NFI_NANDECCES_F3STAT_Msk (0x3ul << NFI_NANDECCES_F3STAT_Pos) /*!< NFI_T::NANDECCES: F3STAT Mask */
#define NFI_NANDECCES0_F3ECNT_Pos (18) /*!< NFI_T::NANDECCES0: F3ECNT Position */
#define NFI_NANDECCES0_F3ECNT_Msk (0x1ful << NFI_NANDECCES0_F3ECNT_Pos) /*!< NFI_T::NANDECCES0: F3ECNT Mask */
#define NFI_NANDECCES_F3ECNT_Pos (18) /*!< NFI_T::NANDECCES: F3ECNT Position */
#define NFI_NANDECCES_F3ECNT_Msk (0x1ful << NFI_NANDECCES_F3ECNT_Pos) /*!< NFI_T::NANDECCES: F3ECNT Mask */
#define NFI_NANDECCES0_F4STAT_Pos (24) /*!< NFI_T::NANDECCES0: F4STAT Position */
#define NFI_NANDECCES0_F4STAT_Msk (0x3ul << NFI_NANDECCES0_F4STAT_Pos) /*!< NFI_T::NANDECCES0: F4STAT Mask */
#define NFI_NANDECCES_F4STAT_Pos (24) /*!< NFI_T::NANDECCES: F4STAT Position */
#define NFI_NANDECCES_F4STAT_Msk (0x3ul << NFI_NANDECCES_F4STAT_Pos) /*!< NFI_T::NANDECCES: F4STAT Mask */
#define NFI_NANDECCES0_F4ECNT_Pos (26) /*!< NFI_T::NANDECCES0: F4ECNT Position */
#define NFI_NANDECCES0_F4ECNT_Msk (0x1ful << NFI_NANDECCES0_F4ECNT_Pos) /*!< NFI_T::NANDECCES0: F4ECNT Mask */
#define NFI_NANDECCES_F4ECNT_Pos (26) /*!< NFI_T::NANDECCES: F4ECNT Position */
#define NFI_NANDECCES_F4ECNT_Msk (0x1ful << NFI_NANDECCES_F4ECNT_Pos) /*!< NFI_T::NANDECCES: F4ECNT Mask */
#define NFI_NANDECCES1_F5STAT_Pos (0) /*!< NFI_T::NANDECCES1: F5STAT Position */
#define NFI_NANDECCES1_F5STAT_Msk (0x3ul << NFI_NANDECCES1_F5STAT_Pos) /*!< NFI_T::NANDECCES1: F5STAT Mask */
#define NFI_NANDECCES1_F5ECNT_Pos (2) /*!< NFI_T::NANDECCES1: F5ECNT Position */
#define NFI_NANDECCES1_F5ECNT_Msk (0x1ful << NFI_NANDECCES1_F5ECNT_Pos) /*!< NFI_T::NANDECCES1: F5ECNT Mask */
#define NFI_NANDECCES1_F6STAT_Pos (8) /*!< NFI_T::NANDECCES1: F6STAT Position */
#define NFI_NANDECCES1_F6STAT_Msk (0x3ul << NFI_NANDECCES1_F6STAT_Pos) /*!< NFI_T::NANDECCES1: F6STAT Mask */
#define NFI_NANDECCES1_F6ECNT_Pos (10) /*!< NFI_T::NANDECCES1: F6ECNT Position */
#define NFI_NANDECCES1_F6ECNT_Msk (0x1ful << NFI_NANDECCES1_F6ECNT_Pos) /*!< NFI_T::NANDECCES1: F6ECNT Mask */
#define NFI_NANDECCES1_F7STAT_Pos (16) /*!< NFI_T::NANDECCES1: F7STAT Position */
#define NFI_NANDECCES1_F7STAT_Msk (0x3ul << NFI_NANDECCES1_F7STAT_Pos) /*!< NFI_T::NANDECCES1: F7STAT Mask */
#define NFI_NANDECCES1_F7ECNT_Pos (18) /*!< NFI_T::NANDECCES1: F7ECNT Position */
#define NFI_NANDECCES1_F7ECNT_Msk (0x1ful << NFI_NANDECCES1_F7ECNT_Pos) /*!< NFI_T::NANDECCES1: F7ECNT Mask */
#define NFI_NANDECCES1_F8STAT_Pos (24) /*!< NFI_T::NANDECCES1: F8STAT Position */
#define NFI_NANDECCES1_F8STAT_Msk (0x3ul << NFI_NANDECCES1_F8STAT_Pos) /*!< NFI_T::NANDECCES1: F8STAT Mask */
#define NFI_NANDECCES1_F8ECNT_Pos (26) /*!< NFI_T::NANDECCES1: F8ECNT Position */
#define NFI_NANDECCES1_F8ECNT_Msk (0x1ful << NFI_NANDECCES1_F8ECNT_Pos) /*!< NFI_T::NANDECCES1: F8ECNT Mask */
#define NFI_NANDECCES2_F9STAT_Pos (0) /*!< NFI_T::NANDECCES2: F9STAT Position */
#define NFI_NANDECCES2_F9STAT_Msk (0x3ul << NFI_NANDECCES2_F9STAT_Pos) /*!< NFI_T::NANDECCES2: F9STAT Mask */
#define NFI_NANDECCES2_F9ECNT_Pos (2) /*!< NFI_T::NANDECCES2: F9ECNT Position */
#define NFI_NANDECCES2_F9ECNT_Msk (0x1ful << NFI_NANDECCES2_F9ECNT_Pos) /*!< NFI_T::NANDECCES2: F9ECNT Mask */
#define NFI_NANDECCES2_F10STAT_Pos (8) /*!< NFI_T::NANDECCES2: F10STAT Position */
#define NFI_NANDECCES2_F10STAT_Msk (0x3ul << NFI_NANDECCES2_F10STAT_Pos) /*!< NFI_T::NANDECCES2: F10STAT Mask */
#define NFI_NANDECCES2_F10ECNT_Pos (10) /*!< NFI_T::NANDECCES2: F10ECNT Position */
#define NFI_NANDECCES2_F10ECNT_Msk (0x1ful << NFI_NANDECCES2_F10ECNT_Pos) /*!< NFI_T::NANDECCES2: F10ECNT Mask */
#define NFI_NANDECCES2_F11STAT_Pos (16) /*!< NFI_T::NANDECCES2: F11STAT Position */
#define NFI_NANDECCES2_F11STAT_Msk (0x3ul << NFI_NANDECCES2_F11STAT_Pos) /*!< NFI_T::NANDECCES2: F11STAT Mask */
#define NFI_NANDECCES2_F11ECNT_Pos (18) /*!< NFI_T::NANDECCES2: F11ECNT Position */
#define NFI_NANDECCES2_F11ECNT_Msk (0x1ful << NFI_NANDECCES2_F11ECNT_Pos) /*!< NFI_T::NANDECCES2: F11ECNT Mask */
#define NFI_NANDECCES2_F12STAT_Pos (24) /*!< NFI_T::NANDECCES2: F12STAT Position */
#define NFI_NANDECCES2_F12STAT_Msk (0x3ul << NFI_NANDECCES2_F12STAT_Pos) /*!< NFI_T::NANDECCES2: F12STAT Mask */
#define NFI_NANDECCES2_F12ECNT_Pos (26) /*!< NFI_T::NANDECCES2: F12ECNT Position */
#define NFI_NANDECCES2_F12ECNT_Msk (0x1ful << NFI_NANDECCES2_F12ECNT_Pos) /*!< NFI_T::NANDECCES2: F12ECNT Mask */
#define NFI_NANDECCES3_F13STAT_Pos (0) /*!< NFI_T::NANDECCES3: F13STAT Position */
#define NFI_NANDECCES3_F13STAT_Msk (0x3ul << NFI_NANDECCES3_F13STAT_Pos) /*!< NFI_T::NANDECCES3: F13STAT Mask */
#define NFI_NANDECCES3_F13ECNT_Pos (2) /*!< NFI_T::NANDECCES3: F13ECNT Position */
#define NFI_NANDECCES3_F13ECNT_Msk (0x1ful << NFI_NANDECCES3_F13ECNT_Pos) /*!< NFI_T::NANDECCES3: F13ECNT Mask */
#define NFI_NANDECCES3_F14STAT_Pos (8) /*!< NFI_T::NANDECCES3: F14STAT Position */
#define NFI_NANDECCES3_F14STAT_Msk (0x3ul << NFI_NANDECCES3_F14STAT_Pos) /*!< NFI_T::NANDECCES3: F14STAT Mask */
#define NFI_NANDECCES3_F14ECNT_Pos (10) /*!< NFI_T::NANDECCES3: F14ECNT Position */
#define NFI_NANDECCES3_F14ECNT_Msk (0x1ful << NFI_NANDECCES3_F14ECNT_Pos) /*!< NFI_T::NANDECCES3: F14ECNT Mask */
#define NFI_NANDECCES3_F15STAT_Pos (16) /*!< NFI_T::NANDECCES3: F15STAT Position */
#define NFI_NANDECCES3_F15STAT_Msk (0x3ul << NFI_NANDECCES3_F15STAT_Pos) /*!< NFI_T::NANDECCES3: F15STAT Mask */
#define NFI_NANDECCES3_F15ECNT_Pos (18) /*!< NFI_T::NANDECCES3: F15ECNT Position */
#define NFI_NANDECCES3_F15ECNT_Msk (0x1ful << NFI_NANDECCES3_F15ECNT_Pos) /*!< NFI_T::NANDECCES3: F15ECNT Mask */
#define NFI_NANDECCES3_F16STAT_Pos (24) /*!< NFI_T::NANDECCES3: F16STAT Position */
#define NFI_NANDECCES3_F16STAT_Msk (0x3ul << NFI_NANDECCES3_F16STAT_Pos) /*!< NFI_T::NANDECCES3: F16STAT Mask */
#define NFI_NANDECCES3_F16ECNT_Pos (26) /*!< NFI_T::NANDECCES3: F16ECNT Position */
#define NFI_NANDECCES3_F16ECNT_Msk (0x1ful << NFI_NANDECCES3_F16ECNT_Pos) /*!< NFI_T::NANDECCES3: F16ECNT Mask */
#define NFI_NANDECCEA0_ERRADDR0_Pos (0) /*!< NFI_T::NANDECCEA0: ERRADDR0 Position */
#define NFI_NANDECCEA0_ERRADDR0_Msk (0x7fful << NFI_NANDECCEA0_ERRADDR0_Pos) /*!< NFI_T::NANDECCEA0: ERRADDR0 Mask */
#define NFI_NANDECCEA0_ERRADDR1_Pos (16) /*!< NFI_T::NANDECCEA0: ERRADDR1 Position */
#define NFI_NANDECCEA0_ERRADDR1_Msk (0x7fful << NFI_NANDECCEA0_ERRADDR1_Pos) /*!< NFI_T::NANDECCEA0: ERRADDR1 Mask */
#define NFI_NANDECCEA1_ERRADDR2_Pos (0) /*!< NFI_T::NANDECCEA1: ERRADDR2 Position */
#define NFI_NANDECCEA1_ERRADDR2_Msk (0x7fful << NFI_NANDECCEA1_ERRADDR2_Pos) /*!< NFI_T::NANDECCEA1: ERRADDR2 Mask */
#define NFI_NANDECCEA1_ERRADDR3_Pos (16) /*!< NFI_T::NANDECCEA1: ERRADDR3 Position */
#define NFI_NANDECCEA1_ERRADDR3_Msk (0x7fful << NFI_NANDECCEA1_ERRADDR3_Pos) /*!< NFI_T::NANDECCEA1: ERRADDR3 Mask */
#define NFI_NANDECCEA2_ERRADDR4_Pos (0) /*!< NFI_T::NANDECCEA2: ERRADDR4 Position */
#define NFI_NANDECCEA2_ERRADDR4_Msk (0x7fful << NFI_NANDECCEA2_ERRADDR4_Pos) /*!< NFI_T::NANDECCEA2: ERRADDR4 Mask */
#define NFI_NANDECCEA2_ERRADDR5_Pos (16) /*!< NFI_T::NANDECCEA2: ERRADDR5 Position */
#define NFI_NANDECCEA2_ERRADDR5_Msk (0x7fful << NFI_NANDECCEA2_ERRADDR5_Pos) /*!< NFI_T::NANDECCEA2: ERRADDR5 Mask */
#define NFI_NANDECCEA3_ERRADDR6_Pos (0) /*!< NFI_T::NANDECCEA3: ERRADDR6 Position */
#define NFI_NANDECCEA3_ERRADDR6_Msk (0x7fful << NFI_NANDECCEA3_ERRADDR6_Pos) /*!< NFI_T::NANDECCEA3: ERRADDR6 Mask */
#define NFI_NANDECCEA3_ERRADDR7_Pos (16) /*!< NFI_T::NANDECCEA3: ERRADDR7 Position */
#define NFI_NANDECCEA3_ERRADDR7_Msk (0x7fful << NFI_NANDECCEA3_ERRADDR7_Pos) /*!< NFI_T::NANDECCEA3: ERRADDR7 Mask */
#define NFI_NANDECCEA4_ERRADDR8_Pos (0) /*!< NFI_T::NANDECCEA4: ERRADDR8 Position */
#define NFI_NANDECCEA4_ERRADDR8_Msk (0x7fful << NFI_NANDECCEA4_ERRADDR8_Pos) /*!< NFI_T::NANDECCEA4: ERRADDR8 Mask */
#define NFI_NANDECCEA4_ERRADDR9_Pos (16) /*!< NFI_T::NANDECCEA4: ERRADDR9 Position */
#define NFI_NANDECCEA4_ERRADDR9_Msk (0x7fful << NFI_NANDECCEA4_ERRADDR9_Pos) /*!< NFI_T::NANDECCEA4: ERRADDR9 Mask */
#define NFI_NANDECCEA5_ERRADDR10_Pos (0) /*!< NFI_T::NANDECCEA5: ERRADDR10 Position */
#define NFI_NANDECCEA5_ERRADDR10_Msk (0x7fful << NFI_NANDECCEA5_ERRADDR10_Pos) /*!< NFI_T::NANDECCEA5: ERRADDR10 Mask */
#define NFI_NANDECCEA5_ERRADDR11_Pos (16) /*!< NFI_T::NANDECCEA5: ERRADDR11 Position */
#define NFI_NANDECCEA5_ERRADDR11_Msk (0x7fful << NFI_NANDECCEA5_ERRADDR11_Pos) /*!< NFI_T::NANDECCEA5: ERRADDR11 Mask */
#define NFI_NANDECCEA6_ERRADDR12_Pos (0) /*!< NFI_T::NANDECCEA6: ERRADDR12 Position */
#define NFI_NANDECCEA6_ERRADDR12_Msk (0x7fful << NFI_NANDECCEA6_ERRADDR12_Pos) /*!< NFI_T::NANDECCEA6: ERRADDR12 Mask */
#define NFI_NANDECCEA6_ERRADDR13_Pos (16) /*!< NFI_T::NANDECCEA6: ERRADDR13 Position */
#define NFI_NANDECCEA6_ERRADDR13_Msk (0x7fful << NFI_NANDECCEA6_ERRADDR13_Pos) /*!< NFI_T::NANDECCEA6: ERRADDR13 Mask */
#define NFI_NANDECCEA7_ERRADDR14_Pos (0) /*!< NFI_T::NANDECCEA7: ERRADDR14 Position */
#define NFI_NANDECCEA7_ERRADDR14_Msk (0x7fful << NFI_NANDECCEA7_ERRADDR14_Pos) /*!< NFI_T::NANDECCEA7: ERRADDR14 Mask */
#define NFI_NANDECCEA7_ERRADDR15_Pos (16) /*!< NFI_T::NANDECCEA7: ERRADDR15 Position */
#define NFI_NANDECCEA7_ERRADDR15_Msk (0x7fful << NFI_NANDECCEA7_ERRADDR15_Pos) /*!< NFI_T::NANDECCEA7: ERRADDR15 Mask */
#define NFI_NANDECCEA8_ERRADDR16_Pos (0) /*!< NFI_T::NANDECCEA8: ERRADDR16 Position */
#define NFI_NANDECCEA8_ERRADDR16_Msk (0x7fful << NFI_NANDECCEA8_ERRADDR16_Pos) /*!< NFI_T::NANDECCEA8: ERRADDR16 Mask */
#define NFI_NANDECCEA8_ERRADDR17_Pos (16) /*!< NFI_T::NANDECCEA8: ERRADDR17 Position */
#define NFI_NANDECCEA8_ERRADDR17_Msk (0x7fful << NFI_NANDECCEA8_ERRADDR17_Pos) /*!< NFI_T::NANDECCEA8: ERRADDR17 Mask */
#define NFI_NANDECCEA9_ERRADDR18_Pos (0) /*!< NFI_T::NANDECCEA9: ERRADDR18 Position */
#define NFI_NANDECCEA9_ERRADDR18_Msk (0x7fful << NFI_NANDECCEA9_ERRADDR18_Pos) /*!< NFI_T::NANDECCEA9: ERRADDR18 Mask */
#define NFI_NANDECCEA9_ERRADDR19_Pos (16) /*!< NFI_T::NANDECCEA9: ERRADDR19 Position */
#define NFI_NANDECCEA9_ERRADDR19_Msk (0x7fful << NFI_NANDECCEA9_ERRADDR19_Pos) /*!< NFI_T::NANDECCEA9: ERRADDR19 Mask */
#define NFI_NANDECCEA10_ERRADDR20_Pos (0) /*!< NFI_T::NANDECCEA10: ERRADDR20 Position */
#define NFI_NANDECCEA10_ERRADDR20_Msk (0x7fful << NFI_NANDECCEA10_ERRADDR20_Pos) /*!< NFI_T::NANDECCEA10: ERRADDR20 Mask */
#define NFI_NANDECCEA10_ERRADDR21_Pos (16) /*!< NFI_T::NANDECCEA10: ERRADDR21 Position */
#define NFI_NANDECCEA10_ERRADDR21_Msk (0x7fful << NFI_NANDECCEA10_ERRADDR21_Pos) /*!< NFI_T::NANDECCEA10: ERRADDR21 Mask */
#define NFI_NANDECCEA11_ERRADDR22_Pos (0) /*!< NFI_T::NANDECCEA11: ERRADDR22 Position */
#define NFI_NANDECCEA11_ERRADDR22_Msk (0x7fful << NFI_NANDECCEA11_ERRADDR22_Pos) /*!< NFI_T::NANDECCEA11: ERRADDR22 Mask */
#define NFI_NANDECCEA11_ERRADDR23_Pos (16) /*!< NFI_T::NANDECCEA11: ERRADDR23 Position */
#define NFI_NANDECCEA11_ERRADDR23_Msk (0x7fful << NFI_NANDECCEA11_ERRADDR23_Pos) /*!< NFI_T::NANDECCEA11: ERRADDR23 Mask */
#define NFI_NANDECCED0_ERRDATA0_Pos (0) /*!< NFI_T::NANDECCED0: ERRDATA0 Position */
#define NFI_NANDECCED0_ERRDATA0_Msk (0xfful << NFI_NANDECCED0_ERRDATA0_Pos) /*!< NFI_T::NANDECCED0: ERRDATA0 Mask */
#define NFI_NANDECCED0_ERRDATA1_Pos (8) /*!< NFI_T::NANDECCED0: ERRDATA1 Position */
#define NFI_NANDECCED0_ERRDATA1_Msk (0xfful << NFI_NANDECCED0_ERRDATA1_Pos) /*!< NFI_T::NANDECCED0: ERRDATA1 Mask */
#define NFI_NANDECCED0_ERRDATA2_Pos (16) /*!< NFI_T::NANDECCED0: ERRDATA2 Position */
#define NFI_NANDECCED0_ERRDATA2_Msk (0xfful << NFI_NANDECCED0_ERRDATA2_Pos) /*!< NFI_T::NANDECCED0: ERRDATA2 Mask */
#define NFI_NANDECCED0_ERRDATA3_Pos (24) /*!< NFI_T::NANDECCED0: ERRDATA3 Position */
#define NFI_NANDECCED0_ERRDATA3_Msk (0xfful << NFI_NANDECCED0_ERRDATA3_Pos) /*!< NFI_T::NANDECCED0: ERRDATA3 Mask */
#define NFI_NANDECCED1_ERRDATA4_Pos (0) /*!< NFI_T::NANDECCED1: ERRDATA4 Position */
#define NFI_NANDECCED1_ERRDATA4_Msk (0xfful << NFI_NANDECCED1_ERRDATA4_Pos) /*!< NFI_T::NANDECCED1: ERRDATA4 Mask */
#define NFI_NANDECCED1_ERRDATA5_Pos (8) /*!< NFI_T::NANDECCED1: ERRDATA5 Position */
#define NFI_NANDECCED1_ERRDATA5_Msk (0xfful << NFI_NANDECCED1_ERRDATA5_Pos) /*!< NFI_T::NANDECCED1: ERRDATA5 Mask */
#define NFI_NANDECCED1_ERRDATA6_Pos (16) /*!< NFI_T::NANDECCED1: ERRDATA6 Position */
#define NFI_NANDECCED1_ERRDATA6_Msk (0xfful << NFI_NANDECCED1_ERRDATA6_Pos) /*!< NFI_T::NANDECCED1: ERRDATA6 Mask */
#define NFI_NANDECCED1_ERRDATA7_Pos (24) /*!< NFI_T::NANDECCED1: ERRDATA7 Position */
#define NFI_NANDECCED1_ERRDATA7_Msk (0xfful << NFI_NANDECCED1_ERRDATA7_Pos) /*!< NFI_T::NANDECCED1: ERRDATA7 Mask */
#define NFI_NANDECCED2_ERRDATA8_Pos (0) /*!< NFI_T::NANDECCED2: ERRDATA8 Position */
#define NFI_NANDECCED2_ERRDATA8_Msk (0xfful << NFI_NANDECCED2_ERRDATA8_Pos) /*!< NFI_T::NANDECCED2: ERRDATA8 Mask */
#define NFI_NANDECCED2_ERRDATA9_Pos (8) /*!< NFI_T::NANDECCED2: ERRDATA9 Position */
#define NFI_NANDECCED2_ERRDATA9_Msk (0xfful << NFI_NANDECCED2_ERRDATA9_Pos) /*!< NFI_T::NANDECCED2: ERRDATA9 Mask */
#define NFI_NANDECCED2_ERRDATA10_Pos (16) /*!< NFI_T::NANDECCED2: ERRDATA10 Position */
#define NFI_NANDECCED2_ERRDATA10_Msk (0xfful << NFI_NANDECCED2_ERRDATA10_Pos) /*!< NFI_T::NANDECCED2: ERRDATA10 Mask */
#define NFI_NANDECCED2_ERRDATA11_Pos (24) /*!< NFI_T::NANDECCED2: ERRDATA11 Position */
#define NFI_NANDECCED2_ERRDATA11_Msk (0xfful << NFI_NANDECCED2_ERRDATA11_Pos) /*!< NFI_T::NANDECCED2: ERRDATA11 Mask */
#define NFI_NANDECCED3_ERRDATA12_Pos (0) /*!< NFI_T::NANDECCED3: ERRDATA12 Position */
#define NFI_NANDECCED3_ERRDATA12_Msk (0xfful << NFI_NANDECCED3_ERRDATA12_Pos) /*!< NFI_T::NANDECCED3: ERRDATA12 Mask */
#define NFI_NANDECCED3_ERRDATA13_Pos (8) /*!< NFI_T::NANDECCED3: ERRDATA13 Position */
#define NFI_NANDECCED3_ERRDATA13_Msk (0xfful << NFI_NANDECCED3_ERRDATA13_Pos) /*!< NFI_T::NANDECCED3: ERRDATA13 Mask */
#define NFI_NANDECCED3_ERRDATA14_Pos (16) /*!< NFI_T::NANDECCED3: ERRDATA14 Position */
#define NFI_NANDECCED3_ERRDATA14_Msk (0xfful << NFI_NANDECCED3_ERRDATA14_Pos) /*!< NFI_T::NANDECCED3: ERRDATA14 Mask */
#define NFI_NANDECCED3_ERRDATA15_Pos (24) /*!< NFI_T::NANDECCED3: ERRDATA15 Position */
#define NFI_NANDECCED3_ERRDATA15_Msk (0xfful << NFI_NANDECCED3_ERRDATA15_Pos) /*!< NFI_T::NANDECCED3: ERRDATA15 Mask */
#define NFI_NANDECCED4_ERRDATA16_Pos (0) /*!< NFI_T::NANDECCED4: ERRDATA16 Position */
#define NFI_NANDECCED4_ERRDATA16_Msk (0xfful << NFI_NANDECCED4_ERRDATA16_Pos) /*!< NFI_T::NANDECCED4: ERRDATA16 Mask */
#define NFI_NANDECCED4_ERRDATA17_Pos (8) /*!< NFI_T::NANDECCED4: ERRDATA17 Position */
#define NFI_NANDECCED4_ERRDATA17_Msk (0xfful << NFI_NANDECCED4_ERRDATA17_Pos) /*!< NFI_T::NANDECCED4: ERRDATA17 Mask */
#define NFI_NANDECCED4_ERRDATA18_Pos (16) /*!< NFI_T::NANDECCED4: ERRDATA18 Position */
#define NFI_NANDECCED4_ERRDATA18_Msk (0xfful << NFI_NANDECCED4_ERRDATA18_Pos) /*!< NFI_T::NANDECCED4: ERRDATA18 Mask */
#define NFI_NANDECCED4_ERRDATA19_Pos (24) /*!< NFI_T::NANDECCED4: ERRDATA19 Position */
#define NFI_NANDECCED4_ERRDATA19_Msk (0xfful << NFI_NANDECCED4_ERRDATA19_Pos) /*!< NFI_T::NANDECCED4: ERRDATA19 Mask */
#define NFI_NANDECCED5_ERRDATA20_Pos (0) /*!< NFI_T::NANDECCED5: ERRDATA20 Position */
#define NFI_NANDECCED5_ERRDATA20_Msk (0xfful << NFI_NANDECCED5_ERRDATA20_Pos) /*!< NFI_T::NANDECCED5: ERRDATA20 Mask */
#define NFI_NANDECCED5_ERRDATA21_Pos (8) /*!< NFI_T::NANDECCED5: ERRDATA21 Position */
#define NFI_NANDECCED5_ERRDATA21_Msk (0xfful << NFI_NANDECCED5_ERRDATA21_Pos) /*!< NFI_T::NANDECCED5: ERRDATA21 Mask */
#define NFI_NANDECCED5_ERRDATA22_Pos (16) /*!< NFI_T::NANDECCED5: ERRDATA22 Position */
#define NFI_NANDECCED5_ERRDATA22_Msk (0xfful << NFI_NANDECCED5_ERRDATA22_Pos) /*!< NFI_T::NANDECCED5: ERRDATA22 Mask */
#define NFI_NANDECCED5_ERRDATA23_Pos (24) /*!< NFI_T::NANDECCED5: ERRDATA23 Position */
#define NFI_NANDECCED5_ERRDATA23_Msk (0xfful << NFI_NANDECCED5_ERRDATA23_Pos) /*!< NFI_T::NANDECCED5: ERRDATA23 Mask */
#define NFI_NANDRA0_Data_Pos (0) /*!< NFI_T::NANDRA0: Data Position */
#define NFI_NANDRA0_Data_Msk (0xfffffffful << NFI_NANDRA0_Data_Pos) /*!< NFI_T::NANDRA0: Data Mask */
#define NFI_NANDRA1_Data_Pos (0) /*!< NFI_T::NANDRA1: Data Position */
#define NFI_NANDRA1_Data_Msk (0xfffffffful << NFI_NANDRA1_Data_Pos) /*!< NFI_T::NANDRA1: Data Mask */
#define NFI_NANDRA2_Data_Pos (0) /*!< NFI_T::NANDRA2: Data Position */
#define NFI_NANDRA2_Data_Msk (0xfffffffful << NFI_NANDRA2_Data_Pos) /*!< NFI_T::NANDRA2: Data Mask */
#define NFI_NANDRA3_Data_Pos (0) /*!< NFI_T::NANDRA3: Data Position */
#define NFI_NANDRA3_Data_Msk (0xfffffffful << NFI_NANDRA3_Data_Pos) /*!< NFI_T::NANDRA3: Data Mask */
#define NFI_NANDRA4_Data_Pos (0) /*!< NFI_T::NANDRA4: Data Position */
#define NFI_NANDRA4_Data_Msk (0xfffffffful << NFI_NANDRA4_Data_Pos) /*!< NFI_T::NANDRA4: Data Mask */
#define NFI_NANDRA5_Data_Pos (0) /*!< NFI_T::NANDRA5: Data Position */
#define NFI_NANDRA5_Data_Msk (0xfffffffful << NFI_NANDRA5_Data_Pos) /*!< NFI_T::NANDRA5: Data Mask */
#define NFI_NANDRA6_Data_Pos (0) /*!< NFI_T::NANDRA6: Data Position */
#define NFI_NANDRA6_Data_Msk (0xfffffffful << NFI_NANDRA6_Data_Pos) /*!< NFI_T::NANDRA6: Data Mask */
#define NFI_NANDRA7_Data_Pos (0) /*!< NFI_T::NANDRA7: Data Position */
#define NFI_NANDRA7_Data_Msk (0xfffffffful << NFI_NANDRA7_Data_Pos) /*!< NFI_T::NANDRA7: Data Mask */
#define NFI_NANDRA8_Data_Pos (0) /*!< NFI_T::NANDRA8: Data Position */
#define NFI_NANDRA8_Data_Msk (0xfffffffful << NFI_NANDRA8_Data_Pos) /*!< NFI_T::NANDRA8: Data Mask */
#define NFI_NANDRA9_Data_Pos (0) /*!< NFI_T::NANDRA9: Data Position */
#define NFI_NANDRA9_Data_Msk (0xfffffffful << NFI_NANDRA9_Data_Pos) /*!< NFI_T::NANDRA9: Data Mask */
#define NFI_NANDRA10_Data_Pos (0) /*!< NFI_T::NANDRA10: Data Position */
#define NFI_NANDRA10_Data_Msk (0xfffffffful << NFI_NANDRA10_Data_Pos) /*!< NFI_T::NANDRA10: Data Mask */
#define NFI_NANDRA11_Data_Pos (0) /*!< NFI_T::NANDRA11: Data Position */
#define NFI_NANDRA11_Data_Msk (0xfffffffful << NFI_NANDRA11_Data_Pos) /*!< NFI_T::NANDRA11: Data Mask */
#define NFI_NANDRA12_Data_Pos (0) /*!< NFI_T::NANDRA12: Data Position */
#define NFI_NANDRA12_Data_Msk (0xfffffffful << NFI_NANDRA12_Data_Pos) /*!< NFI_T::NANDRA12: Data Mask */
#define NFI_NANDRA13_Data_Pos (0) /*!< NFI_T::NANDRA13: Data Position */
#define NFI_NANDRA13_Data_Msk (0xfffffffful << NFI_NANDRA13_Data_Pos) /*!< NFI_T::NANDRA13: Data Mask */
#define NFI_NANDRA14_Data_Pos (0) /*!< NFI_T::NANDRA14: Data Position */
#define NFI_NANDRA14_Data_Msk (0xfffffffful << NFI_NANDRA14_Data_Pos) /*!< NFI_T::NANDRA14: Data Mask */
#define NFI_NANDRA15_Data_Pos (0) /*!< NFI_T::NANDRA15: Data Position */
#define NFI_NANDRA15_Data_Msk (0xfffffffful << NFI_NANDRA15_Data_Pos) /*!< NFI_T::NANDRA15: Data Mask */
#define NFI_NANDRA16_Data_Pos (0) /*!< NFI_T::NANDRA16: Data Position */
#define NFI_NANDRA16_Data_Msk (0xfffffffful << NFI_NANDRA16_Data_Pos) /*!< NFI_T::NANDRA16: Data Mask */
#define NFI_NANDRA17_Data_Pos (0) /*!< NFI_T::NANDRA17: Data Position */
#define NFI_NANDRA17_Data_Msk (0xfffffffful << NFI_NANDRA17_Data_Pos) /*!< NFI_T::NANDRA17: Data Mask */
#define NFI_NANDRA18_Data_Pos (0) /*!< NFI_T::NANDRA18: Data Position */
#define NFI_NANDRA18_Data_Msk (0xfffffffful << NFI_NANDRA18_Data_Pos) /*!< NFI_T::NANDRA18: Data Mask */
#define NFI_NANDRA19_Data_Pos (0) /*!< NFI_T::NANDRA19: Data Position */
#define NFI_NANDRA19_Data_Msk (0xfffffffful << NFI_NANDRA19_Data_Pos) /*!< NFI_T::NANDRA19: Data Mask */
#define NFI_NANDRA20_Data_Pos (0) /*!< NFI_T::NANDRA20: Data Position */
#define NFI_NANDRA20_Data_Msk (0xfffffffful << NFI_NANDRA20_Data_Pos) /*!< NFI_T::NANDRA20: Data Mask */
#define NFI_NANDRA21_Data_Pos (0) /*!< NFI_T::NANDRA21: Data Position */
#define NFI_NANDRA21_Data_Msk (0xfffffffful << NFI_NANDRA21_Data_Pos) /*!< NFI_T::NANDRA21: Data Mask */
#define NFI_NANDRA22_Data_Pos (0) /*!< NFI_T::NANDRA22: Data Position */
#define NFI_NANDRA22_Data_Msk (0xfffffffful << NFI_NANDRA22_Data_Pos) /*!< NFI_T::NANDRA22: Data Mask */
#define NFI_NANDRA23_Data_Pos (0) /*!< NFI_T::NANDRA23: Data Position */
#define NFI_NANDRA23_Data_Msk (0xfffffffful << NFI_NANDRA23_Data_Pos) /*!< NFI_T::NANDRA23: Data Mask */
#define NFI_NANDRA24_Data_Pos (0) /*!< NFI_T::NANDRA24: Data Position */
#define NFI_NANDRA24_Data_Msk (0xfffffffful << NFI_NANDRA24_Data_Pos) /*!< NFI_T::NANDRA24: Data Mask */
#define NFI_NANDRA25_Data_Pos (0) /*!< NFI_T::NANDRA25: Data Position */
#define NFI_NANDRA25_Data_Msk (0xfffffffful << NFI_NANDRA25_Data_Pos) /*!< NFI_T::NANDRA25: Data Mask */
#define NFI_NANDRA26_Data_Pos (0) /*!< NFI_T::NANDRA26: Data Position */
#define NFI_NANDRA26_Data_Msk (0xfffffffful << NFI_NANDRA26_Data_Pos) /*!< NFI_T::NANDRA26: Data Mask */
#define NFI_NANDRA27_Data_Pos (0) /*!< NFI_T::NANDRA27: Data Position */
#define NFI_NANDRA27_Data_Msk (0xfffffffful << NFI_NANDRA27_Data_Pos) /*!< NFI_T::NANDRA27: Data Mask */
#define NFI_NANDRA28_Data_Pos (0) /*!< NFI_T::NANDRA28: Data Position */
#define NFI_NANDRA28_Data_Msk (0xfffffffful << NFI_NANDRA28_Data_Pos) /*!< NFI_T::NANDRA28: Data Mask */
#define NFI_NANDRA29_Data_Pos (0) /*!< NFI_T::NANDRA29: Data Position */
#define NFI_NANDRA29_Data_Msk (0xfffffffful << NFI_NANDRA29_Data_Pos) /*!< NFI_T::NANDRA29: Data Mask */
#define NFI_NANDRA30_Data_Pos (0) /*!< NFI_T::NANDRA30: Data Position */
#define NFI_NANDRA30_Data_Msk (0xfffffffful << NFI_NANDRA30_Data_Pos) /*!< NFI_T::NANDRA30: Data Mask */
#define NFI_NANDRA31_Data_Pos (0) /*!< NFI_T::NANDRA31: Data Position */
#define NFI_NANDRA31_Data_Msk (0xfffffffful << NFI_NANDRA31_Data_Pos) /*!< NFI_T::NANDRA31: Data Mask */
#define NFI_NANDRA32_Data_Pos (0) /*!< NFI_T::NANDRA32: Data Position */
#define NFI_NANDRA32_Data_Msk (0xfffffffful << NFI_NANDRA32_Data_Pos) /*!< NFI_T::NANDRA32: Data Mask */
#define NFI_NANDRA33_Data_Pos (0) /*!< NFI_T::NANDRA33: Data Position */
#define NFI_NANDRA33_Data_Msk (0xfffffffful << NFI_NANDRA33_Data_Pos) /*!< NFI_T::NANDRA33: Data Mask */
#define NFI_NANDRA34_Data_Pos (0) /*!< NFI_T::NANDRA34: Data Position */
#define NFI_NANDRA34_Data_Msk (0xfffffffful << NFI_NANDRA34_Data_Pos) /*!< NFI_T::NANDRA34: Data Mask */
#define NFI_NANDRA35_Data_Pos (0) /*!< NFI_T::NANDRA35: Data Position */
#define NFI_NANDRA35_Data_Msk (0xfffffffful << NFI_NANDRA35_Data_Pos) /*!< NFI_T::NANDRA35: Data Mask */
#define NFI_NANDRA36_Data_Pos (0) /*!< NFI_T::NANDRA36: Data Position */
#define NFI_NANDRA36_Data_Msk (0xfffffffful << NFI_NANDRA36_Data_Pos) /*!< NFI_T::NANDRA36: Data Mask */
#define NFI_NANDRA37_Data_Pos (0) /*!< NFI_T::NANDRA37: Data Position */
#define NFI_NANDRA37_Data_Msk (0xfffffffful << NFI_NANDRA37_Data_Pos) /*!< NFI_T::NANDRA37: Data Mask */
#define NFI_NANDRA38_Data_Pos (0) /*!< NFI_T::NANDRA38: Data Position */
#define NFI_NANDRA38_Data_Msk (0xfffffffful << NFI_NANDRA38_Data_Pos) /*!< NFI_T::NANDRA38: Data Mask */
#define NFI_NANDRA39_Data_Pos (0) /*!< NFI_T::NANDRA39: Data Position */
#define NFI_NANDRA39_Data_Msk (0xfffffffful << NFI_NANDRA39_Data_Pos) /*!< NFI_T::NANDRA39: Data Mask */
#define NFI_NANDRA40_Data_Pos (0) /*!< NFI_T::NANDRA40: Data Position */
#define NFI_NANDRA40_Data_Msk (0xfffffffful << NFI_NANDRA40_Data_Pos) /*!< NFI_T::NANDRA40: Data Mask */
#define NFI_NANDRA41_Data_Pos (0) /*!< NFI_T::NANDRA41: Data Position */
#define NFI_NANDRA41_Data_Msk (0xfffffffful << NFI_NANDRA41_Data_Pos) /*!< NFI_T::NANDRA41: Data Mask */
#define NFI_NANDRA42_Data_Pos (0) /*!< NFI_T::NANDRA42: Data Position */
#define NFI_NANDRA42_Data_Msk (0xfffffffful << NFI_NANDRA42_Data_Pos) /*!< NFI_T::NANDRA42: Data Mask */
#define NFI_NANDRA43_Data_Pos (0) /*!< NFI_T::NANDRA43: Data Position */
#define NFI_NANDRA43_Data_Msk (0xfffffffful << NFI_NANDRA43_Data_Pos) /*!< NFI_T::NANDRA43: Data Mask */
#define NFI_NANDRA44_Data_Pos (0) /*!< NFI_T::NANDRA44: Data Position */
#define NFI_NANDRA44_Data_Msk (0xfffffffful << NFI_NANDRA44_Data_Pos) /*!< NFI_T::NANDRA44: Data Mask */
#define NFI_NANDRA45_Data_Pos (0) /*!< NFI_T::NANDRA45: Data Position */
#define NFI_NANDRA45_Data_Msk (0xfffffffful << NFI_NANDRA45_Data_Pos) /*!< NFI_T::NANDRA45: Data Mask */
#define NFI_NANDRA46_Data_Pos (0) /*!< NFI_T::NANDRA46: Data Position */
#define NFI_NANDRA46_Data_Msk (0xfffffffful << NFI_NANDRA46_Data_Pos) /*!< NFI_T::NANDRA46: Data Mask */
#define NFI_NANDRA47_Data_Pos (0) /*!< NFI_T::NANDRA47: Data Position */
#define NFI_NANDRA47_Data_Msk (0xfffffffful << NFI_NANDRA47_Data_Pos) /*!< NFI_T::NANDRA47: Data Mask */
#define NFI_NANDRA48_Data_Pos (0) /*!< NFI_T::NANDRA48: Data Position */
#define NFI_NANDRA48_Data_Msk (0xfffffffful << NFI_NANDRA48_Data_Pos) /*!< NFI_T::NANDRA48: Data Mask */
#define NFI_NANDRA49_Data_Pos (0) /*!< NFI_T::NANDRA49: Data Position */
#define NFI_NANDRA49_Data_Msk (0xfffffffful << NFI_NANDRA49_Data_Pos) /*!< NFI_T::NANDRA49: Data Mask */
#define NFI_NANDRA50_Data_Pos (0) /*!< NFI_T::NANDRA50: Data Position */
#define NFI_NANDRA50_Data_Msk (0xfffffffful << NFI_NANDRA50_Data_Pos) /*!< NFI_T::NANDRA50: Data Mask */
#define NFI_NANDRA51_Data_Pos (0) /*!< NFI_T::NANDRA51: Data Position */
#define NFI_NANDRA51_Data_Msk (0xfffffffful << NFI_NANDRA51_Data_Pos) /*!< NFI_T::NANDRA51: Data Mask */
#define NFI_NANDRA52_Data_Pos (0) /*!< NFI_T::NANDRA52: Data Position */
#define NFI_NANDRA52_Data_Msk (0xfffffffful << NFI_NANDRA52_Data_Pos) /*!< NFI_T::NANDRA52: Data Mask */
#define NFI_NANDRA53_Data_Pos (0) /*!< NFI_T::NANDRA53: Data Position */
#define NFI_NANDRA53_Data_Msk (0xfffffffful << NFI_NANDRA53_Data_Pos) /*!< NFI_T::NANDRA53: Data Mask */
#define NFI_NANDRA54_Data_Pos (0) /*!< NFI_T::NANDRA54: Data Position */
#define NFI_NANDRA54_Data_Msk (0xfffffffful << NFI_NANDRA54_Data_Pos) /*!< NFI_T::NANDRA54: Data Mask */
#define NFI_NANDRA55_Data_Pos (0) /*!< NFI_T::NANDRA55: Data Position */
#define NFI_NANDRA55_Data_Msk (0xfffffffful << NFI_NANDRA55_Data_Pos) /*!< NFI_T::NANDRA55: Data Mask */
#define NFI_NANDRA56_Data_Pos (0) /*!< NFI_T::NANDRA56: Data Position */
#define NFI_NANDRA56_Data_Msk (0xfffffffful << NFI_NANDRA56_Data_Pos) /*!< NFI_T::NANDRA56: Data Mask */
#define NFI_NANDRA57_Data_Pos (0) /*!< NFI_T::NANDRA57: Data Position */
#define NFI_NANDRA57_Data_Msk (0xfffffffful << NFI_NANDRA57_Data_Pos) /*!< NFI_T::NANDRA57: Data Mask */
#define NFI_NANDRA58_Data_Pos (0) /*!< NFI_T::NANDRA58: Data Position */
#define NFI_NANDRA58_Data_Msk (0xfffffffful << NFI_NANDRA58_Data_Pos) /*!< NFI_T::NANDRA58: Data Mask */
#define NFI_NANDRA59_Data_Pos (0) /*!< NFI_T::NANDRA59: Data Position */
#define NFI_NANDRA59_Data_Msk (0xfffffffful << NFI_NANDRA59_Data_Pos) /*!< NFI_T::NANDRA59: Data Mask */
#define NFI_NANDRA60_Data_Pos (0) /*!< NFI_T::NANDRA60: Data Position */
#define NFI_NANDRA60_Data_Msk (0xfffffffful << NFI_NANDRA60_Data_Pos) /*!< NFI_T::NANDRA60: Data Mask */
#define NFI_NANDRA61_Data_Pos (0) /*!< NFI_T::NANDRA61: Data Position */
#define NFI_NANDRA61_Data_Msk (0xfffffffful << NFI_NANDRA61_Data_Pos) /*!< NFI_T::NANDRA61: Data Mask */
#define NFI_NANDRA62_Data_Pos (0) /*!< NFI_T::NANDRA62: Data Position */
#define NFI_NANDRA62_Data_Msk (0xfffffffful << NFI_NANDRA62_Data_Pos) /*!< NFI_T::NANDRA62: Data Mask */
#define NFI_NANDRA63_Data_Pos (0) /*!< NFI_T::NANDRA63: Data Position */
#define NFI_NANDRA63_Data_Msk (0xfffffffful << NFI_NANDRA63_Data_Pos) /*!< NFI_T::NANDRA63: Data Mask */
#define NFI_NANDRA64_Data_Pos (0) /*!< NFI_T::NANDRA64: Data Position */
#define NFI_NANDRA64_Data_Msk (0xfffffffful << NFI_NANDRA64_Data_Pos) /*!< NFI_T::NANDRA64: Data Mask */
#define NFI_NANDRA65_Data_Pos (0) /*!< NFI_T::NANDRA65: Data Position */
#define NFI_NANDRA65_Data_Msk (0xfffffffful << NFI_NANDRA65_Data_Pos) /*!< NFI_T::NANDRA65: Data Mask */
#define NFI_NANDRA66_Data_Pos (0) /*!< NFI_T::NANDRA66: Data Position */
#define NFI_NANDRA66_Data_Msk (0xfffffffful << NFI_NANDRA66_Data_Pos) /*!< NFI_T::NANDRA66: Data Mask */
#define NFI_NANDRA67_Data_Pos (0) /*!< NFI_T::NANDRA67: Data Position */
#define NFI_NANDRA67_Data_Msk (0xfffffffful << NFI_NANDRA67_Data_Pos) /*!< NFI_T::NANDRA67: Data Mask */
#define NFI_NANDRA68_Data_Pos (0) /*!< NFI_T::NANDRA68: Data Position */
#define NFI_NANDRA68_Data_Msk (0xfffffffful << NFI_NANDRA68_Data_Pos) /*!< NFI_T::NANDRA68: Data Mask */
#define NFI_NANDRA69_Data_Pos (0) /*!< NFI_T::NANDRA69: Data Position */
#define NFI_NANDRA69_Data_Msk (0xfffffffful << NFI_NANDRA69_Data_Pos) /*!< NFI_T::NANDRA69: Data Mask */
#define NFI_NANDRA70_Data_Pos (0) /*!< NFI_T::NANDRA70: Data Position */
#define NFI_NANDRA70_Data_Msk (0xfffffffful << NFI_NANDRA70_Data_Pos) /*!< NFI_T::NANDRA70: Data Mask */
#define NFI_NANDRA71_Data_Pos (0) /*!< NFI_T::NANDRA71: Data Position */
#define NFI_NANDRA71_Data_Msk (0xfffffffful << NFI_NANDRA71_Data_Pos) /*!< NFI_T::NANDRA71: Data Mask */
#define NFI_NANDRA72_Data_Pos (0) /*!< NFI_T::NANDRA72: Data Position */
#define NFI_NANDRA72_Data_Msk (0xfffffffful << NFI_NANDRA72_Data_Pos) /*!< NFI_T::NANDRA72: Data Mask */
#define NFI_NANDRA73_Data_Pos (0) /*!< NFI_T::NANDRA73: Data Position */
#define NFI_NANDRA73_Data_Msk (0xfffffffful << NFI_NANDRA73_Data_Pos) /*!< NFI_T::NANDRA73: Data Mask */
#define NFI_NANDRA74_Data_Pos (0) /*!< NFI_T::NANDRA74: Data Position */
#define NFI_NANDRA74_Data_Msk (0xfffffffful << NFI_NANDRA74_Data_Pos) /*!< NFI_T::NANDRA74: Data Mask */
#define NFI_NANDRA75_Data_Pos (0) /*!< NFI_T::NANDRA75: Data Position */
#define NFI_NANDRA75_Data_Msk (0xfffffffful << NFI_NANDRA75_Data_Pos) /*!< NFI_T::NANDRA75: Data Mask */
#define NFI_NANDRA76_Data_Pos (0) /*!< NFI_T::NANDRA76: Data Position */
#define NFI_NANDRA76_Data_Msk (0xfffffffful << NFI_NANDRA76_Data_Pos) /*!< NFI_T::NANDRA76: Data Mask */
#define NFI_NANDRA77_Data_Pos (0) /*!< NFI_T::NANDRA77: Data Position */
#define NFI_NANDRA77_Data_Msk (0xfffffffful << NFI_NANDRA77_Data_Pos) /*!< NFI_T::NANDRA77: Data Mask */
#define NFI_NANDRA78_Data_Pos (0) /*!< NFI_T::NANDRA78: Data Position */
#define NFI_NANDRA78_Data_Msk (0xfffffffful << NFI_NANDRA78_Data_Pos) /*!< NFI_T::NANDRA78: Data Mask */
#define NFI_NANDRA79_Data_Pos (0) /*!< NFI_T::NANDRA79: Data Position */
#define NFI_NANDRA79_Data_Msk (0xfffffffful << NFI_NANDRA79_Data_Pos) /*!< NFI_T::NANDRA79: Data Mask */
#define NFI_NANDRA80_Data_Pos (0) /*!< NFI_T::NANDRA80: Data Position */
#define NFI_NANDRA80_Data_Msk (0xfffffffful << NFI_NANDRA80_Data_Pos) /*!< NFI_T::NANDRA80: Data Mask */
#define NFI_NANDRA81_Data_Pos (0) /*!< NFI_T::NANDRA81: Data Position */
#define NFI_NANDRA81_Data_Msk (0xfffffffful << NFI_NANDRA81_Data_Pos) /*!< NFI_T::NANDRA81: Data Mask */
#define NFI_NANDRA82_Data_Pos (0) /*!< NFI_T::NANDRA82: Data Position */
#define NFI_NANDRA82_Data_Msk (0xfffffffful << NFI_NANDRA82_Data_Pos) /*!< NFI_T::NANDRA82: Data Mask */
#define NFI_NANDRA83_Data_Pos (0) /*!< NFI_T::NANDRA83: Data Position */
#define NFI_NANDRA83_Data_Msk (0xfffffffful << NFI_NANDRA83_Data_Pos) /*!< NFI_T::NANDRA83: Data Mask */
#define NFI_NANDRA84_Data_Pos (0) /*!< NFI_T::NANDRA84: Data Position */
#define NFI_NANDRA84_Data_Msk (0xfffffffful << NFI_NANDRA84_Data_Pos) /*!< NFI_T::NANDRA84: Data Mask */
#define NFI_NANDRA85_Data_Pos (0) /*!< NFI_T::NANDRA85: Data Position */
#define NFI_NANDRA85_Data_Msk (0xfffffffful << NFI_NANDRA85_Data_Pos) /*!< NFI_T::NANDRA85: Data Mask */
#define NFI_NANDRA86_Data_Pos (0) /*!< NFI_T::NANDRA86: Data Position */
#define NFI_NANDRA86_Data_Msk (0xfffffffful << NFI_NANDRA86_Data_Pos) /*!< NFI_T::NANDRA86: Data Mask */
#define NFI_NANDRA87_Data_Pos (0) /*!< NFI_T::NANDRA87: Data Position */
#define NFI_NANDRA87_Data_Msk (0xfffffffful << NFI_NANDRA87_Data_Pos) /*!< NFI_T::NANDRA87: Data Mask */
#define NFI_NANDRA88_Data_Pos (0) /*!< NFI_T::NANDRA88: Data Position */
#define NFI_NANDRA88_Data_Msk (0xfffffffful << NFI_NANDRA88_Data_Pos) /*!< NFI_T::NANDRA88: Data Mask */
#define NFI_NANDRA89_Data_Pos (0) /*!< NFI_T::NANDRA89: Data Position */
#define NFI_NANDRA89_Data_Msk (0xfffffffful << NFI_NANDRA89_Data_Pos) /*!< NFI_T::NANDRA89: Data Mask */
#define NFI_NANDRA90_Data_Pos (0) /*!< NFI_T::NANDRA90: Data Position */
#define NFI_NANDRA90_Data_Msk (0xfffffffful << NFI_NANDRA90_Data_Pos) /*!< NFI_T::NANDRA90: Data Mask */
#define NFI_NANDRA91_Data_Pos (0) /*!< NFI_T::NANDRA91: Data Position */
#define NFI_NANDRA91_Data_Msk (0xfffffffful << NFI_NANDRA91_Data_Pos) /*!< NFI_T::NANDRA91: Data Mask */
#define NFI_NANDRA92_Data_Pos (0) /*!< NFI_T::NANDRA92: Data Position */
#define NFI_NANDRA92_Data_Msk (0xfffffffful << NFI_NANDRA92_Data_Pos) /*!< NFI_T::NANDRA92: Data Mask */
#define NFI_NANDRA93_Data_Pos (0) /*!< NFI_T::NANDRA93: Data Position */
#define NFI_NANDRA93_Data_Msk (0xfffffffful << NFI_NANDRA93_Data_Pos) /*!< NFI_T::NANDRA93: Data Mask */
#define NFI_NANDRA94_Data_Pos (0) /*!< NFI_T::NANDRA94: Data Position */
#define NFI_NANDRA94_Data_Msk (0xfffffffful << NFI_NANDRA94_Data_Pos) /*!< NFI_T::NANDRA94: Data Mask */
#define NFI_NANDRA95_Data_Pos (0) /*!< NFI_T::NANDRA95: Data Position */
#define NFI_NANDRA95_Data_Msk (0xfffffffful << NFI_NANDRA95_Data_Pos) /*!< NFI_T::NANDRA95: Data Mask */
#define NFI_NANDRA96_Data_Pos (0) /*!< NFI_T::NANDRA96: Data Position */
#define NFI_NANDRA96_Data_Msk (0xfffffffful << NFI_NANDRA96_Data_Pos) /*!< NFI_T::NANDRA96: Data Mask */
#define NFI_NANDRA97_Data_Pos (0) /*!< NFI_T::NANDRA97: Data Position */
#define NFI_NANDRA97_Data_Msk (0xfffffffful << NFI_NANDRA97_Data_Pos) /*!< NFI_T::NANDRA97: Data Mask */
#define NFI_NANDRA98_Data_Pos (0) /*!< NFI_T::NANDRA98: Data Position */
#define NFI_NANDRA98_Data_Msk (0xfffffffful << NFI_NANDRA98_Data_Pos) /*!< NFI_T::NANDRA98: Data Mask */
#define NFI_NANDRA99_Data_Pos (0) /*!< NFI_T::NANDRA99: Data Position */
#define NFI_NANDRA99_Data_Msk (0xfffffffful << NFI_NANDRA99_Data_Pos) /*!< NFI_T::NANDRA99: Data Mask */
#define NFI_NANDRA100_Data_Pos (0) /*!< NFI_T::NANDRA100: Data Position */
#define NFI_NANDRA100_Data_Msk (0xfffffffful << NFI_NANDRA100_Data_Pos) /*!< NFI_T::NANDRA100: Data Mask */
#define NFI_NANDRA101_Data_Pos (0) /*!< NFI_T::NANDRA101: Data Position */
#define NFI_NANDRA101_Data_Msk (0xfffffffful << NFI_NANDRA101_Data_Pos) /*!< NFI_T::NANDRA101: Data Mask */
#define NFI_NANDRA102_Data_Pos (0) /*!< NFI_T::NANDRA102: Data Position */
#define NFI_NANDRA102_Data_Msk (0xfffffffful << NFI_NANDRA102_Data_Pos) /*!< NFI_T::NANDRA102: Data Mask */
#define NFI_NANDRA103_Data_Pos (0) /*!< NFI_T::NANDRA103: Data Position */
#define NFI_NANDRA103_Data_Msk (0xfffffffful << NFI_NANDRA103_Data_Pos) /*!< NFI_T::NANDRA103: Data Mask */
#define NFI_NANDRA104_Data_Pos (0) /*!< NFI_T::NANDRA104: Data Position */
#define NFI_NANDRA104_Data_Msk (0xfffffffful << NFI_NANDRA104_Data_Pos) /*!< NFI_T::NANDRA104: Data Mask */
#define NFI_NANDRA105_Data_Pos (0) /*!< NFI_T::NANDRA105: Data Position */
#define NFI_NANDRA105_Data_Msk (0xfffffffful << NFI_NANDRA105_Data_Pos) /*!< NFI_T::NANDRA105: Data Mask */
#define NFI_NANDRA106_Data_Pos (0) /*!< NFI_T::NANDRA106: Data Position */
#define NFI_NANDRA106_Data_Msk (0xfffffffful << NFI_NANDRA106_Data_Pos) /*!< NFI_T::NANDRA106: Data Mask */
#define NFI_NANDRA107_Data_Pos (0) /*!< NFI_T::NANDRA107: Data Position */
#define NFI_NANDRA107_Data_Msk (0xfffffffful << NFI_NANDRA107_Data_Pos) /*!< NFI_T::NANDRA107: Data Mask */
#define NFI_NANDRA108_Data_Pos (0) /*!< NFI_T::NANDRA108: Data Position */
#define NFI_NANDRA108_Data_Msk (0xfffffffful << NFI_NANDRA108_Data_Pos) /*!< NFI_T::NANDRA108: Data Mask */
#define NFI_NANDRA109_Data_Pos (0) /*!< NFI_T::NANDRA109: Data Position */
#define NFI_NANDRA109_Data_Msk (0xfffffffful << NFI_NANDRA109_Data_Pos) /*!< NFI_T::NANDRA109: Data Mask */
#define NFI_NANDRA110_Data_Pos (0) /*!< NFI_T::NANDRA110: Data Position */
#define NFI_NANDRA110_Data_Msk (0xfffffffful << NFI_NANDRA110_Data_Pos) /*!< NFI_T::NANDRA110: Data Mask */
#define NFI_NANDRA111_Data_Pos (0) /*!< NFI_T::NANDRA111: Data Position */
#define NFI_NANDRA111_Data_Msk (0xfffffffful << NFI_NANDRA111_Data_Pos) /*!< NFI_T::NANDRA111: Data Mask */
#define NFI_NANDRA112_Data_Pos (0) /*!< NFI_T::NANDRA112: Data Position */
#define NFI_NANDRA112_Data_Msk (0xfffffffful << NFI_NANDRA112_Data_Pos) /*!< NFI_T::NANDRA112: Data Mask */
#define NFI_NANDRA113_Data_Pos (0) /*!< NFI_T::NANDRA113: Data Position */
#define NFI_NANDRA113_Data_Msk (0xfffffffful << NFI_NANDRA113_Data_Pos) /*!< NFI_T::NANDRA113: Data Mask */
#define NFI_NANDRA114_Data_Pos (0) /*!< NFI_T::NANDRA114: Data Position */
#define NFI_NANDRA114_Data_Msk (0xfffffffful << NFI_NANDRA114_Data_Pos) /*!< NFI_T::NANDRA114: Data Mask */
#define NFI_NANDRA115_Data_Pos (0) /*!< NFI_T::NANDRA115: Data Position */
#define NFI_NANDRA115_Data_Msk (0xfffffffful << NFI_NANDRA115_Data_Pos) /*!< NFI_T::NANDRA115: Data Mask */
#define NFI_NANDRA116_Data_Pos (0) /*!< NFI_T::NANDRA116: Data Position */
#define NFI_NANDRA116_Data_Msk (0xfffffffful << NFI_NANDRA116_Data_Pos) /*!< NFI_T::NANDRA116: Data Mask */
#define NFI_NANDRA117_Data_Pos (0) /*!< NFI_T::NANDRA117: Data Position */
#define NFI_NANDRA117_Data_Msk (0xfffffffful << NFI_NANDRA117_Data_Pos) /*!< NFI_T::NANDRA117: Data Mask */
#define NFI_NANDRA_Data_Pos (0) /*!< NFI_T::NANDRA: Data Position */
#define NFI_NANDRA_Data_Msk (0xfffffffful << NFI_NANDRA_Data_Pos) /*!< NFI_T::NANDRA: Data Mask */
/**@}*/ /* NFI_CONST */
/**@}*/ /* end of NFI register group */

16
bsp/nuvoton/libraries/ma35/StdDriver/SConscript
View File

@ -8,6 +8,20 @@ src = Glob('*src/*.c') + Glob('src/*.cpp')
cpppath = [cwd + '/inc']
libpath = [cwd + '/lib']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
if not GetDepend('BSP_USE_STDDRIVER_SOURCE'):
if rtconfig.CROSS_TOOL == 'keil':
if GetOption('target') == 'mdk5' and os.path.isfile('./lib/libstddriver_keil.lib'):
libs += ['libstddriver_keil']
elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./lib/libstddriver_gcc_CM4.a') and GetDepend('USE_MA35D1_SUBM'):
libs += ['libstddriver_gcc_CM4']
elif rtconfig.CROSS_TOOL == 'gcc' and os.path.isfile('./lib/libstddriver_gcc_CA35.a') and GetDepend('USE_MA35D1_AARCH32'):
libs += ['libstddriver_gcc_CA35']
if not libs:
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath)
else:
src = []
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = cpppath, LIBS = libs, LIBPATH = libpath)
Return('group')

6
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_clk.h
View File

@ -363,9 +363,9 @@ extern "C"
#define PDMA1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(1UL<<0)) /*!< PDMA1 Module \hideinitializer */
#define PDMA2_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(2UL<<0)) /*!< PDMA2 Module \hideinitializer */
#define PDMA3_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(3UL<<0)) /*!< PDMA3 Module \hideinitializer */
#define WH0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< WH0 Module \hideinitializer */
#define WH1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< WH1 Module \hideinitializer */
#define HWS_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< HWS Module \hideinitializer */
#define WHC0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(4UL<<0)) /*!< WH0 Module \hideinitializer */
#define WHC1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(5UL<<0)) /*!< WH1 Module \hideinitializer */
#define HWSEM0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(6UL<<0)) /*!< HWS Module \hideinitializer */
#define EBI_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(7UL<<0)) /*!< EBI Module \hideinitializer */
#define SRAM0_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(8UL<<0)) /*!< SRAM0 Module \hideinitializer */
#define SRAM1_MODULE ((1UL<<29)|(MODULE_NoMsk<<26)|(MODULE_NoMsk<<22)|(MODULE_NoMsk<<17)|(MODULE_NoMsk<<14)|(MODULE_NoMsk<<10)|(MODULE_NoMsk<<5)|(9UL<<0)) /*!< SRAM1 Module \hideinitializer */

1
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_disp.h
View File

@ -190,6 +190,7 @@ void DISP_SetBlendValue(uint32_t u32GloAV_Src, uint32_t u32GloAV_Dst);
void DISP_SetColorKeyValue(uint32_t u32ColorKeyLow, uint32_t u32ColorKeyHigh);
int DISP_SetFBAddr(E_DISP_LAYER eLayer, uint32_t u32DMAFBStartAddr);
int DISP_SetFBFmt(E_DISP_LAYER eLayer, E_FB_FMT eFbFmt, uint32_t u32Pitch);
uint32_t DISP_LCDTIMING_GetFPS(const DISP_LCD_TIMING* psDispLCDTiming);
/*@}*/ /* end of group DISP_EXPORTED_FUNCTIONS */

43
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_hwsem.h
View File

@ -13,6 +13,11 @@ extern "C"
{
#endif
#ifdef __has_include
#if __has_include("rtconfig.h")
#include "rtconfig.h"
#endif
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
@ -26,9 +31,23 @@ extern "C"
@{
*/
#define HWSEM_CNT 8ul /*!<HWSEM count \hideinitializer */
#define HWSEM_NOLOCK 0ul /*!<Semaphore is non-lock \hideinitializer */
#define HWSEM_LOCK_BY_A35 1ul /*!<Semaphore lock by A35 \hideinitializer */
#define HWSEM_LOCK_BY_M4 2ul /*!<Semaphore lock by M4 \hideinitializer */
#if defined(USE_MA35D1_SUBM)
#define HWSEM_LOCK_BY_OWNER HWSEM_LOCK_BY_M4
#define INTSTS_CORE INTSTSM4
#define INTEN_CORE INTENM4
#else
#define HWSEM_LOCK_BY_OWNER HWSEM_LOCK_BY_A35
#define INTSTS_CORE INTSTSA35
#define INTEN_CORE INTENA35
#endif
#define HWSEM_INTSTS_SEM0IF_Pos 0
#define HWSEM_INTSTS_SEM0IF_Msk (1<<HWSEM_INTSTS_SEM0IF_Pos)
#define HWSEM_INTEN_SEM0IEN_Pos 0
#define HWSEM_INTEN_SEM0IEN_Msk (1<<HWSEM_INTEN_SEM0IEN_Pos)
/*@}*/ /* end of group HWSEM_EXPORTED_CONSTANTS */
@ -58,6 +77,17 @@ extern "C"
*/
#define HWSEM_IS_LOCKED(hwsem, u32Num) ((hwsem)->SEM[(u32Num)] & (HWSEM_SEM_ID_Msk))
/**
* @brief
*
* @param[in] hwsem The pointer of the specified HWSEM module.
* @param[in] u32Num HWSEM number, valid values are between 0~7
*
* @retval 0 The key of specified semaphore.
* \hideinitializer
*/
#define HWSEM_GET_KEY(hwsem, u32Num) (((hwsem)->SEM[(u32Num)]&HWSEM_SEM_KEY_Msk) >> HWSEM_SEM_KEY_Pos)
/**
* @brief Enable specified HWSEM interrupt
*
@ -67,7 +97,7 @@ extern "C"
*
* \hideinitializer
*/
#define HWSEM_ENABLE_INT(hwsem, u32Num) ((hwsem)->INTENM4 |= (HWSEM_INTENM4_SEM0IEN_Msk << (u32Num)))
#define HWSEM_ENABLE_INT(hwsem, u32Num) ((hwsem)->INTEN_CORE |= (HWSEM_INTEN_SEM0IEN_Msk << (u32Num)))
/**
@ -79,7 +109,7 @@ extern "C"
*
* \hideinitializer
*/
#define HWSEM_DISABLE_INT(hwsem, u32Num) ((hwsem)->INTENM4 &= ~(HWSEM_INTENM4_SEM0IEN_Msk << (u32Num)))
#define HWSEM_DISABLE_INT(hwsem, u32Num) ((hwsem)->INTEN_CORE &= ~(HWSEM_INTEN_SEM0IEN_Msk << (u32Num)))
/**
* @brief Get specified interrupt flag
@ -91,7 +121,7 @@ extern "C"
* Otherwise The specified interrupt is happened.
* \hideinitializer
*/
#define HWSEM_GET_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTSM4 & (HWSEM_INTSTSM4_SEM0IF_Msk << (u32Num)))
#define HWSEM_GET_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTS_CORE & (HWSEM_INTSTS_SEM0IF_Msk << (u32Num)))
/**
@ -102,7 +132,7 @@ extern "C"
*
* \hideinitializer
*/
#define HWSEM_CLR_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTSM4 = (HWSEM_INTSTSM4_SEM0IF_Msk << (u32Num)))
#define HWSEM_CLR_INT_FLAG(hwsem, u32Num) ((hwsem)->INTSTS_CORE = (HWSEM_INTSTS_SEM0IF_Msk << (u32Num)))
/**
@ -115,6 +145,7 @@ extern "C"
* \hideinitializer
*/
#define HWSEM_UNLOCK(hwsem, u32Num, u8Key) ((hwsem)->SEM[(u32Num)] = ((u8Key) << HWSEM_SEM_KEY_Pos) & HWSEM_SEM_KEY_Msk)
#define HWSEM_LOCK HWSEM_UNLOCK
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE int32_t HWSEM_Try_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key);
@ -133,7 +164,7 @@ __STATIC_INLINE void HWSEM_Spin_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8
__STATIC_INLINE int32_t HWSEM_Try_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8Key)
{
hwsem->SEM[u32Num] = (u8Key << HWSEM_SEM_KEY_Pos);
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_M4 &&
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_OWNER &&
(hwsem->SEM[u32Num] & HWSEM_SEM_KEY_Msk) == (u8Key << HWSEM_SEM_KEY_Pos))
return 0;
else
@ -154,7 +185,7 @@ __STATIC_INLINE void HWSEM_Spin_Lock(HWSEM_T *hwsem, uint32_t u32Num, uint8_t u8
while (1)
{
hwsem->SEM[u32Num] = (u8Key << HWSEM_SEM_KEY_Pos);
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_M4 &&
if ((hwsem->SEM[u32Num] & HWSEM_SEM_ID_Msk) == HWSEM_LOCK_BY_OWNER &&
(hwsem->SEM[u32Num] & HWSEM_SEM_KEY_Msk) == (u8Key << HWSEM_SEM_KEY_Pos))
break;
}

8
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sdh.h
View File

@ -8,6 +8,10 @@
#ifndef __NU_SDH_H__
#define __NU_SDH_H__
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
#ifdef __cplusplus
extern "C"
{
@ -116,6 +120,10 @@ void SDH_SetPower(SDH_T *sdh, uint32_t u32OnOff);
}
#endif
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
#endif

110
bsp/nuvoton/libraries/ma35/StdDriver/inc/nu_sys.h
View File

@ -36,15 +36,15 @@ extern "C"
#define PDMA2_RST ((0UL<<24) | SYS_IPRST0_PDMA2RST_Pos) /*!< Reset PDMA2 \hideinitializer */
#define PDMA3_RST ((0UL<<24) | SYS_IPRST0_PDMA3RST_Pos) /*!< Reset PDMA3 \hideinitializer */
#define DISPC_RST ((0UL<<24) | SYS_IPRST0_DISPCRST_Pos) /*!< Reset DISPC \hideinitializer */
#define CCAP0_RST ((0UL<<24) | SYS_IPRST0_CCAP0RST_Pos) /*!< Reset VCAP0 \hideinitializer */
#define CCAP1_RST ((0UL<<24) | SYS_IPRST0_CCAP1RST_Pos) /*!< Reset VCAP1 \hideinitializer */
#define CCAP0_RST ((0UL<<24) | SYS_IPRST0_CCAP0RST_Pos) /*!< Reset CCAP0 \hideinitializer */
#define CCAP1_RST ((0UL<<24) | SYS_IPRST0_CCAP1RST_Pos) /*!< Reset CCAP1 \hideinitializer */
#define GFX_RST ((0UL<<24) | SYS_IPRST0_GFXRST_Pos) /*!< Reset GFX \hideinitializer */
#define VDEC_RST ((0UL<<24) | SYS_IPRST0_VDECRST_Pos) /*!< Reset VDEC \hideinitializer */
#define WRHO0_RST ((0UL<<24) | SYS_IPRST0_WRHO0RST_Pos) /*!< Reset WRHO0 \hideinitializer */
#define WRHO1_RST ((0UL<<24) | SYS_IPRST0_WRHO1RST_Pos) /*!< Reset WRHO1 \hideinitializer */
#define WHC0_RST ((0UL<<24) | SYS_IPRST0_WRHO0RST_Pos) /*!< Reset WRHO0 \hideinitializer */
#define WHC1_RST ((0UL<<24) | SYS_IPRST0_WRHO1RST_Pos) /*!< Reset WRHO1 \hideinitializer */
#define GMAC0_RST ((0UL<<24) | SYS_IPRST0_GMAC0RST_Pos) /*!< Reset GMAC0 \hideinitializer */
#define GMAC1_RST ((0UL<<24) | SYS_IPRST0_GMAC1RST_Pos) /*!< Reset GMAC1 \hideinitializer */
#define HWSEM_RST ((0UL<<24) | SYS_IPRST0_HWSEMRST_Pos) /*!< Reset HWSEM \hideinitializer */
#define HWSEM0_RST ((0UL<<24) | SYS_IPRST0_HWSEMRST_Pos) /*!< Reset HWSEM \hideinitializer */
#define EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos) /*!< Reset EBI \hideinitializer */
#define HSUSBH0_RST ((0UL<<24) | SYS_IPRST0_HSUSBH0RST_Pos) /*!< Reset HSUSBH0 \hideinitializer */
#define HSUSBH1_RST ((0UL<<24) | SYS_IPRST0_HSUSBH1RST_Pos) /*!< Reset HSUSBH1 \hideinitializer */
@ -184,7 +184,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPA_MFPH_PA8MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPA_MFPH_PA8MFP_UART5_nCTS (0x02UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Clear to Send input pin for UART5. */
#define SYS_GPA_MFPH_PA8MFP_UART4_RXD (0x03UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< Data receiver input pin for UART4. */
#define SYS_GPA_MFPH_PA8MFP_NAND_RDY (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< NAND Flash ready/busy input pin. */
#define SYS_GPA_MFPH_PA8MFP_NAND_RDY0 (0x06UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< NAND Flash ready/busy input pin. */
#define SYS_GPA_MFPH_PA8MFP_EBI_AD8 (0x07UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< EBI address/data bus bit8. */
#define SYS_GPA_MFPH_PA8MFP_EBI_ADR8 (0x09UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPA_MFPH_PA9MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< General purpose digital I/O pin. */
@ -212,7 +212,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPA_MFPH_PA13MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPA_MFPH_PA13MFP_UART7_nRTS (0x02UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Request to Send output pin for UART7. */
#define SYS_GPA_MFPH_PA13MFP_UART8_TXD (0x03UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< Data transmitter output pin for UART8. */
#define SYS_GPA_MFPH_PA13MFP_NAND_nCS (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< NAND Flash chip select pin. */
#define SYS_GPA_MFPH_PA13MFP_NAND_nCS0 (0x06UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< NAND Flash chip select pin. */
#define SYS_GPA_MFPH_PA13MFP_EBI_AD13 (0x07UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< EBI address/data bus bit1. */
#define SYS_GPA_MFPH_PA13MFP_EBI_ADR13 (0x09UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPA_MFPH_PA14MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< General purpose digital I/O pin. */
@ -270,7 +270,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPB_MFPH_PB9MFP_I2C2_SCL (0x04UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< I2C2 clock pin. */
#define SYS_GPB_MFPH_PB9MFP_SPI0_CLK (0x05UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< SPI0 serial clock pin. */
#define SYS_GPB_MFPH_PB9MFP_I2S0_MCLK (0x06UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< I2S0 master clock output pin. */
#define SYS_GPB_MFPH_PB9MFP_VCAP1_HSYNC (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Camera capture 1 interface hsync input pin. */
#define SYS_GPB_MFPH_PB9MFP_CCAP1_HSYNC (0x07UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< Camera capture 1 interface hsync input pin. */
#define SYS_GPB_MFPH_PB9MFP_ADC0_CH1 (0x08UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< ADC0 channel 1 analog input. */
#define SYS_GPB_MFPH_PB9MFP_EBI_ALE (0x09UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< EBI address latch enable output pin. */
#define SYS_GPB_MFPH_PB9MFP_EBI_AD13 (0x0AUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< EBI address/data bus bit1. */
@ -285,7 +285,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPB_MFPH_PB10MFP_USBHL2_DM (0x04UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< USB 1.1 host-lite 2 differential signal D-. */
#define SYS_GPB_MFPH_PB10MFP_SPI0_MOSI (0x05UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. */
#define SYS_GPB_MFPH_PB10MFP_EBI_MCLK (0x06UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EBI external clock output pin. */
#define SYS_GPB_MFPH_PB10MFP_VCAP1_VSYNC (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Camera capture 1 interface vsync input pin. */
#define SYS_GPB_MFPH_PB10MFP_CCAP1_VSYNC (0x07UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< Camera capture 1 interface vsync input pin. */
#define SYS_GPB_MFPH_PB10MFP_ADC0_CH2 (0x08UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< ADC0 channel 2 analog input. */
#define SYS_GPB_MFPH_PB10MFP_EBI_ADR15 (0x09UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPB_MFPH_PB10MFP_EBI_AD14 (0x0AUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< EBI address/data bus bit1. */
@ -300,7 +300,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPB_MFPH_PB11MFP_USBHL2_DP (0x04UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< USB 1.1 host-lite 2 differential signal D+. */
#define SYS_GPB_MFPH_PB11MFP_SPI0_MISO (0x05UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< 1st SPI0 MISO (Master In, Slave Out) pin. */
#define SYS_GPB_MFPH_PB11MFP_I2S1_MCLK (0x06UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< I2S1 master clock output pin. */
#define SYS_GPB_MFPH_PB11MFP_VCAP1_SFIELD (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Camera capture 1 interface SFIELD input pin. */
#define SYS_GPB_MFPH_PB11MFP_CCAP1_SFIELD (0x07UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< Camera capture 1 interface SFIELD input pin. */
#define SYS_GPB_MFPH_PB11MFP_ADC0_CH3 (0x08UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< ADC0 channel 3 analog input. */
#define SYS_GPB_MFPH_PB11MFP_EBI_nCS2 (0x09UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EBI chip select enable output pin. */
#define SYS_GPB_MFPH_PB11MFP_EBI_ALE (0x0AUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< EBI address latch enable output pin. */
@ -567,81 +567,81 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPE_MFPL_PE0MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPL_PE0MFP_UART9_nCTS (0x02UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Clear to Send input pin for UART*. */
#define SYS_GPE_MFPL_PE0MFP_UART8_RXD (0x03UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Data receiver input pin for UART8. */
#define SYS_GPE_MFPL_PE0MFP_VCAP1_DATA0 (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Camera capture 1 data input bus bit 0. */
#define SYS_GPE_MFPL_PE0MFP_CCAP1_DATA0 (0x07UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< Camera capture 1 data input bus bit 0. */
#define SYS_GPE_MFPL_PE0MFP_RGMII0_MDC (0x08UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< RGMII0 Management Data Clock. */
#define SYS_GPE_MFPL_PE0MFP_RMII0_MDC (0x09UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< RMII0 PHY Management Clock output pin. */
#define SYS_GPE_MFPL_PE1MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPL_PE1MFP_UART9_nRTS (0x02UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Request to Send output pin for UART*. */
#define SYS_GPE_MFPL_PE1MFP_UART8_TXD (0x03UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Data transmitter output pin for UART8. */
#define SYS_GPE_MFPL_PE1MFP_VCAP1_DATA1 (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Camera capture 1 data input bus bit 1. */
#define SYS_GPE_MFPL_PE1MFP_CCAP1_DATA1 (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< Camera capture 1 data input bus bit 1. */
#define SYS_GPE_MFPL_PE1MFP_RGMII0_MDIO (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< RGMII0 PHY Management Data pin. */
#define SYS_GPE_MFPL_PE1MFP_RMII0_MDIO (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< RMII0 PHY Management Data pin. */
#define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPL_PE2MFP_UART9_RXD (0x02UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< Data receiver input pin for UART*. */
#define SYS_GPE_MFPL_PE2MFP_VCAP1_DATA2 (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< Camera capture 1 data input bus bit 2. */
#define SYS_GPE_MFPL_PE2MFP_CCAP1_DATA2 (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< Camera capture 1 data input bus bit 2. */
#define SYS_GPE_MFPL_PE2MFP_RGMII0_TXCTL (0x08UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< RGMII0 Transmit Control output pin. */
#define SYS_GPE_MFPL_PE2MFP_RMII0_TXEN (0x09UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< RMII0 Transmit Enable output pin. */
#define SYS_GPE_MFPL_PE3MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPL_PE3MFP_UART9_TXD (0x02UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< Data transmitter output pin for UART*. */
#define SYS_GPE_MFPL_PE3MFP_VCAP1_DATA3 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< Camera capture 1 data input bus bit 3. */
#define SYS_GPE_MFPL_PE3MFP_CCAP1_DATA3 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< Camera capture 1 data input bus bit 3. */
#define SYS_GPE_MFPL_PE3MFP_RGMII0_TXD0 (0x08UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< MII/RMII Transmit Data bus bit 0. */
#define SYS_GPE_MFPL_PE3MFP_RMII0_TXD0 (0x09UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< RMII0 Transmit Data bus bit 0. */
#define SYS_GPE_MFPL_PE4MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPL_PE4MFP_UART4_nCTS (0x02UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Clear to Send input pin for UART4. */
#define SYS_GPE_MFPL_PE4MFP_UART3_RXD (0x03UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Data receiver input pin for UART3. */
#define SYS_GPE_MFPL_PE4MFP_VCAP1_DATA4 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Camera capture 1 data input bus bit 4. */
#define SYS_GPE_MFPL_PE4MFP_CCAP1_DATA4 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< Camera capture 1 data input bus bit 4. */
#define SYS_GPE_MFPL_PE4MFP_RGMII0_TXD1 (0x08UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< MII/RMII Transmit Data bus bit 1. */
#define SYS_GPE_MFPL_PE4MFP_RMII0_TXD1 (0x09UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< RMII0 Transmit Data bus bit 1. */
#define SYS_GPE_MFPL_PE5MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPL_PE5MFP_UART4_nRTS (0x02UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Request to Send output pin for UART4. */
#define SYS_GPE_MFPL_PE5MFP_UART3_TXD (0x03UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Data transmitter output pin for UART3. */
#define SYS_GPE_MFPL_PE5MFP_VCAP1_DATA5 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Camera capture 1 data input bus bit 5. */
#define SYS_GPE_MFPL_PE5MFP_CCAP1_DATA5 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< Camera capture 1 data input bus bit 5. */
#define SYS_GPE_MFPL_PE5MFP_RGMII0_RXCLK (0x08UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< RGMII0 Mode RX Clock input pin. */
#define SYS_GPE_MFPL_PE5MFP_RMII0_REFCLK (0x09UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< RMII0 Reference Clock input pin. */
#define SYS_GPE_MFPL_PE6MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPL_PE6MFP_UART4_RXD (0x02UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Data receiver input pin for UART4. */
#define SYS_GPE_MFPL_PE6MFP_VCAP1_DATA6 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Camera capture 1 data input bus bit 6. */
#define SYS_GPE_MFPL_PE6MFP_CCAP1_DATA6 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< Camera capture 1 data input bus bit 6. */
#define SYS_GPE_MFPL_PE6MFP_RGMII0_RXCTL (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< RGMII0 Receive Control input pin. */
#define SYS_GPE_MFPL_PE6MFP_RMII0_CRSDV (0x09UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< RMII0 Carrier Sense/Receive Data input pin. */
#define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPL_PE7MFP_UART4_TXD (0x02UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Data transmitter output pin for UART4. */
#define SYS_GPE_MFPL_PE7MFP_VCAP1_DATA7 (0x07UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Camera capture 1 data input bus bit 7. */
#define SYS_GPE_MFPL_PE7MFP_CCAP1_DATA7 (0x07UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< Camera capture 1 data input bus bit 7. */
#define SYS_GPE_MFPL_PE7MFP_RGMII0_RXD0 (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< RGMII0 Receive Data bus bit 0. */
#define SYS_GPE_MFPL_PE7MFP_RMII0_RXD0 (0x09UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< RMII0 Receive Data bus bit 0. */
/********************* Bit definition of GPE_MFPH register **********************/
#define SYS_GPE_MFPH_PE8MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPH_PE8MFP_UART13_nCTS (0x02UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Clear to Send input pin for UART13. */
#define SYS_GPE_MFPH_PE8MFP_UART12_RXD (0x03UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Data receiver input pin for UART12. */
#define SYS_GPE_MFPH_PE8MFP_VCAP1_SCLK (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Camera capture 1 interface sensor clock output pin. */
#define SYS_GPE_MFPH_PE8MFP_CCAP1_SCLK (0x07UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< Camera capture 1 interface sensor clock output pin. */
#define SYS_GPE_MFPH_PE8MFP_RGMII0_RXD1 (0x08UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< RGMII0 Receive Data bus bit 1. */
#define SYS_GPE_MFPH_PE8MFP_RMII0_RXD1 (0x09UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< RMII0 Receive Data bus bit 1. */
#define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPH_PE9MFP_UART13_nRTS (0x02UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Request to Send output pin for UART13. */
#define SYS_GPE_MFPH_PE9MFP_UART12_TXD (0x03UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Data transmitter output pin for UART12. */
#define SYS_GPE_MFPH_PE9MFP_VCAP1_PIXCLK (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Camera capture 1 interface pixel clock input pin. */
#define SYS_GPE_MFPH_PE9MFP_CCAP1_PIXCLK (0x07UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< Camera capture 1 interface pixel clock input pin. */
#define SYS_GPE_MFPH_PE9MFP_RGMII0_RXD2 (0x08UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< RGMII0 Receive Data bus bit 2. */
#define SYS_GPE_MFPH_PE9MFP_RMII0_RXERR (0x09UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< RMII0 Receive Data Error input pin. */
#define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPH_PE10MFP_UART15_nCTS (0x02UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Clear to Send input pin for UART15. */
#define SYS_GPE_MFPH_PE10MFP_UART14_RXD (0x03UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Data receiver input pin for UART14. */
#define SYS_GPE_MFPH_PE10MFP_SPI1_SS0 (0x05UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< 1st SPI1 slave select pin. */
#define SYS_GPE_MFPH_PE10MFP_VCAP1_HSYNC (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Camera capture 1 interface hsync input pin. */
#define SYS_GPE_MFPH_PE10MFP_CCAP1_HSYNC (0x07UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< Camera capture 1 interface hsync input pin. */
#define SYS_GPE_MFPH_PE10MFP_RGMII0_RXD3 (0x08UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< RGMII0 Receive Data bus bit 3. */
#define SYS_GPE_MFPH_PE11MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPH_PE11MFP_UART15_nRTS (0x02UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Request to Send output pin for UART15. */
#define SYS_GPE_MFPH_PE11MFP_UART14_TXD (0x03UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Data transmitter output pin for UART14. */
#define SYS_GPE_MFPH_PE11MFP_SPI1_CLK (0x05UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< SPI1 serial clock pin. */
#define SYS_GPE_MFPH_PE11MFP_VCAP1_VSYNC (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Camera capture 1 interface vsync input pin. */
#define SYS_GPE_MFPH_PE11MFP_CCAP1_VSYNC (0x07UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< Camera capture 1 interface vsync input pin. */
#define SYS_GPE_MFPH_PE11MFP_RGMII0_TXCLK (0x08UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< RGMII0 Mode TX Clock output pin. */
#define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPH_PE12MFP_UART15_RXD (0x02UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Data receiver input pin for UART15. */
#define SYS_GPE_MFPH_PE12MFP_SPI1_MOSI (0x05UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< 1st SPI1 MOSI (Master Out, Slave In) pin. */
#define SYS_GPE_MFPH_PE12MFP_VCAP1_DATA8 (0x07UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Camera capture 1 data input bus bit 8. */
#define SYS_GPE_MFPH_PE12MFP_CCAP1_DATA8 (0x07UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< Camera capture 1 data input bus bit 8. */
#define SYS_GPE_MFPH_PE12MFP_RGMII0_TXD2 (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< MII/RMII Transmit Data bus bit 2. */
#define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPH_PE13MFP_UART15_TXD (0x02UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Data transmitter output pin for UART15. */
#define SYS_GPE_MFPH_PE13MFP_SPI1_MISO (0x05UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< 1st SPI1 MISO (Master In, Slave Out) pin. */
#define SYS_GPE_MFPH_PE13MFP_VCAP1_DATA9 (0x07UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Camera capture 1 data input bus bit 9. */
#define SYS_GPE_MFPH_PE13MFP_CCAP1_DATA9 (0x07UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< Camera capture 1 data input bus bit 9. */
#define SYS_GPE_MFPH_PE13MFP_RGMII0_TXD3 (0x08UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< MII/RMII Transmit Data bus bit 3. */
#define SYS_GPE_MFPH_PE14MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPE_MFPH_PE14MFP_UART0_TXD (0x01UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< Data transmitter output pin for UART0. */
@ -762,7 +762,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPF_MFPH_PF14MFP_RMII1_PPS (0x04UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< RMII1 Pulse Per Second output pin. */
#define SYS_GPF_MFPH_PF14MFP_SPI0_I2SMCLK (0x05UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< SPI0 I2S master clock output pin. */
#define SYS_GPF_MFPH_PF14MFP_SPI1_I2SMCLK (0x06UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< SPI1 I2S master clock output pin. */
#define SYS_GPF_MFPH_PF14MFP_VCAP1_SFIELD (0x07UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< Camera capture 1 interface SFIELD input pin. */
#define SYS_GPF_MFPH_PF14MFP_CCAP1_SFIELD (0x07UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< Camera capture 1 interface SFIELD input pin. */
#define SYS_GPF_MFPH_PF14MFP_RGMII0_PPS (0x08UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< RGMII0 Pulse Per Second output pin. */
#define SYS_GPF_MFPH_PF14MFP_RMII0_PPS (0x09UL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< RMII0 Pulse Per Second output pin. */
#define SYS_GPF_MFPH_PF14MFP_TM0 (0x0BUL<<SYS_GPF_MFPH_PF14MFP_Pos) /*!< Timer0 event counter input / toggle output */
@ -1316,19 +1316,19 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPK_MFPH_PK8MFP_QEI1_INDEX (0x0CUL<<SYS_GPK_MFPH_PK8MFP_Pos) /*!< Quadrature encoder index input of QEI Unit 1. */
#define SYS_GPK_MFPH_PK9MFP_GPIO (0x00UL<<SYS_GPK_MFPH_PK9MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPK_MFPH_PK9MFP_I2C3_SCL (0x04UL<<SYS_GPK_MFPH_PK9MFP_Pos) /*!< I2C3 clock pin. */
#define SYS_GPK_MFPH_PK9MFP_VCAP0_SCLK (0x06UL<<SYS_GPK_MFPH_PK9MFP_Pos) /*!< Camera capture 0 interface sensor clock output pin. */
#define SYS_GPK_MFPH_PK9MFP_CCAP0_SCLK (0x06UL<<SYS_GPK_MFPH_PK9MFP_Pos) /*!< Camera capture 0 interface sensor clock output pin. */
#define SYS_GPK_MFPH_PK9MFP_EBI_AD0 (0x08UL<<SYS_GPK_MFPH_PK9MFP_Pos) /*!< EBI address/data bus bit0. */
#define SYS_GPK_MFPH_PK9MFP_EBI_ADR0 (0x0AUL<<SYS_GPK_MFPH_PK9MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPK_MFPH_PK10MFP_GPIO (0x00UL<<SYS_GPK_MFPH_PK10MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPK_MFPH_PK10MFP_CAN1_RXD (0x03UL<<SYS_GPK_MFPH_PK10MFP_Pos) /*!< CAN1 bus receiver input. */
#define SYS_GPK_MFPH_PK10MFP_USBHL3_DM (0x04UL<<SYS_GPK_MFPH_PK10MFP_Pos) /*!< USB 1.1 host-lite 3 differential signal D-. */
#define SYS_GPK_MFPH_PK10MFP_VCAP0_PIXCLK (0x06UL<<SYS_GPK_MFPH_PK10MFP_Pos) /*!< Camera capture 0 interface pixel clock input pin. */
#define SYS_GPK_MFPH_PK10MFP_CCAP0_PIXCLK (0x06UL<<SYS_GPK_MFPH_PK10MFP_Pos) /*!< Camera capture 0 interface pixel clock input pin. */
#define SYS_GPK_MFPH_PK10MFP_EBI_AD1 (0x08UL<<SYS_GPK_MFPH_PK10MFP_Pos) /*!< EBI address/data bus bit1. */
#define SYS_GPK_MFPH_PK10MFP_EBI_ADR1 (0x0AUL<<SYS_GPK_MFPH_PK10MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPK_MFPH_PK11MFP_GPIO (0x00UL<<SYS_GPK_MFPH_PK11MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPK_MFPH_PK11MFP_CAN1_TXD (0x03UL<<SYS_GPK_MFPH_PK11MFP_Pos) /*!< CAN1 bus transmitter output. */
#define SYS_GPK_MFPH_PK11MFP_USBHL3_DP (0x04UL<<SYS_GPK_MFPH_PK11MFP_Pos) /*!< USB 1.1 host-lite 3 differential signal D+. */
#define SYS_GPK_MFPH_PK11MFP_VCAP0_HSYNC (0x06UL<<SYS_GPK_MFPH_PK11MFP_Pos) /*!< Camera capture 0 interface hsync input pin. */
#define SYS_GPK_MFPH_PK11MFP_CCAP0_HSYNC (0x06UL<<SYS_GPK_MFPH_PK11MFP_Pos) /*!< Camera capture 0 interface hsync input pin. */
#define SYS_GPK_MFPH_PK11MFP_EBI_AD2 (0x08UL<<SYS_GPK_MFPH_PK11MFP_Pos) /*!< EBI address/data bus bit2. */
#define SYS_GPK_MFPH_PK11MFP_EBI_ADR2 (0x0AUL<<SYS_GPK_MFPH_PK11MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPK_MFPH_PK12MFP_GPIO (0x00UL<<SYS_GPK_MFPH_PK12MFP_Pos) /*!< General purpose digital I/O pin. */
@ -1574,58 +1574,58 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
/********************* Bit definition of GPM_MFPL register **********************/
#define SYS_GPM_MFPL_PM0MFP_GPIO (0x00UL<<SYS_GPM_MFPL_PM0MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPL_PM0MFP_I2C4_SDA (0x04UL<<SYS_GPM_MFPL_PM0MFP_Pos) /*!< I2C4 data input/output pin. */
#define SYS_GPM_MFPL_PM0MFP_VCAP0_VSYNC (0x06UL<<SYS_GPM_MFPL_PM0MFP_Pos) /*!< Camera capture 0 interface vsync input pin. */
#define SYS_GPM_MFPL_PM0MFP_CCAP0_VSYNC (0x06UL<<SYS_GPM_MFPL_PM0MFP_Pos) /*!< Camera capture 0 interface vsync input pin. */
#define SYS_GPM_MFPL_PM0MFP_EBI_AD3 (0x08UL<<SYS_GPM_MFPL_PM0MFP_Pos) /*!< EBI address/data bus bit3. */
#define SYS_GPM_MFPL_PM0MFP_EBI_ADR3 (0x0AUL<<SYS_GPM_MFPL_PM0MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPL_PM1MFP_GPIO (0x00UL<<SYS_GPM_MFPL_PM1MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPL_PM1MFP_I2C4_SCL (0x04UL<<SYS_GPM_MFPL_PM1MFP_Pos) /*!< I2C4 clock pin. */
#define SYS_GPM_MFPL_PM1MFP_SPI3_I2SMCLK (0x05UL<<SYS_GPM_MFPL_PM1MFP_Pos) /*!< SPI3 I2S master clock output pin. */
#define SYS_GPM_MFPL_PM1MFP_VCAP0_SFIELD (0x06UL<<SYS_GPM_MFPL_PM1MFP_Pos) /*!< Camera capture 0 interface SFIELD input pin. */
#define SYS_GPM_MFPL_PM1MFP_CCAP0_SFIELD (0x06UL<<SYS_GPM_MFPL_PM1MFP_Pos) /*!< Camera capture 0 interface SFIELD input pin. */
#define SYS_GPM_MFPL_PM1MFP_EBI_AD4 (0x08UL<<SYS_GPM_MFPL_PM1MFP_Pos) /*!< EBI address/data bus bit4. */
#define SYS_GPM_MFPL_PM1MFP_EBI_ADR4 (0x0AUL<<SYS_GPM_MFPL_PM1MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPL_PM2MFP_GPIO (0x00UL<<SYS_GPM_MFPL_PM2MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPL_PM2MFP_CAN3_RXD (0x03UL<<SYS_GPM_MFPL_PM2MFP_Pos) /*!< CAN3 bus receiver input. */
#define SYS_GPM_MFPL_PM2MFP_USBHL0_DM (0x04UL<<SYS_GPM_MFPL_PM2MFP_Pos) /*!< USB 1.1 host-lite 0 differential signal D-. */
#define SYS_GPM_MFPL_PM2MFP_VCAP0_DATA0 (0x06UL<<SYS_GPM_MFPL_PM2MFP_Pos) /*!< Camera capture 0 data input bus bit 0. */
#define SYS_GPM_MFPL_PM2MFP_CCAP0_DATA0 (0x06UL<<SYS_GPM_MFPL_PM2MFP_Pos) /*!< Camera capture 0 data input bus bit 0. */
#define SYS_GPM_MFPL_PM2MFP_EBI_AD5 (0x08UL<<SYS_GPM_MFPL_PM2MFP_Pos) /*!< EBI address/data bus bit5. */
#define SYS_GPM_MFPL_PM2MFP_EBI_ADR5 (0x0AUL<<SYS_GPM_MFPL_PM2MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPL_PM3MFP_GPIO (0x00UL<<SYS_GPM_MFPL_PM3MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPL_PM3MFP_CAN3_TXD (0x03UL<<SYS_GPM_MFPL_PM3MFP_Pos) /*!< CAN3 bus transmitter output. */
#define SYS_GPM_MFPL_PM3MFP_USBHL0_DP (0x04UL<<SYS_GPM_MFPL_PM3MFP_Pos) /*!< USB 1.1 host-lite 0 differential signal D+. */
#define SYS_GPM_MFPL_PM3MFP_VCAP0_DATA1 (0x06UL<<SYS_GPM_MFPL_PM3MFP_Pos) /*!< Camera capture 0 data input bus bit 1. */
#define SYS_GPM_MFPL_PM3MFP_CCAP0_DATA1 (0x06UL<<SYS_GPM_MFPL_PM3MFP_Pos) /*!< Camera capture 0 data input bus bit 1. */
#define SYS_GPM_MFPL_PM3MFP_EBI_AD6 (0x08UL<<SYS_GPM_MFPL_PM3MFP_Pos) /*!< EBI address/data bus bit6. */
#define SYS_GPM_MFPL_PM3MFP_EBI_ADR6 (0x0AUL<<SYS_GPM_MFPL_PM3MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPL_PM4MFP_GPIO (0x00UL<<SYS_GPM_MFPL_PM4MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPL_PM4MFP_I2C5_SDA (0x04UL<<SYS_GPM_MFPL_PM4MFP_Pos) /*!< I2C5 data input/output pin. */
#define SYS_GPM_MFPL_PM4MFP_VCAP0_DATA2 (0x06UL<<SYS_GPM_MFPL_PM4MFP_Pos) /*!< Camera capture 0 data input bus bit 2. */
#define SYS_GPM_MFPL_PM4MFP_CCAP0_DATA2 (0x06UL<<SYS_GPM_MFPL_PM4MFP_Pos) /*!< Camera capture 0 data input bus bit 2. */
#define SYS_GPM_MFPL_PM4MFP_EBI_AD7 (0x08UL<<SYS_GPM_MFPL_PM4MFP_Pos) /*!< EBI address/data bus bit7. */
#define SYS_GPM_MFPL_PM4MFP_EBI_ADR7 (0x0AUL<<SYS_GPM_MFPL_PM4MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPL_PM5MFP_GPIO (0x00UL<<SYS_GPM_MFPL_PM5MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPL_PM5MFP_I2C5_SCL (0x04UL<<SYS_GPM_MFPL_PM5MFP_Pos) /*!< I2C5 clock pin. */
#define SYS_GPM_MFPL_PM5MFP_VCAP0_DATA3 (0x06UL<<SYS_GPM_MFPL_PM5MFP_Pos) /*!< Camera capture 0 data input bus bit 3. */
#define SYS_GPM_MFPL_PM5MFP_CCAP0_DATA3 (0x06UL<<SYS_GPM_MFPL_PM5MFP_Pos) /*!< Camera capture 0 data input bus bit 3. */
#define SYS_GPM_MFPL_PM5MFP_EBI_AD8 (0x08UL<<SYS_GPM_MFPL_PM5MFP_Pos) /*!< EBI address/data bus bit8. */
#define SYS_GPM_MFPL_PM5MFP_EBI_ADR8 (0x0AUL<<SYS_GPM_MFPL_PM5MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPL_PM6MFP_GPIO (0x00UL<<SYS_GPM_MFPL_PM6MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPL_PM6MFP_CAN0_RXD (0x03UL<<SYS_GPM_MFPL_PM6MFP_Pos) /*!< CAN0 bus receiver input. */
#define SYS_GPM_MFPL_PM6MFP_USBHL1_DM (0x04UL<<SYS_GPM_MFPL_PM6MFP_Pos) /*!< USB 1.1 host-lite 1 differential signal D-. */
#define SYS_GPM_MFPL_PM6MFP_VCAP0_DATA4 (0x06UL<<SYS_GPM_MFPL_PM6MFP_Pos) /*!< Camera capture 0 data input bus bit 4. */
#define SYS_GPM_MFPL_PM6MFP_CCAP0_DATA4 (0x06UL<<SYS_GPM_MFPL_PM6MFP_Pos) /*!< Camera capture 0 data input bus bit 4. */
#define SYS_GPM_MFPL_PM6MFP_EBI_AD9 (0x08UL<<SYS_GPM_MFPL_PM6MFP_Pos) /*!< EBI address/data bus bit9. */
#define SYS_GPM_MFPL_PM6MFP_EBI_ADR9 (0x0AUL<<SYS_GPM_MFPL_PM6MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPL_PM7MFP_GPIO (0x00UL<<SYS_GPM_MFPL_PM7MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPL_PM7MFP_CAN0_TXD (0x03UL<<SYS_GPM_MFPL_PM7MFP_Pos) /*!< CAN0 bus transmitter output. */
#define SYS_GPM_MFPL_PM7MFP_USBHL1_DP (0x04UL<<SYS_GPM_MFPL_PM7MFP_Pos) /*!< USB 1.1 host-lite 1 differential signal D+. */
#define SYS_GPM_MFPL_PM7MFP_VCAP0_DATA5 (0x06UL<<SYS_GPM_MFPL_PM7MFP_Pos) /*!< Camera capture 0 data input bus bit 5. */
#define SYS_GPM_MFPL_PM7MFP_CCAP0_DATA5 (0x06UL<<SYS_GPM_MFPL_PM7MFP_Pos) /*!< Camera capture 0 data input bus bit 5. */
#define SYS_GPM_MFPL_PM7MFP_EBI_AD10 (0x08UL<<SYS_GPM_MFPL_PM7MFP_Pos) /*!< EBI address/data bus bit1. */
#define SYS_GPM_MFPL_PM7MFP_EBI_ADR10 (0x0AUL<<SYS_GPM_MFPL_PM7MFP_Pos) /*!< EBI address/data bus bit*. */
/********************* Bit definition of GPM_MFPH register **********************/
#define SYS_GPM_MFPH_PM8MFP_GPIO (0x00UL<<SYS_GPM_MFPH_PM8MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPH_PM8MFP_I2C0_SDA (0x04UL<<SYS_GPM_MFPH_PM8MFP_Pos) /*!< I2C0 data input/output pin. */
#define SYS_GPM_MFPH_PM8MFP_VCAP0_DATA6 (0x06UL<<SYS_GPM_MFPH_PM8MFP_Pos) /*!< Camera capture 0 data input bus bit 6. */
#define SYS_GPM_MFPH_PM8MFP_CCAP0_DATA6 (0x06UL<<SYS_GPM_MFPH_PM8MFP_Pos) /*!< Camera capture 0 data input bus bit 6. */
#define SYS_GPM_MFPH_PM8MFP_EBI_AD11 (0x08UL<<SYS_GPM_MFPH_PM8MFP_Pos) /*!< EBI address/data bus bit1. */
#define SYS_GPM_MFPH_PM8MFP_EBI_ADR11 (0x0AUL<<SYS_GPM_MFPH_PM8MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPH_PM9MFP_GPIO (0x00UL<<SYS_GPM_MFPH_PM9MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPM_MFPH_PM9MFP_I2C0_SCL (0x04UL<<SYS_GPM_MFPH_PM9MFP_Pos) /*!< I2C0 clock pin. */
#define SYS_GPM_MFPH_PM9MFP_VCAP0_DATA7 (0x06UL<<SYS_GPM_MFPH_PM9MFP_Pos) /*!< Camera capture 0 data input bus bit 7. */
#define SYS_GPM_MFPH_PM9MFP_CCAP0_DATA7 (0x06UL<<SYS_GPM_MFPH_PM9MFP_Pos) /*!< Camera capture 0 data input bus bit 7. */
#define SYS_GPM_MFPH_PM9MFP_EBI_AD12 (0x08UL<<SYS_GPM_MFPH_PM9MFP_Pos) /*!< EBI address/data bus bit1. */
#define SYS_GPM_MFPH_PM9MFP_EBI_ADR12 (0x0AUL<<SYS_GPM_MFPH_PM9MFP_Pos) /*!< EBI address/data bus bit*. */
#define SYS_GPM_MFPH_PM10MFP_GPIO (0x00UL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< General purpose digital I/O pin. */
@ -1633,7 +1633,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPM_MFPH_PM10MFP_CAN2_RXD (0x03UL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< CAN2 bus receiver input. */
#define SYS_GPM_MFPH_PM10MFP_USBHL4_DM (0x04UL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< USB 1.1 host-lite 4 differential signal D-. */
#define SYS_GPM_MFPH_PM10MFP_SPI3_SS0 (0x05UL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< 1st SPI3 slave select pin. */
#define SYS_GPM_MFPH_PM10MFP_VCAP0_DATA8 (0x06UL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< Camera capture 0 data input bus bit 8. */
#define SYS_GPM_MFPH_PM10MFP_CCAP0_DATA8 (0x06UL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< Camera capture 0 data input bus bit 8. */
#define SYS_GPM_MFPH_PM10MFP_SPI2_I2SMCLK (0x07UL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< SPI2 I2S master clock output pin. */
#define SYS_GPM_MFPH_PM10MFP_EBI_AD13 (0x08UL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< EBI address/data bus bit1. */
#define SYS_GPM_MFPH_PM10MFP_EBI_ADR13 (0x0AUL<<SYS_GPM_MFPH_PM10MFP_Pos) /*!< EBI address/data bus bit*. */
@ -1642,7 +1642,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPM_MFPH_PM11MFP_CAN2_TXD (0x03UL<<SYS_GPM_MFPH_PM11MFP_Pos) /*!< CAN2 bus transmitter output. */
#define SYS_GPM_MFPH_PM11MFP_USBHL4_DP (0x04UL<<SYS_GPM_MFPH_PM11MFP_Pos) /*!< USB 1.1 host-lite 4 differential signal D+. */
#define SYS_GPM_MFPH_PM11MFP_SPI3_SS1 (0x05UL<<SYS_GPM_MFPH_PM11MFP_Pos) /*!< 1st SPI3 slave select pin. */
#define SYS_GPM_MFPH_PM11MFP_VCAP0_DATA9 (0x06UL<<SYS_GPM_MFPH_PM11MFP_Pos) /*!< Camera capture 0 data input bus bit 9. */
#define SYS_GPM_MFPH_PM11MFP_CCAP0_DATA9 (0x06UL<<SYS_GPM_MFPH_PM11MFP_Pos) /*!< Camera capture 0 data input bus bit 9. */
#define SYS_GPM_MFPH_PM11MFP_SPI2_SS1 (0x07UL<<SYS_GPM_MFPH_PM11MFP_Pos) /*!< 1st SPI2 slave select pin. */
#define SYS_GPM_MFPH_PM11MFP_EBI_AD14 (0x08UL<<SYS_GPM_MFPH_PM11MFP_Pos) /*!< EBI address/data bus bit1. */
#define SYS_GPM_MFPH_PM11MFP_EBI_ADR14 (0x0AUL<<SYS_GPM_MFPH_PM11MFP_Pos) /*!< EBI address/data bus bit*. */
@ -1690,67 +1690,67 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
/********************* Bit definition of GPN_MFPL register **********************/
#define SYS_GPN_MFPL_PN0MFP_GPIO (0x00UL<<SYS_GPN_MFPL_PN0MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPL_PN0MFP_I2C2_SDA (0x04UL<<SYS_GPN_MFPL_PN0MFP_Pos) /*!< I2C2 data input/output pin. */
#define SYS_GPN_MFPL_PN0MFP_VCAP1_DATA0 (0x06UL<<SYS_GPN_MFPL_PN0MFP_Pos) /*!< Camera capture 1 data input bus bit 0. */
#define SYS_GPN_MFPL_PN0MFP_CCAP1_DATA0 (0x06UL<<SYS_GPN_MFPL_PN0MFP_Pos) /*!< Camera capture 1 data input bus bit 0. */
#define SYS_GPN_MFPL_PN1MFP_GPIO (0x00UL<<SYS_GPN_MFPL_PN1MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPL_PN1MFP_I2C2_SCL (0x04UL<<SYS_GPN_MFPL_PN1MFP_Pos) /*!< I2C2 clock pin. */
#define SYS_GPN_MFPL_PN1MFP_VCAP1_DATA1 (0x06UL<<SYS_GPN_MFPL_PN1MFP_Pos) /*!< Camera capture 1 data input bus bit 1. */
#define SYS_GPN_MFPL_PN1MFP_CCAP1_DATA1 (0x06UL<<SYS_GPN_MFPL_PN1MFP_Pos) /*!< Camera capture 1 data input bus bit 1. */
#define SYS_GPN_MFPL_PN2MFP_GPIO (0x00UL<<SYS_GPN_MFPL_PN2MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPL_PN2MFP_CAN0_RXD (0x03UL<<SYS_GPN_MFPL_PN2MFP_Pos) /*!< CAN0 bus receiver input. */
#define SYS_GPN_MFPL_PN2MFP_USBHL0_DM (0x04UL<<SYS_GPN_MFPL_PN2MFP_Pos) /*!< USB 1.1 host-lite 0 differential signal D-. */
#define SYS_GPN_MFPL_PN2MFP_VCAP1_DATA2 (0x06UL<<SYS_GPN_MFPL_PN2MFP_Pos) /*!< Camera capture 1 data input bus bit 2. */
#define SYS_GPN_MFPL_PN2MFP_CCAP1_DATA2 (0x06UL<<SYS_GPN_MFPL_PN2MFP_Pos) /*!< Camera capture 1 data input bus bit 2. */
#define SYS_GPN_MFPL_PN3MFP_GPIO (0x00UL<<SYS_GPN_MFPL_PN3MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPL_PN3MFP_CAN0_TXD (0x03UL<<SYS_GPN_MFPL_PN3MFP_Pos) /*!< CAN0 bus transmitter output. */
#define SYS_GPN_MFPL_PN3MFP_USBHL0_DP (0x04UL<<SYS_GPN_MFPL_PN3MFP_Pos) /*!< USB 1.1 host-lite 0 differential signal D+. */
#define SYS_GPN_MFPL_PN3MFP_VCAP1_DATA3 (0x06UL<<SYS_GPN_MFPL_PN3MFP_Pos) /*!< Camera capture 1 data input bus bit 3. */
#define SYS_GPN_MFPL_PN3MFP_CCAP1_DATA3 (0x06UL<<SYS_GPN_MFPL_PN3MFP_Pos) /*!< Camera capture 1 data input bus bit 3. */
#define SYS_GPN_MFPL_PN4MFP_GPIO (0x00UL<<SYS_GPN_MFPL_PN4MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPL_PN4MFP_I2C1_SDA (0x04UL<<SYS_GPN_MFPL_PN4MFP_Pos) /*!< I2C1 data input/output pin. */
#define SYS_GPN_MFPL_PN4MFP_VCAP1_DATA4 (0x06UL<<SYS_GPN_MFPL_PN4MFP_Pos) /*!< Camera capture 1 data input bus bit 4. */
#define SYS_GPN_MFPL_PN4MFP_CCAP1_DATA4 (0x06UL<<SYS_GPN_MFPL_PN4MFP_Pos) /*!< Camera capture 1 data input bus bit 4. */
#define SYS_GPN_MFPL_PN5MFP_GPIO (0x00UL<<SYS_GPN_MFPL_PN5MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPL_PN5MFP_I2C1_SCL (0x04UL<<SYS_GPN_MFPL_PN5MFP_Pos) /*!< I2C1 clock pin. */
#define SYS_GPN_MFPL_PN5MFP_VCAP1_DATA5 (0x06UL<<SYS_GPN_MFPL_PN5MFP_Pos) /*!< Camera capture 1 data input bus bit 5. */
#define SYS_GPN_MFPL_PN5MFP_CCAP1_DATA5 (0x06UL<<SYS_GPN_MFPL_PN5MFP_Pos) /*!< Camera capture 1 data input bus bit 5. */
#define SYS_GPN_MFPL_PN6MFP_GPIO (0x00UL<<SYS_GPN_MFPL_PN6MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPL_PN6MFP_CAN1_RXD (0x03UL<<SYS_GPN_MFPL_PN6MFP_Pos) /*!< CAN1 bus receiver input. */
#define SYS_GPN_MFPL_PN6MFP_USBHL1_DM (0x04UL<<SYS_GPN_MFPL_PN6MFP_Pos) /*!< USB 1.1 host-lite 1 differential signal D-. */
#define SYS_GPN_MFPL_PN6MFP_VCAP1_DATA6 (0x06UL<<SYS_GPN_MFPL_PN6MFP_Pos) /*!< Camera capture 1 data input bus bit 6. */
#define SYS_GPN_MFPL_PN6MFP_CCAP1_DATA6 (0x06UL<<SYS_GPN_MFPL_PN6MFP_Pos) /*!< Camera capture 1 data input bus bit 6. */
#define SYS_GPN_MFPL_PN7MFP_GPIO (0x00UL<<SYS_GPN_MFPL_PN7MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPL_PN7MFP_CAN1_TXD (0x03UL<<SYS_GPN_MFPL_PN7MFP_Pos) /*!< CAN1 bus transmitter output. */
#define SYS_GPN_MFPL_PN7MFP_USBHL1_DP (0x04UL<<SYS_GPN_MFPL_PN7MFP_Pos) /*!< USB 1.1 host-lite 1 differential signal D+. */
#define SYS_GPN_MFPL_PN7MFP_VCAP1_DATA7 (0x06UL<<SYS_GPN_MFPL_PN7MFP_Pos) /*!< Camera capture 1 data input bus bit 7. */
#define SYS_GPN_MFPL_PN7MFP_CCAP1_DATA7 (0x06UL<<SYS_GPN_MFPL_PN7MFP_Pos) /*!< Camera capture 1 data input bus bit 7. */
/********************* Bit definition of GPN_MFPH register **********************/
#define SYS_GPN_MFPH_PN8MFP_GPIO (0x00UL<<SYS_GPN_MFPH_PN8MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPH_PN8MFP_EPWM2_CH4 (0x01UL<<SYS_GPN_MFPH_PN8MFP_Pos) /*!< EPWM2 channel4 output/capture input. */
#define SYS_GPN_MFPH_PN8MFP_I2C0_SDA (0x04UL<<SYS_GPN_MFPH_PN8MFP_Pos) /*!< I2C0 data input/output pin. */
#define SYS_GPN_MFPH_PN8MFP_SPI2_I2SMCLK (0x05UL<<SYS_GPN_MFPH_PN8MFP_Pos) /*!< SPI2 I2S master clock output pin. */
#define SYS_GPN_MFPH_PN8MFP_VCAP1_DATA8 (0x06UL<<SYS_GPN_MFPH_PN8MFP_Pos) /*!< Camera capture 1 data input bus bit 8. */
#define SYS_GPN_MFPH_PN8MFP_CCAP1_DATA8 (0x06UL<<SYS_GPN_MFPH_PN8MFP_Pos) /*!< Camera capture 1 data input bus bit 8. */
#define SYS_GPN_MFPH_PN9MFP_GPIO (0x00UL<<SYS_GPN_MFPH_PN9MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPH_PN9MFP_EPWM2_CH5 (0x01UL<<SYS_GPN_MFPH_PN9MFP_Pos) /*!< EPWM2 channel5 output/capture input. */
#define SYS_GPN_MFPH_PN9MFP_I2C0_SCL (0x04UL<<SYS_GPN_MFPH_PN9MFP_Pos) /*!< I2C0 clock pin. */
#define SYS_GPN_MFPH_PN9MFP_SPI1_I2SMCLK (0x05UL<<SYS_GPN_MFPH_PN9MFP_Pos) /*!< SPI1 I2S master clock output pin. */
#define SYS_GPN_MFPH_PN9MFP_VCAP1_DATA9 (0x06UL<<SYS_GPN_MFPH_PN9MFP_Pos) /*!< Camera capture 1 data input bus bit 9. */
#define SYS_GPN_MFPH_PN9MFP_CCAP1_DATA9 (0x06UL<<SYS_GPN_MFPH_PN9MFP_Pos) /*!< Camera capture 1 data input bus bit 9. */
#define SYS_GPN_MFPH_PN10MFP_GPIO (0x00UL<<SYS_GPN_MFPH_PN10MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPH_PN10MFP_CAN2_RXD (0x03UL<<SYS_GPN_MFPH_PN10MFP_Pos) /*!< CAN2 bus receiver input. */
#define SYS_GPN_MFPH_PN10MFP_USBHL2_DM (0x04UL<<SYS_GPN_MFPH_PN10MFP_Pos) /*!< USB 1.1 host-lite 2 differential signal D-. */
#define SYS_GPN_MFPH_PN10MFP_VCAP1_SCLK (0x06UL<<SYS_GPN_MFPH_PN10MFP_Pos) /*!< Camera capture 1 interface sensor clock output pin. */
#define SYS_GPN_MFPH_PN10MFP_CCAP1_SCLK (0x06UL<<SYS_GPN_MFPH_PN10MFP_Pos) /*!< Camera capture 1 interface sensor clock output pin. */
#define SYS_GPN_MFPH_PN11MFP_GPIO (0x00UL<<SYS_GPN_MFPH_PN11MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPH_PN11MFP_CAN2_TXD (0x03UL<<SYS_GPN_MFPH_PN11MFP_Pos) /*!< CAN2 bus transmitter output. */
#define SYS_GPN_MFPH_PN11MFP_USBHL2_DP (0x04UL<<SYS_GPN_MFPH_PN11MFP_Pos) /*!< USB 1.1 host-lite 2 differential signal D+. */
#define SYS_GPN_MFPH_PN11MFP_VCAP1_PIXCLK (0x06UL<<SYS_GPN_MFPH_PN11MFP_Pos) /*!< Camera capture 1 interface pixel clock input pin. */
#define SYS_GPN_MFPH_PN11MFP_CCAP1_PIXCLK (0x06UL<<SYS_GPN_MFPH_PN11MFP_Pos) /*!< Camera capture 1 interface pixel clock input pin. */
#define SYS_GPN_MFPH_PN12MFP_GPIO (0x00UL<<SYS_GPN_MFPH_PN12MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPH_PN12MFP_UART6_nCTS (0x02UL<<SYS_GPN_MFPH_PN12MFP_Pos) /*!< Clear to Send input pin for UART6. */
#define SYS_GPN_MFPH_PN12MFP_UART12_RXD (0x03UL<<SYS_GPN_MFPH_PN12MFP_Pos) /*!< Data receiver input pin for UART12. */
#define SYS_GPN_MFPH_PN12MFP_I2C5_SDA (0x04UL<<SYS_GPN_MFPH_PN12MFP_Pos) /*!< I2C5 data input/output pin. */
#define SYS_GPN_MFPH_PN12MFP_VCAP1_HSYNC (0x06UL<<SYS_GPN_MFPH_PN12MFP_Pos) /*!< Camera capture 1 interface hsync input pin. */
#define SYS_GPN_MFPH_PN12MFP_CCAP1_HSYNC (0x06UL<<SYS_GPN_MFPH_PN12MFP_Pos) /*!< Camera capture 1 interface hsync input pin. */
#define SYS_GPN_MFPH_PN13MFP_GPIO (0x00UL<<SYS_GPN_MFPH_PN13MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPH_PN13MFP_UART6_nRTS (0x02UL<<SYS_GPN_MFPH_PN13MFP_Pos) /*!< Request to Send output pin for UART6. */
#define SYS_GPN_MFPH_PN13MFP_UART12_TXD (0x03UL<<SYS_GPN_MFPH_PN13MFP_Pos) /*!< Data transmitter output pin for UART12. */
#define SYS_GPN_MFPH_PN13MFP_I2C5_SCL (0x04UL<<SYS_GPN_MFPH_PN13MFP_Pos) /*!< I2C5 clock pin. */
#define SYS_GPN_MFPH_PN13MFP_VCAP1_VSYNC (0x06UL<<SYS_GPN_MFPH_PN13MFP_Pos) /*!< Camera capture 1 interface vsync input pin. */
#define SYS_GPN_MFPH_PN13MFP_CCAP1_VSYNC (0x06UL<<SYS_GPN_MFPH_PN13MFP_Pos) /*!< Camera capture 1 interface vsync input pin. */
#define SYS_GPN_MFPH_PN14MFP_GPIO (0x00UL<<SYS_GPN_MFPH_PN14MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPH_PN14MFP_UART6_RXD (0x02UL<<SYS_GPN_MFPH_PN14MFP_Pos) /*!< Data receiver input pin for UART6. */
#define SYS_GPN_MFPH_PN14MFP_CAN3_RXD (0x03UL<<SYS_GPN_MFPH_PN14MFP_Pos) /*!< CAN3 bus receiver input. */
#define SYS_GPN_MFPH_PN14MFP_USBHL3_DM (0x04UL<<SYS_GPN_MFPH_PN14MFP_Pos) /*!< USB 1.1 host-lite 3 differential signal D-. */
#define SYS_GPN_MFPH_PN14MFP_SPI1_SS1 (0x05UL<<SYS_GPN_MFPH_PN14MFP_Pos) /*!< 1st SPI1 slave select pin. */
#define SYS_GPN_MFPH_PN14MFP_VCAP1_SFIELD (0x06UL<<SYS_GPN_MFPH_PN14MFP_Pos) /*!< Camera capture 1 interface SFIELD input pin. */
#define SYS_GPN_MFPH_PN14MFP_CCAP1_SFIELD (0x06UL<<SYS_GPN_MFPH_PN14MFP_Pos) /*!< Camera capture 1 interface SFIELD input pin. */
#define SYS_GPN_MFPH_PN14MFP_SPI1_I2SMCLK (0x07UL<<SYS_GPN_MFPH_PN14MFP_Pos) /*!< SPI1 I2S master clock output pin. */
#define SYS_GPN_MFPH_PN15MFP_GPIO (0x00UL<<SYS_GPN_MFPH_PN15MFP_Pos) /*!< General purpose digital I/O pin. */
#define SYS_GPN_MFPH_PN15MFP_EPWM2_CH4 (0x01UL<<SYS_GPN_MFPH_PN15MFP_Pos) /*!< EPWM2 channel4 output/capture input. */

8
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_clk.c
View File

@ -558,7 +558,7 @@ void CLK_DisableXtalRC(uint32_t u32ClkMask)
* - \ref PDMA3_MODULE
* - \ref WH0_MODULE
* - \ref WH1_MODULE
* - \ref HWS_MODULE
* - \ref HWSEM0_MODULE
* - \ref EBI_MODULE
* - \ref SRAM0_MODULE
* - \ref SRAM1_MODULE
@ -692,7 +692,7 @@ void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
* - \ref PDMA3_MODULE
* - \ref WH0_MODULE
* - \ref WH1_MODULE
* - \ref HWS_MODULE
* - \ref HWSEM0_MODULE
* - \ref EBI_MODULE
* - \ref SRAM0_MODULE
* - \ref SRAM1_MODULE
@ -1471,7 +1471,7 @@ uint64_t CLK_SetPLLFreq(uint32_t u32PllIdx, uint32_t u32OpMode, uint64_t PllSrcC
* - \ref PDMA3_MODULE
* - \ref WH0_MODULE
* - \ref WH1_MODULE
* - \ref HWS_MODULE
* - \ref HWSEM0_MODULE
* - \ref EBI_MODULE
* - \ref SRAM0_MODULE
* - \ref SRAM1_MODULE
@ -1611,7 +1611,7 @@ uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
* - \ref PDMA3_MODULE
* - \ref WH0_MODULE
* - \ref WH1_MODULE
* - \ref HWS_MODULE
* - \ref HWSEM0_MODULE
* - \ref EBI_MODULE
* - \ref SRAM0_MODULE
* - \ref SRAM1_MODULE

17
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_disp.c
View File

@ -258,6 +258,23 @@ int DISP_SetTransparencyMode(E_DISP_LAYER eLayer, E_TRANSPARENCY_MODE eTM)
return 0;
}
uint32_t DISP_LCDTIMING_GetFPS(const DISP_LCD_TIMING* psDispLCDTiming)
{
static uint32_t u32FPS = 0;
if ( psDispLCDTiming != NULL )
{
uint32_t u32HTotal, u32VTotal;
u32HTotal = psDispLCDTiming->u32HA + psDispLCDTiming->u32HBP + psDispLCDTiming->u32HFP + psDispLCDTiming->u32HSL;
u32VTotal = psDispLCDTiming->u32VA + psDispLCDTiming->u32VBP + psDispLCDTiming->u32VFP + psDispLCDTiming->u32VSL;
u32FPS = psDispLCDTiming->u32PCF / u32HTotal / u32VTotal;
}
return u32FPS;
}
int DISP_Trigger(E_DISP_LAYER eLayer, uint32_t u32Action)
{
switch (eLayer)

6
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_i2s.c
View File

@ -28,10 +28,8 @@ static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s);
* @param[in] i2s The pointer of the specified I2S module.
* @return Source clock frequency of I2S peripheral.
* @details
* 0: _HXT
* 1: APLL
* 2: PCLK0
* 3: HIRC
* 0: APLL
* 1: SYSCLK1_DIV2
*/
static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)

2
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_pdma.c
View File

@ -240,8 +240,8 @@ void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral,
if (u32ScatterEn)
{
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
pdma->DSCT[u32Ch].NEXT = u32DescAddr;
pdma->DSCT[u32Ch].CTL = (pdma->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
}
else
{

10
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_rtc.c
View File

@ -65,12 +65,12 @@ static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32
int32_t RTC_Open(S_RTC_TIME_DATA_T *sPt)
{
RTC->INIT = RTC_INIT_KEY;
if (RTC->INIT != RTC_INIT_ACTIVE_Msk)
if ((RTC->INIT & RTC_INIT_ACTIVE_Msk) != RTC_INIT_ACTIVE_Msk)
{
uint32_t u32Timeout = 10000000ul;
uint32_t volatile u32Timeout = 10000000ul;
RTC->INIT = RTC_INIT_KEY;
while ((u32Timeout > 0) && (RTC->INIT != RTC_INIT_ACTIVE_Msk))
while ((u32Timeout > 0) && ((RTC->INIT & RTC_INIT_ACTIVE_Msk) != RTC_INIT_ACTIVE_Msk))
{
u32Timeout--;
}
@ -317,7 +317,7 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCAL, u32RegTIME;
if (sPt == 0ul)
if (sPt == NULL)
{
}
else
@ -396,7 +396,7 @@ void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCALM, u32RegTALM;
if (sPt == 0)
if (sPt == NULL)
{
}
else

2
bsp/nuvoton/libraries/ma35/StdDriver/src/nu_sys.c
View File

@ -42,7 +42,7 @@ extern "C"
* - \ref WRHO1_RST
* - \ref GMAC0_RST
* - \ref GMAC1_RST
* - \ref HWSEM_RST
* - \ref HWSEM0_RST
* - \ref EBI_RST
* - \ref HSUSBH0_RST
* - \ref HSUSBH1_RST

8
bsp/nuvoton/libraries/ma35/UsbHostLib/inc/config.h
View File

@ -25,8 +25,6 @@
#define HCLK_MHZ 700 /* used for loop-delay. must be larger than
true HCLK clock MHz */
#define NON_CACHE_MASK (0xC0000000)
static __inline void ENABLE_OHCI_IRQ(void)
{
rt_hw_interrupt_umask(USBH0_IRQn);
@ -87,7 +85,7 @@ static __inline void DISABLE_EHCI_IRQ(void)
limited. */
#define MAX_UDEV_DRIVER 8 /*!< Maximum number of registered drivers */
#define MAX_ALT_PER_IFACE 8 /*!< maximum number of alternative interfaces per interface */
#define MAX_ALT_PER_IFACE 32 /*!< maximum number of alternative interfaces per interface */
#define MAX_EP_PER_IFACE 6 /*!< maximum number of endpoints per interface */
#define MAX_HUB_DEVICE 8 /*!< Maximum number of hub devices */
@ -95,8 +93,8 @@ static __inline void DISABLE_EHCI_IRQ(void)
are all allocated from this pool. Allocated unit size is determined by MEM_POOL_UNIT_SIZE.
May allocate one or more units depend on hardware descriptor type. */
#define MEM_POOL_UNIT_SIZE 64 /*!< A fixed hard coding setting. Do not change it! */
#define MEM_POOL_UNIT_NUM 256 /*!< Increase this or heap size if memory allocate failed. */
#define MEM_POOL_UNIT_SIZE 256 /*!< A fixed hard coding setting. Do not change it! */
#define MEM_POOL_UNIT_NUM 64 /*!< Increase this or heap size if memory allocate failed. */
/*----------------------------------------------------------------------------------------*/
/* Re-defined staff for various compiler */

61
bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ehci.c_
View File

@ -11,15 +11,15 @@
/// @cond HIDDEN_SYMBOLS
static QH_T *_H_qh; /* head of reclamation list */
static qTD_T *_ghost_qtd; /* used as a terminator qTD */
static QH_T *qh_remove_list;
static QH_T *_H_qh __attribute__((section(".usbhostlib._H_qh"))); /* head of reclamation list */
static qTD_T *_ghost_qtd __attribute__((section(".usbhostlib._ghost_qtd"))); /* used as a terminator qTD */
static QH_T *qh_remove_list __attribute__((section(".usbhostlib.qh_remove_list")));
static uint32_t _PFList_mem[FL_SIZE] __attribute__((aligned(4096))); /* Periodic frame list */
static uint32_t _PFList_mem[FL_SIZE] __attribute__((section(".usbhostlib._PFList_mem"))) __attribute__((aligned(4096))); /* Periodic frame list */
static uint32_t *_PFList;
static uint32_t *_PFList __attribute__((section(".usbhostlib._PFList")));
static QH_T *_Iqh[NUM_IQH];
static QH_T *_Iqh[NUM_IQH] __attribute__((section(".usbhostlib.QH_T"))) __attribute__((aligned(32)));;
static int ehci_quit_iso_xfer(UTR_T *utr, EP_INFO_T *ep);
static void scan_isochronous_list(void);
@ -29,24 +29,25 @@ static void scan_isochronous_list(void);
static void dump_ehci_regs(void)
{
USB_debug("Dump HSUSBH(0x%x) registers:\n", ptr_to_u32(&_ehci->EHCVNR));
USB_debug(" EHCVNR = 0x%x\n", _ehci->EHCVNR);
USB_debug(" EHCSPR = 0x%x\n", _ehci->EHCSPR);
USB_debug(" EHCCPR = 0x%x\n", _ehci->EHCCPR);
USB_debug(" UCMDR = 0x%x\n", _ehci->UCMDR);
USB_debug(" USTSR = 0x%x\n", _ehci->USTSR);
USB_debug(" UIENR = 0x%x\n", _ehci->UIENR);
USB_debug(" UFINDR = 0x%x\n", _ehci->UFINDR);
USB_debug(" UPFLBAR = 0x%x\n", _ehci->UPFLBAR);
USB_debug(" UCALAR = 0x%x\n", _ehci->UCALAR);
USB_debug(" UCFGR = 0x%x\n", _ehci->UCFGR);
USB_debug(" UPSCR0 = 0x%x\n", _ehci->UPSCR);
USB_debug(" EHCVNR = 0x%08x\n", _ehci->EHCVNR);
USB_debug(" EHCSPR = 0x%08x\n", _ehci->EHCSPR);
USB_debug(" EHCCPR = 0x%08x\n", _ehci->EHCCPR);
USB_debug(" UCMDR = 0x%08x\n", _ehci->UCMDR);
USB_debug(" USTSR = 0x%08x\n", _ehci->USTSR);
USB_debug(" UIENR = 0x%08x\n", _ehci->UIENR);
USB_debug(" UFINDR = 0x%08x\n", _ehci->UFINDR);
USB_debug(" UPFLBAR = 0x%08x\n", _ehci->UPFLBAR);
USB_debug(" UCALAR = 0x%08x\n", _ehci->UCALAR);
USB_debug(" UCFGR = 0x%08x\n", _ehci->UCFGR);
USB_debug(" UPSCR0 = 0x%08x\n", _ehci->UPSCR[0]);
// USB_debug(" UPSCR1 = 0x%08x\n", _ehci->UPSCR[1]);
// USB_debug(" PHYCTL0 = 0x%x\n", _ehci->USBPCR0);
// USB_debug(" PHYCTL1 = 0x%x\n", _ehci->USBPCR1);
}
static void dump_ehci_ports()
{
USB_debug("_ehci port0=0x%x\n", _ehci->UPSCR);
USB_debug("_ehci port0=0x%x, port1=0x%x\n", _ehci->UPSCR[0], _ehci->UPSCR[1]);
}
static void dump_ehci_qtd(qTD_T *qtd)
@ -150,7 +151,7 @@ static void init_periodic_frame_list()
QH_T *qh_p;
int i, idx, interval;
_PFList = (uint32_t *)((uint32_t)_PFList_mem | NON_CACHE_MASK);
_PFList = (uint32_t *)((uint32_t)&_PFList_mem[0]);
memset(_PFList, 0, sizeof(_PFList_mem));
iso_ep_list = NULL;
@ -281,6 +282,8 @@ static int ehci_init(void)
else
return USBH_ERR_EHCI_INIT; /* Invalid FL_SIZE setting! */
_ehci->UPFLBAR = (uint32_t)_PFList;
/*------------------------------------------------------------------------------------*/
/* start run */
/*------------------------------------------------------------------------------------*/
@ -295,8 +298,8 @@ static int ehci_init(void)
init_periodic_frame_list();
_ehci->UPFLBAR = (uint32_t)_PFList;
usbh_delay_ms(10); /* delay 10 ms */
//usbh_delay_ms(10); /* delay 10 ms */
//dump_ehci_regs();
return 0;
}
@ -611,6 +614,7 @@ static int ehci_ctrl_xfer(UTR_T *utr)
_H_qh->HLink = QH_HLNK_QH(qh);
}
//dump_ehci_regs();
/* Start transfer */
_ehci->UCMDR |= HSUSBH_UCMDR_ASEN_Msk; /* start asynchronous transfer */
return 0;
@ -1098,8 +1102,13 @@ void EHCI_IRQHandler(int vector, void *param)
USB_error("Transfer error!\n");
}
if (intsts & HSUSBH_USTSR_USBINT_Msk)
if (intsts & (HSUSBH_USTSR_USBINT_Msk | HSUSBH_USTSR_UERRINT_Msk))
{
if (intsts & HSUSBH_USTSR_UERRINT_Msk)
{
USB_error("Transfer error!\n");
}
/* some transfers completed, travel asynchronous */
/* and periodic lists to find and reclaim them. */
scan_asynchronous_list();
@ -1140,12 +1149,12 @@ static int ehci_rh_port_reset(int port)
_ehci->UPSCR[port] = (_ehci->UPSCR[port] | HSUSBH_UPSCR_PRST_Msk) & ~HSUSBH_UPSCR_PE_Msk;
t0 = usbh_get_ticks();
while (usbh_get_ticks() - t0 < (reset_time) + 1) ; /* wait at least 50 ms */
while (usbh_get_ticks() - t0 < (reset_time/10) + 1) ; /* wait at least 50 ms */
_ehci->UPSCR[port] &= ~HSUSBH_UPSCR_PRST_Msk;
t0 = usbh_get_ticks();
while (usbh_get_ticks() - t0 < (reset_time) + 1)
while (usbh_get_ticks() - t0 < (reset_time/10) + 1)
{
if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk) ||
((_ehci->UPSCR[port] & (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)) == (HSUSBH_UPSCR_CCS_Msk | HSUSBH_UPSCR_PE_Msk)))
@ -1174,7 +1183,7 @@ static int ehci_rh_polling(void)
int port;
int connect_status, t0, debounce_tick;
for (port = 0; port < EHCI_PORT_CNT; port++)
for (port = 0; port < 1; port++)
{
if (!(_ehci->UPSCR[port] & HSUSBH_UPSCR_CSC_Msk))
continue;
@ -1197,7 +1206,7 @@ static int ehci_rh_polling(void)
/* Port de-bounce */
/*--------------------------------------------------------------------------------*/
t0 = usbh_get_ticks();
debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME);
debounce_tick = usbh_tick_from_millisecond(HUB_DEBOUNCE_TIME/10);
connect_status = _ehci->UPSCR[port] & HSUSBH_UPSCR_CCS_Msk;
while (usbh_get_ticks() - t0 < debounce_tick)
{

46
bsp/nuvoton/libraries/ma35/UsbHostLib/src/_ohci.c_
View File

@ -17,11 +17,9 @@
#define PORT_CNT (_ohci->HcRhDescriptorA & 0xf)
static uint8_t _hcca_mem[256] __attribute__((aligned(256)));
static HCCA_T _hcca __attribute__((section(".usbhostlib._hcca"))) __attribute__((aligned(256)));
static HCCA_T *_hcca;
static ED_T *_Ied[6];
static ED_T * _Ied[6] __attribute__((section(".usbhostlib._Ied")));
static ED_T *ed_remove_list;
@ -97,7 +95,7 @@ static void init_hcca_int_table()
ED_T *ed_p;
int i, idx, interval;
memset(_hcca->int_table, 0, sizeof(_hcca->int_table));
memset(_hcca.int_table, 0, sizeof(_hcca.int_table));
for (i = 5; i >= 0; i--) /* interval = i^2 */
{
@ -108,13 +106,13 @@ static void init_hcca_int_table()
for (idx = interval - 1; idx < 32; idx += interval)
{
if (_hcca->int_table[idx] == 0) /* is empty list, insert directly */
if (_hcca.int_table[idx] == 0) /* is empty list, insert directly */
{
_hcca->int_table[idx] = (uint32_t)_Ied[i];
_hcca.int_table[idx] = (uint32_t)_Ied[i];
}
else
{
ed_p = (ED_T *)_hcca->int_table[idx];
ed_p = (ED_T *)_hcca.int_table[idx];
while (1)
{
@ -133,7 +131,7 @@ static void init_hcca_int_table()
}
}
static ED_T *get_int_tree_head_node(int interval)
static ED_T * get_int_tree_head_node(int interval)
{
int i;
@ -166,8 +164,6 @@ static int ohci_init(void)
uint32_t fminterval;
volatile int i;
_hcca = (HCCA_T *)((uint32_t)_hcca_mem | NON_CACHE_MASK);
if (ohci_reset() < 0)
return -1;
@ -180,11 +176,11 @@ static int ohci_init(void)
_ohci->HcControlHeadED = 0; /* control ED list head */
_ohci->HcBulkHeadED = 0; /* bulk ED list head */
_ohci->HcHCCA = (uint32_t)_hcca; /* HCCA area */
_ohci->HcHCCA = (uint32_t)&_hcca; /* HCCA area */
/* periodic start 90% of frame interval */
fminterval = 0x2edf; /* 11,999 */
_ohci->HcPeriodicStart = (fminterval * 9) / 10;
_ohci->HcPeriodicStart = (fminterval*9)/10;
/* set FSLargestDataPacket, 10,104 for 0x2edf frame interval */
fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
@ -342,7 +338,7 @@ static uint32_t ed_make_info(UDEV_T *udev, EP_INFO_T *ep)
static void write_td(TD_T *td, uint32_t info, uint8_t *buff, uint32_t data_len)
{
uint32_t baddr = ptr_to_u32(buff);
td->Info = info;
td->CBP = (((baddr == 0) || !data_len) ? 0 : baddr);
td->BE = (((baddr == 0) || !data_len) ? 0 : baddr + data_len - 1);
@ -661,7 +657,7 @@ static int ohci_int_xfer(UTR_T *utr)
info = (TD_CC | TD_R | TD_DP_IN | TD_TYPE_INT);
/* Keep data toggle */
info = (info & ~(1 << 25)) | (td->Info & (1 << 25));
info = (info & ~(1<<25)) | (td->Info & (1<<25));
/* fill this TD */
write_td(td, info, utr->buff, utr->data_len);
@ -735,7 +731,7 @@ static int ohci_iso_xfer(UTR_T *utr)
/* Prepare TDs */
/*------------------------------------------------------------------------------------*/
if (utr->bIsoNewSched) /* Is the starting of isochronous streaming? */
ed->next_sf = _hcca->frame_no + OHCI_ISO_DELAY;
ed->next_sf = _hcca.frame_no + OHCI_ISO_DELAY;
utr->td_cnt = 0;
utr->iso_sf = ed->next_sf;
@ -759,7 +755,7 @@ static int ohci_iso_xfer(UTR_T *utr)
td->PSW[0] = 0xE000 | (buff_addr & 0xFFF);
td->ed = ed;
utr->td_cnt++; /* increase TD count, for recalim counter */
utr->td_cnt++; /* increase TD count, for reclaim counter */
/* chain to end of TD list */
if (td_list == NULL)
@ -841,7 +837,7 @@ static int ohci_rh_port_reset(int port)
_ohci->HcRhPortStatus[port] = USBH_HcRhPortStatus_PRS_Msk;
t0 = usbh_get_ticks();
while (usbh_get_ticks() - t0 < (reset_time) + 1)
while (usbh_get_ticks() - t0 < (reset_time/10) + 1)
{
/*
* If device is disconnected or port enabled, we can stop port reset.
@ -853,7 +849,7 @@ static int ohci_rh_port_reset(int port)
reset_time += PORT_RESET_RETRY_INC_MS;
}
USB_debug("OHCI port %d - port reset failed!\n", port + 1);
USB_debug("OHCI port %d - port reset failed!\n", port+1);
return USBH_ERR_PORT_RESET;
port_reset_done:
@ -871,7 +867,7 @@ static int ohci_rh_polling(void)
UDEV_T *udev;
int ret;
for (i = 0; i < OHCI_PORT_CNT; i++)
for (i = 0; i < 1; i++)
{
/* clear unwanted port change status */
_ohci->HcRhPortStatus[i] = USBH_HcRhPortStatus_OCIC_Msk | USBH_HcRhPortStatus_PRSC_Msk |
@ -1183,8 +1179,8 @@ void OHCI_IRQHandler(int vector, void *param)
/*
* reverse done list
*/
td = (TD_T *)(_hcca->done_head & TD_ADDR_MASK);
_hcca->done_head = 0;
td = (TD_T *)(_hcca.done_head & TD_ADDR_MASK);
_hcca.done_head = 0;
td_prev = NULL;
_ohci->HcInterruptStatus = USBH_HcInterruptStatus_WDH_Msk;
@ -1232,7 +1228,7 @@ static void dump_ohci_int_table()
{
USB_debug("%02d: ", i);
ed = (ED_T *)_hcca->int_table[i];
ed = (ED_T *)_hcca.int_table[i];
while (ed != NULL)
{
@ -1268,12 +1264,14 @@ static void dump_ohci_regs()
USB_debug(" HcRhDescriptorB = 0x%x\n", _ohci->HcRhDescriptorB);
USB_debug(" HcRhStatus = 0x%x\n", _ohci->HcRhStatus);
USB_debug(" HcRhPortStatus0 = 0x%x\n", _ohci->HcRhPortStatus[0]);
USB_debug(" HcRhPortStatus1 = 0x%x\n", _ohci->HcRhPortStatus[1]);
USB_debug(" HcPhyControl = 0x%x\n", _ohci->HcPhyControl);
USB_debug(" HcMiscControl = 0x%x\n", _ohci->HcMiscControl);
}
static void dump_ohci_ports()
{
USB_debug("_ohci port0=0x%x\n", _ohci->HcRhPortStatus[0]);
USB_debug("_ohci port0=0x%x, port1=0x%x\n", _ohci->HcRhPortStatus[0], _ohci->HcRhPortStatus[1]);
}
#endif // ENABLE_DEBUG_MSG

99
bsp/nuvoton/libraries/ma35/UsbHostLib/src/mem_alloc.c
View File

@ -25,14 +25,7 @@
#define mem_debug(...)
#endif
#ifdef __ICCARM__
#pragma data_alignment=1024
uint8_t _mem_pool_buff[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE];
#else
uint8_t _mem_pool_buff[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE] __attribute__((aligned(1024)));
#endif
static uint8_t *_mem_pool[MEM_POOL_UNIT_NUM];
static uint8_t _mem_pool[MEM_POOL_UNIT_NUM][MEM_POOL_UNIT_SIZE] __attribute__((section(".usbhostlib._mem_pool"))) __attribute__((aligned(32)));
static uint8_t _unit_used[MEM_POOL_UNIT_NUM];
static volatile int _usbh_mem_used;
@ -42,7 +35,7 @@ static volatile int _mem_pool_used;
UDEV_T *g_udev_list;
uint8_t _dev_addr_pool[128];
uint8_t _dev_addr_pool[128] __attribute__((section(".usbhostlib._dev_addr_pool")));
static volatile int _device_addr;
static int _sidx = 0;;
@ -53,8 +46,6 @@ static int _sidx = 0;;
void usbh_memory_init(void)
{
int i;
if (sizeof(TD_T) > MEM_POOL_UNIT_SIZE)
{
USB_error("TD_T - MEM_POOL_UNIT_SIZE too small!\n");
@ -67,15 +58,10 @@ void usbh_memory_init(void)
while (1);
}
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
_unit_used[i] = 0;
_mem_pool[i] = (uint8_t *)((uint32_t)&_mem_pool_buff[i] | NON_CACHE_MASK);
}
_usbh_mem_used = 0L;
_usbh_max_mem_used = 0L;
memset(_unit_used, 0, sizeof(_unit_used));
_mem_pool_used = 0;
_sidx = 0;
@ -93,9 +79,13 @@ uint32_t usbh_memory_used(void)
return _usbh_mem_used;
}
static void memory_counter(int size)
static void memory_counter(int inc, int size)
{
_usbh_mem_used += size;
if (inc)
_usbh_mem_used += size;
else
_usbh_mem_used -= size;
if (_usbh_mem_used > _usbh_max_mem_used)
_usbh_max_mem_used = _usbh_mem_used;
}
@ -104,7 +94,7 @@ void *usbh_alloc_mem(int size)
{
void *p;
p = USB_malloc(size, 16);
p = USB_malloc(size, 4);
if (p == NULL)
{
USB_error("usbh_alloc_mem failed! %d\n", size);
@ -112,14 +102,14 @@ void *usbh_alloc_mem(int size)
}
memset(p, 0, size);
memory_counter(size);
memory_counter(1, size);
return p;
}
void usbh_free_mem(void *p, int size)
{
USB_free(p);
memory_counter(0 - size);
memory_counter(0, size);
}
@ -131,15 +121,14 @@ UDEV_T *alloc_device(void)
{
UDEV_T *udev;
udev = (UDEV_T *)USB_malloc(sizeof(*udev), 16);
udev = (UDEV_T *)USB_malloc(sizeof(*udev), 4);
if (udev == NULL)
{
USB_error("alloc_device failed!\n");
return NULL;
}
memset(udev, 0, sizeof(*udev));
memory_counter(sizeof(*udev));
memory_counter(1, sizeof(*udev));
udev->cur_conf = -1; /* must! used to identify the first SET CONFIGURATION */
udev->next = g_udev_list; /* chain to global device list */
g_udev_list = udev;
@ -177,7 +166,7 @@ void free_device(UDEV_T *udev)
}
}
USB_free(udev);
memory_counter(-sizeof(*udev));
memory_counter(0, sizeof(*udev));
}
int alloc_dev_address(void)
@ -212,39 +201,19 @@ void free_dev_address(int dev_addr)
UTR_T *alloc_utr(UDEV_T *udev)
{
#if 0
UTR_T *utr, *utr_noncache;
utr = (UTR_T *)USB_malloc(sizeof(*utr), 16);
if (utr == NULL)
{
USB_error("alloc_utr failed!\n");
return NULL;
}
utr_noncache = (UTR_T *)((uint32_t)utr | NONCACHEABLE);
memory_counter(sizeof(*utr));
memset(utr_noncache, 0, sizeof(*utr));
utr_noncache->udev = udev;
mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr_noncache);
return utr_noncache;
#else
UTR_T *utr;
utr = (UTR_T *)USB_malloc(sizeof(*utr), 16);
utr = (UTR_T *)USB_malloc(sizeof(*utr), 4);
if (utr == NULL)
{
USB_error("alloc_utr failed!\n");
return NULL;
}
memory_counter(sizeof(*utr));
memory_counter(1, sizeof(*utr));
memset(utr, 0, sizeof(*utr));
utr->udev = udev;
mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr_noncache);
mem_debug("[ALLOC] [UTR] - 0x%x\n", (int)utr);
return utr;
#endif
}
void free_utr(UTR_T *utr)
@ -253,14 +222,8 @@ void free_utr(UTR_T *utr)
return;
mem_debug("[FREE] [UTR] - 0x%x\n", (int)utr);
#if 0
if ((uint32_t)utr & NONCACHEABLE)
utr = (UTR_T *)((uint32_t)utr & ~NONCACHEABLE);
#endif
USB_free(utr);
memory_counter(0 - (int)sizeof(*utr));
memory_counter(0, (int)sizeof(*utr));
}
/*--------------------------------------------------------------------------*/
@ -278,7 +241,7 @@ ED_T *alloc_ohci_ED(void)
{
_unit_used[i] = 1;
_mem_pool_used++;
ed = (ED_T *)_mem_pool[i];
ed = (ED_T *)&_mem_pool[i];
memset(ed, 0, sizeof(*ed));
mem_debug("[ALLOC] [ED] - 0x%x\n", (int)ed);
return ed;
@ -294,7 +257,7 @@ void free_ohci_ED(ED_T *ed)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)ed)
if ((uint32_t)&_mem_pool[i] == (uint32_t)ed)
{
mem_debug("[FREE] [ED] - 0x%x\n", (int)ed);
_unit_used[i] = 0;
@ -319,7 +282,7 @@ TD_T *alloc_ohci_TD(UTR_T *utr)
{
_unit_used[i] = 1;
_mem_pool_used++;
td = (TD_T *)_mem_pool[i];
td = (TD_T *)&_mem_pool[i];
memset(td, 0, sizeof(*td));
td->utr = utr;
@ -337,7 +300,7 @@ void free_ohci_TD(TD_T *td)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)td)
if ((uint32_t)&_mem_pool[i] == (uint32_t)td)
{
mem_debug("[FREE] [TD] - 0x%x\n", (int)td);
_unit_used[i] = 0;
@ -363,7 +326,7 @@ QH_T *alloc_ehci_QH(void)
_unit_used[i] = 1;
_sidx = i;
_mem_pool_used++;
qh = (QH_T *)_mem_pool[i];
qh = (QH_T *)&_mem_pool[i];
memset(qh, 0, sizeof(*qh));
mem_debug("[ALLOC] [QH] - 0x%x\n", (int)qh);
break;
@ -387,7 +350,7 @@ void free_ehci_QH(QH_T *qh)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)qh)
if ((uint32_t)&_mem_pool[i] == (uint32_t)qh)
{
mem_debug("[FREE] [QH] - 0x%x\n", (int)qh);
_unit_used[i] = 0;
@ -413,7 +376,7 @@ qTD_T *alloc_ehci_qTD(UTR_T *utr)
_unit_used[i] = 1;
_sidx = i;
_mem_pool_used++;
qtd = (qTD_T *)_mem_pool[i];
qtd = (qTD_T *)&_mem_pool[i];
memset(qtd, 0, sizeof(*qtd));
qtd->Next_qTD = QTD_LIST_END;
@ -434,7 +397,7 @@ void free_ehci_qTD(qTD_T *qtd)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)qtd)
if ((uint32_t)&_mem_pool[i] == (uint32_t)qtd)
{
mem_debug("[FREE] [qTD] - 0x%x\n", (int)qtd);
_unit_used[i] = 0;
@ -463,7 +426,7 @@ iTD_T *alloc_ehci_iTD(void)
_unit_used[i] = _unit_used[i + 1] = 1;
_sidx = i + 1;
_mem_pool_used += 2;
itd = (iTD_T *)_mem_pool[i];
itd = (iTD_T *)&_mem_pool[i];
memset(itd, 0, sizeof(*itd));
mem_debug("[ALLOC] [iTD] - 0x%x\n", (int)itd);
return itd;
@ -479,7 +442,7 @@ void free_ehci_iTD(iTD_T *itd)
for (i = 0; i + 1 < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)itd)
if ((uint32_t)&_mem_pool[i] == (uint32_t)itd)
{
mem_debug("[FREE] [iTD] - 0x%x\n", (int)itd);
_unit_used[i] = _unit_used[i + 1] = 0;
@ -505,7 +468,7 @@ siTD_T *alloc_ehci_siTD(void)
_unit_used[i] = 1;
_sidx = i;
_mem_pool_used ++;
sitd = (siTD_T *)_mem_pool[i];
sitd = (siTD_T *)&_mem_pool[i];
memset(sitd, 0, sizeof(*sitd));
mem_debug("[ALLOC] [siTD] - 0x%x\n", (int)sitd);
return sitd;
@ -521,7 +484,7 @@ void free_ehci_siTD(siTD_T *sitd)
for (i = 0; i < MEM_POOL_UNIT_NUM; i++)
{
if ((uint32_t)_mem_pool[i] == (uint32_t)sitd)
if ((uint32_t)&_mem_pool[i] == (uint32_t)sitd)
{
mem_debug("[FREE] [siTD] - 0x%x\n", (int)sitd);
_unit_used[i] = 0;

5
bsp/nuvoton/libraries/ma35/UsbHostLib/src/support.c
View File

@ -39,8 +39,7 @@ typedef struct USB_mhdr
uint32_t reserved;
} USB_MHDR_T;
uint8_t _USBMemoryPool[USB_MEMORY_POOL_SIZE] __attribute__((aligned(USB_MEM_BLOCK_SIZE)));
uint8_t _USBMemoryPool[USB_MEMORY_POOL_SIZE] __attribute__((section(".usbhostlib.USBMemoryPool"))) __attribute__((aligned(USB_MEM_BLOCK_SIZE)));
static USB_MHDR_T *_pCurrent;
uint32_t *_USB_pCurrent = (uint32_t *) &_pCurrent;
@ -50,7 +49,7 @@ static uint32_t _MemoryPoolBase, _MemoryPoolEnd;
void USB_InitializeMemoryPool()
{
_MemoryPoolBase = (uint32_t)&_USBMemoryPool[0] | NON_CACHE_MASK;
_MemoryPoolBase = (uint32_t)&_USBMemoryPool[0];
_MemoryPoolEnd = _MemoryPoolBase + USB_MEMORY_POOL_SIZE;
_FreeMemorySize = _MemoryPoolEnd - _MemoryPoolBase;
_AllocatedMemorySize = 0;

2
bsp/nuvoton/libraries/ma35/UsbHostLib/src/usb_core.c
View File

@ -103,6 +103,7 @@ int usbh_polling_root_hubs(void)
int ret, change = 0;
#ifdef ENABLE_EHCI0
//_ehci0->UPSCR[1] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port 2 owner to OHCI */
do
{
ret = ehci0_driver.rthub_polling();
@ -114,6 +115,7 @@ int usbh_polling_root_hubs(void)
#endif
#ifdef ENABLE_EHCI1
//_ehci1->UPSCR[1] = HSUSBH_UPSCR_PP_Msk | HSUSBH_UPSCR_PO_Msk; /* set port 2 owner to OHCI */
do
{
ret = ehci1_driver.rthub_polling();

65
bsp/nuvoton/libraries/ma35/rtt_port/Kconfig
View File

@ -5,6 +5,32 @@
select RT_USING_USER_MAIN
default y
config BSP_USING_SSPCC
bool
depends on SOC_SERIES_MA35D1 && !USE_MA35D1_SUBM
default y
config BSP_USING_SSMCC
bool
depends on SOC_SERIES_MA35D1 && !USE_MA35D1_SUBM
default y
config BSP_USING_UMCTL2
bool
depends on SOC_SERIES_MA35D1 && !USE_MA35D1_SUBM
default y
config BSP_USING_RTP
bool
depends on SOC_SERIES_MA35D1 && !USE_MA35D1_SUBM
default y
if BSP_USING_RTP
config RTP_USING_AT_STARTUP
bool "Enable RTP Executation at startup"
default y
endif
config USE_MA35D1_AARCH32
bool
select ARCH_ARM_CORTEX_A
@ -17,6 +43,15 @@
bool
select ARCH_ARMV8
if USE_MA35D1_AARCH64
config BSP_USING_GIC
bool
default y
config BSP_USING_GICV2
bool
default y
endif
config USE_MA35D1_SUBM
bool
select ARCH_ARM_CORTEX_M4
@ -1098,6 +1133,36 @@
default n
endif
config BSP_USING_HWSEM
bool "Enable Hardware semaphore(HWSEM)"
default y
if BSP_USING_HWSEM
config BSP_USING_HWSEM0
bool "Enable HWSEM0"
default y
endif
config BSP_USING_WHC
bool "Enable Wormhole(WHC)"
default y
if BSP_USING_WHC
config BSP_USING_WHC0
bool "Enable WHC0"
default y
config BSP_USING_WHC1
bool "Enable WHC1"
depends on !USE_MA35D1_SUBM
default n
endif
config BSP_USING_NFI
bool "Enable Raw NAND flash Interface(NFI)"
depends on !USE_MA35D1_SUBM
default y
config BSP_USING_EBI
bool "Enable External Bus Interface(EBI)"
default n

27
bsp/nuvoton/libraries/ma35/rtt_port/drv_common.h
View File

@ -21,7 +21,9 @@
#include "gic.h"
#include "mmu.h"
#include "cp15.h"
#if defined(USE_MA35D1_AARCH32)
#include "cp15.h"
#endif
#include "gtimer.h"
#define __REG32(x) (*((volatile unsigned int*)((rt_ubase_t)x)))
@ -35,21 +37,6 @@
#define DDR_LIMIT_SIZE 0xC0000000u
#define UNCACHEABLE 0x40000000u
#define SSPCC_SET_REALM(IP, REALM) \
do { \
rt_kprintf("Set %s realm to %s(%d)\n", #IP, #REALM, REALM); \
SSPCC_SetRealm(IP, REALM); \
rt_kprintf("Get %s realm is %d ....%s\n", #IP, SSPCC_GetRealm(IP), (SSPCC_GetRealm(IP)==REALM)?"Success":"Failure"); \
} while(0)
#define SSPCC_SET_GPIO_REALM(PORT, PIN, REALM) \
do { \
rt_kprintf("Set %s%s realm to %s(%d)\n", #PORT, #PIN, #REALM, REALM); \
SSPCC_SetRealm_GPIO((uint32_t)PORT, PIN, REALM); \
rt_kprintf("Get %s%s realm is %d ....%s\n", #PORT, #PIN, SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN), (SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN)==REALM)?"Success":"Failure"); \
} while(0)
/* the basic constants needed by gic */
rt_inline rt_uint32_t platform_get_gic_dist_base(void)
{
@ -72,12 +59,16 @@ rt_inline rt_uint32_t nu_cpu_dcache_line_size(void)
return 4 << ((ctr >> 16) & 0xF);
}
extern void rt_hw_cpu_dcache_clean(void *addr, int size);
extern void rt_hw_cpu_dcache_clean_inv(void *addr, int size);
extern void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, int size);
extern void rt_hw_cpu_dcache_invalidate(void *addr, int size);
#else
#define UNCACHEABLE 0
#endif
void nu_clock_init(void);
#define REGION_ADDR_SRAM0 0x24000000
#define REGION_ADDR_DDR (0x80020000|UNCACHEABLE)
#define REGION_MAXSIZE_SRAM0 (128*1024)
#define REGION_MAXSIZE_DDR (4*1024*1024-REGION_MAXSIZE_SRAM0)
#define REGION_MAXSIZE_LIMIT (REGION_MAXSIZE_SRAM0+REGION_MAXSIZE_DDR)
#endif /* __DRV_COMMON_H__ */

270
bsp/nuvoton/libraries/ma35/rtt_port/drv_common.c → bsp/nuvoton/libraries/ma35/rtt_port/drv_common_aarch32.c
View File

@ -11,21 +11,25 @@
******************************************************************************/
#include <rtthread.h>
#if defined(USE_MA35D1_AARCH32)
#include <rthw.h>
#include <stdio.h>
#include "drv_common.h"
#include "board.h"
#include "drv_uart.h"
#include "drv_sspcc.h"
#include "drv_ssmcc.h"
#include "drv_umctl2.h"
#define LOG_TAG "drv.common"
#undef DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_LEVEL LOG_LVL_INFO
#define DBG_COLOR
#include <rtdbg.h>
#if defined(USE_MA35D1_AARCH32)
#define NORMAL_MEM_UNCACHED (SHARED|AP_RW|DOMAIN0|STRONGORDER|DESC_SEC)
/*
@ -46,26 +50,23 @@ struct mem_desc platform_mem_desc[] =
{0xC0000000, 0xFFFFFFFF, 0x80000000, NORMAL_MEM_UNCACHED} // 1GB DDR, non-cacheable
};
const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
#endif
/**
* This function will initialize board
*/
static void nu_mmu_initialize(void)
{
#if defined(USE_MA35D1_AARCH64)
mmu_init();
/* device memory 0x0000_0000 - 0x3FFF_FFFF */
armv8_map(0x00000000, 0x00000000, 0x40000000, MEM_ATTR_IO);
/* device memory 0x4000_0000 - 0x7FFF_FFFF */
armv8_map(0x40000000, 0x40000000, 0x40000000, MEM_ATTR_IO);
/* system memory 0x8000_0000 - 0xFFFF_FFFF */
armv8_map(0x80000000, 0x80000000, 0x80000000, MEM_ATTR_MEMORY);
mmu_enable();
#endif
}
rt_mmu_info mmu_info;
#if !defined(USE_MA35D1_SUBM)
extern size_t MMUTable[];
extern void nu_clock_dump(void);
extern void nu_clock_raise(void);
extern void nu_clock_init(void);
extern void nu_chipcfg_dump(void);
extern uint32_t nu_chipcfg_ddrsize(void);
volatile uint32_t secondary_cpu_entry __attribute__((aligned(32))) = 0;
static rt_uint32_t timerStep;
void rt_hw_systick_isr(int vector, void *parameter)
{
gtimer_set_load_value(timerStep);
@ -83,42 +84,6 @@ int rt_hw_systick_init(void)
return 0;
}
void nu_sspcc_init(void)
{
int i, j;
CLK->APBCLK2 |= CLK_APBCLK2_SSPCCEN_Msk;
/* Set all GPIO security set to TZNS. */
for (i = 0; i < 16; i++)
{
for (j = 0; j < 14; j++)
{
SSPCC_SetRealm_GPIO(GPIO_BASE + (j * 0x40), i, SSPCC_SSET_TZNS);
}
}
}
void nu_ssmcc_init(void)
{
CLK->APBCLK2 |= CLK_APBCLK2_SSMCCEN_Msk;
/* set region 0 to secure region, non-secure and m4 all can access */
SSMCC_SetRegion0(SSMCC_SECURE_READ | SSMCC_SECURE_WRITE | SSMCC_NONSECURE_READ | SSMCC_NONSECURE_WRITE | SSMCC_M4NS_READ | SSMCC_M4NS_WRITE);
}
void nu_ddr_init(void)
{
UMCTL2->PCTRL_0 = UMCTL2_PCTRL_0_port_en_Msk; //[0x0490]
UMCTL2->PCTRL_1 = UMCTL2_PCTRL_1_port_en_Msk; //[0x0540]
UMCTL2->PCTRL_2 = UMCTL2_PCTRL_2_port_en_Msk; //[0x05f0]
UMCTL2->PCTRL_3 = UMCTL2_PCTRL_3_port_en_Msk; //[0x06a0]
UMCTL2->PCTRL_4 = UMCTL2_PCTRL_4_port_en_Msk; //[0x0750]
UMCTL2->PCTRL_5 = UMCTL2_PCTRL_5_port_en_Msk; //[0x0800]
UMCTL2->PCTRL_6 = UMCTL2_PCTRL_6_port_en_Msk; //[0x08b0]
UMCTL2->PCTRL_7 = UMCTL2_PCTRL_7_port_en_Msk; //[0x0960]
}
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
@ -156,154 +121,13 @@ void rt_hw_us_delay(rt_uint32_t us)
}
} /* rt_hw_us_delay */
#else
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
int rt_hw_systick_init(void)
{
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/* Configure SysTick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
return 0;
}
/**
* The time delay function.
*
* @param microseconds.
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
#endif
void devmem(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, mode = 0;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "0x%x", &value) != 1)
goto exit_devmem;
mode = 1; //Write
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (mode)
{
*((volatile uint32_t *)u32Addr) = value;
}
rt_kprintf("0x%08x\n", *((volatile uint32_t *)u32Addr));
return;
exit_devmem:
rt_kprintf("Read: devmem <physical address in hex>\n");
rt_kprintf("Write: devmem <physical address in hex> <value in hex format>\n");
return;
}
MSH_CMD_EXPORT(devmem, dump device registers);
void devmem2(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, word_count = 1;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "%d", &value) != 1)
goto exit_devmem;
word_count = value;
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (word_count > 0)
{
LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t));
}
return;
exit_devmem:
rt_kprintf("devmem2: <physical address in hex> <count in dec>\n");
return;
}
MSH_CMD_EXPORT(devmem2, dump device registers);
void idle_wfi(void)
{
#if defined(USE_MA35D1_SUBM)
__WFI();
#else
asm volatile("wfi");
#endif
}
extern void nu_clock_dump(void);
extern void nu_clock_raise(void);
rt_weak void nutool_pincfg_init(void)
{
}
/**
@ -311,10 +135,11 @@ rt_weak void nutool_pincfg_init(void)
*/
rt_weak void rt_hw_board_init(void)
{
uint32_t u32BoardHeapEnd;
/* Unlock protected registers */
SYS_UnlockReg();
#if !defined(USE_MA35D1_SUBM)
/* initialize SSPCC */
nu_sspcc_init();
@ -322,25 +147,32 @@ rt_weak void rt_hw_board_init(void)
nu_ssmcc_init();
/* initialize UMCTL2 */
nu_ddr_init();
#endif
nu_umctl2_init();
/* initialize base clock */
nu_clock_init();
/* initialize peripheral pin function */
nutool_pincfg_init();
rt_hw_mmu_map_init(&mmu_info, (void*)0x80000000, 0x10000000, MMUTable, 0);
rt_hw_mmu_ioremap_init(&mmu_info, (void*)0x80000000, 0x10000000);
/* initialize hardware interrupt */
rt_hw_interrupt_init();
/* initialize MMU */
nu_mmu_initialize();
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)BOARD_HEAP_START, (void *)BOARD_HEAP_END);
if (nu_chipcfg_ddrsize() > 0)
{
/* Get MCP DDR capacity in run-time. */
u32BoardHeapEnd = 0x80000000 + nu_chipcfg_ddrsize();
}
else
{
/* Use board.h definition */
u32BoardHeapEnd = (uint32_t)BOARD_HEAP_END;
}
rt_system_heap_init((void *)BOARD_HEAP_START, (void *)u32BoardHeapEnd);
#endif
/* initialize uart */
@ -350,18 +182,7 @@ rt_weak void rt_hw_board_init(void)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#if !defined(USE_MA35D1_SUBM)
#if !defined(USE_MA35D1_AARCH64)
//TOFIX
nu_clock_raise();
#endif
nu_clock_dump();
#endif
#if defined(RT_USING_HEAP)
/* Dump heap information */
rt_kprintf("Heap: Begin@%08x, END@%08x, SIZE: %d KiB\n", BOARD_HEAP_START, BOARD_HEAP_END, ((rt_uint32_t)BOARD_HEAP_END - (rt_uint32_t)BOARD_HEAP_START) / 1024);
#endif
/* initialize systick */
rt_hw_systick_init();
@ -371,22 +192,29 @@ rt_weak void rt_hw_board_init(void)
rt_components_board_init();
#endif
#if defined(RT_USING_HEAP)
/* Dump heap information */
LOG_I("Heap: Begin@%08x, END@%08x, SIZE: %d MB", BOARD_HEAP_START, u32BoardHeapEnd, ((rt_uint32_t)u32BoardHeapEnd - (rt_uint32_t)BOARD_HEAP_START) / 1024 / 1024);
#endif
nu_chipcfg_dump();
nu_clock_dump();
#if defined(RT_USING_SMP)
/* install IPI handle */
rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
#endif
}
#if defined(RT_USING_SMP)
extern void secondary_cpu_start(void);
extern void rt_secondary_cpu_entry(void);
void set_secondary_cpu_boot_address(void)
{
secondary_cpu_entry = (uint32_t)&secondary_cpu_start;
rt_kprintf("Wake up cpu-1 goto -> 0x%08x\n", secondary_cpu_entry);
secondary_cpu_entry = (uint32_t)&rt_secondary_cpu_entry;
rt_kprintf("Wake up cpu-1 goto -> 0x%08x@0x%08x\n", secondary_cpu_entry, &secondary_cpu_entry);
}
void rt_hw_secondary_cpu_up(void)
@ -414,7 +242,7 @@ void rt_hw_secondary_cpu_up(void)
}
}
void secondary_cpu_c_start(void)
void rt_hw_secondary_cpu_bsp_start(void)
{
rt_kprintf("[%s] cpu-%d\r\n", __func__, rt_hw_cpu_id());
@ -435,3 +263,5 @@ void rt_hw_secondary_cpu_idle_exec(void)
}
#endif
#endif /* #if defined(USE_MA35D1_AARCH32) */

144
bsp/nuvoton/libraries/ma35/rtt_port/drv_common_subm.c Normal file
View File

@ -0,0 +1,144 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-07-14 Wayne First version
*
******************************************************************************/
#include <rtthread.h>
#if defined(USE_MA35D1_SUBM)
#include <rthw.h>
#include <stdio.h>
#include "drv_common.h"
#include "board.h"
#include "drv_uart.h"
#define LOG_TAG "drv.common"
#undef DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_COLOR
#include <rtdbg.h>
extern void nu_clock_init(void);
void SysTick_Handler(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
int rt_hw_systick_init(void)
{
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/* Configure SysTick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
return 0;
}
/**
* The time delay function.
*
* @param microseconds.
*/
void rt_hw_us_delay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = SysTick->LOAD;
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
told = SysTick->VAL;
while (1)
{
tnow = SysTick->VAL;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
void idle_wfi(void)
{
__WFI();
}
rt_weak void nutool_pincfg_init(void)
{
}
/**
* This function will initial board.
*/
rt_weak void rt_hw_board_init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* initialize base clock */
nu_clock_init();
/* initialize peripheral pin function */
nutool_pincfg_init();
/* initialize hardware interrupt */
rt_hw_interrupt_init();
#if defined(RT_USING_HEAP)
rt_system_heap_init((void *)BOARD_HEAP_START, (void *)BOARD_HEAP_END);
#endif
/* initialize uart */
rt_hw_uart_init();
#if defined(RT_USING_CONSOLE)
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
#if defined(RT_USING_HEAP)
/* Dump heap information */
rt_kprintf("Heap: Begin@%08x, END@%08x, SIZE: %d KiB\n", BOARD_HEAP_START, BOARD_HEAP_END, ((rt_uint32_t)BOARD_HEAP_END - (rt_uint32_t)BOARD_HEAP_START) / 1024);
#endif
/* initialize systick */
rt_hw_systick_init();
rt_thread_idle_sethook(idle_wfi);
#if defined(RT_USING_COMPONENTS_INIT)
rt_components_board_init();
#endif
}
#endif

36
bsp/nuvoton/libraries/ma35/rtt_port/drv_disp.c
View File

@ -53,6 +53,10 @@ typedef struct nu_disp *nu_disp_t;
static volatile uint32_t g_u32VSyncBlank = 0;
static struct rt_completion vsync_wq;
#if defined(DISP_USING_OVERLAY)
static rt_mutex_t disp_lock;
#endif
static struct nu_disp nu_fbdev[eLayer_Cnt] =
{
{
@ -69,9 +73,9 @@ static struct nu_disp nu_fbdev[eLayer_Cnt] =
#endif
};
rt_weak void nu_lcd_backlight_on(void) { }
RT_WEAK void nu_lcd_backlight_on(void) { }
rt_weak void nu_lcd_backlight_off(void) { }
RT_WEAK void nu_lcd_backlight_off(void) { }
static void nu_disp_isr(int vector, void *param)
{
@ -88,6 +92,10 @@ static rt_err_t disp_layer_open(rt_device_t dev, rt_uint16_t oflag)
nu_disp_t psDisp = (nu_disp_t)dev;
RT_ASSERT(psDisp != RT_NULL);
#if defined(DISP_USING_OVERLAY)
rt_mutex_take(disp_lock, RT_WAITING_FOREVER);
#endif
psDisp->ref_count++;
#if defined(DISP_USING_OVERLAY)
@ -112,6 +120,10 @@ static rt_err_t disp_layer_open(rt_device_t dev, rt_uint16_t oflag)
}
#endif
#if defined(DISP_USING_OVERLAY)
rt_mutex_release(disp_lock);
#endif
return RT_EOK;
}
@ -120,6 +132,10 @@ static rt_err_t disp_layer_close(rt_device_t dev)
nu_disp_t psDisp = (nu_disp_t)dev;
RT_ASSERT(psDisp != RT_NULL);
#if defined(DISP_USING_OVERLAY)
rt_mutex_take(disp_lock, RT_WAITING_FOREVER);
#endif
psDisp->ref_count--;
#if defined(DISP_USING_OVERLAY)
@ -140,6 +156,10 @@ static rt_err_t disp_layer_close(rt_device_t dev)
DISP_Trigger(eLayer_Video, 0);
}
#if defined(DISP_USING_OVERLAY)
rt_mutex_release(disp_lock);
#endif
return RT_EOK;
}
@ -208,8 +228,6 @@ static rt_err_t disp_layer_control(rt_device_t dev, int cmd, void *args)
/* Initial LCD */
DISP_SetFBFmt(psDisp->layer, eFBFmt, psDisp->info.pitch);
}
break;
@ -243,7 +261,7 @@ static rt_err_t disp_layer_control(rt_device_t dev, int cmd, void *args)
if (psDisp->last_commit >= g_u32VSyncBlank)
{
rt_completion_init(&vsync_wq);
rt_completion_wait(&vsync_wq, RT_TICK_PER_SECOND / 60);
rt_completion_wait(&vsync_wq, RT_TICK_PER_SECOND / DISP_LCDTIMING_GetFPS(RT_NULL));
}
}
break;
@ -331,12 +349,20 @@ int rt_hw_disp_init(void)
rt_kprintf("%s's fbdev video memory at 0x%08x.\n", psDisp->name, psDisp->info.framebuffer);
}
#if defined(DISP_USING_OVERLAY)
/* Initial display lock */
disp_lock = rt_mutex_create("displock", RT_IPC_FLAG_FIFO);
RT_ASSERT(disp_lock);
#endif
/* Register ISR */
rt_hw_interrupt_install(DISP_IRQn, nu_disp_isr, RT_NULL, "DISP");
/* Enable interrupt. */
rt_hw_interrupt_umask(DISP_IRQn);
rt_kprintf("LCD panel timing is %d FPS.\n", DISP_LCDTIMING_GetFPS(&psDispLcdInstance->sLcdTiming));
return (int)ret;
}
INIT_DEVICE_EXPORT(rt_hw_disp_init);

310
bsp/nuvoton/libraries/ma35/rtt_port/drv_hwsem.c Normal file
View File

@ -0,0 +1,310 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#include <rtconfig.h>
#if defined(BSP_USING_HWSEM)
#include <rthw.h>
#include "drv_hwsem.h"
#include "drv_sys.h"
#include "drv_common.h"
#include "nu_bitutil.h"
/* Private define ---------------------------------------------------------------*/
enum
{
HWSEM_START = -1,
#if defined(BSP_USING_HWSEM0)
HWSEM0_IDX,
#endif
HWSEM_END
};
/* Private typedef --------------------------------------------------------------*/
struct nu_mutex_priv
{
struct nu_mutex parent;
rt_thread_t owner;
uint8_t key;
uint8_t hold;
struct rt_completion completion;
void *user_data;
};
typedef struct nu_mutex_priv *nu_mutex_priv_t;
struct nu_hwsem
{
struct rt_device dev;
char *name;
HWSEM_T *base;
IRQn_Type irqn;
uint32_t rstidx;
struct nu_mutex_priv mutex[evHWSEM_CNT];
};
typedef struct nu_hwsem *nu_hwsem_t;
static struct nu_hwsem nu_hwsem_arr [] =
{
#if defined(BSP_USING_HWSEM0)
{
.name = "hwsem0",
.base = HWSEM0,
.irqn = HWSEM0_IRQn,
.rstidx = HWSEM0_RST,
},
#endif
}; /* nu_hwsem */
/**
* All HWSEM interrupt service routine
*/
static void nu_hwsem_isr(int vector, void *param)
{
nu_hwsem_t psNuHwSem = (nu_hwsem_t)param;
rt_int32_t irqidx;
volatile uint32_t vu32Intsts = psNuHwSem->base->INTSTS_CORE;
while ((irqidx = nu_ctz(vu32Intsts)) < evHWSEM_CNT)
{
nu_mutex_priv_t priv = (nu_mutex_priv_t)&psNuHwSem->mutex[irqidx];
uint32_t u32IsrBitMask = 1 << irqidx ;
HWSEM_CLR_INT_FLAG(psNuHwSem->base, irqidx);
/* Unlocked, Signal waiter. */
rt_completion_done(&priv->completion);
/* Clear sent bit */
vu32Intsts &= ~(u32IsrBitMask);
}
}
nu_mutex_t nu_mutex_init(struct rt_device *device, E_HWSEM_ID id)
{
if (id < evHWSEM_CNT)
{
nu_hwsem_t psNuHwSem = (nu_hwsem_t)device->user_data;
nu_mutex_t mutex = (nu_mutex_t)&psNuHwSem->mutex[id];
nu_mutex_priv_t priv = (nu_mutex_priv_t)mutex;
if (!priv->owner)
{
priv->owner = rt_thread_self();
}
else
{
goto exit_nu_mutex_init;
}
return mutex;
}
exit_nu_mutex_init:
return RT_NULL;
}
void nu_mutex_deinit(struct rt_device *device, E_HWSEM_ID id)
{
if (id < evHWSEM_CNT)
{
nu_hwsem_t psNuHwSem = (nu_hwsem_t)device->user_data;
nu_mutex_t mutex = (nu_mutex_t)&psNuHwSem->mutex[id];
nu_mutex_priv_t priv = (nu_mutex_priv_t)mutex;
if (priv->owner == rt_thread_self())
{
priv->owner = RT_NULL;
}
}
}
rt_err_t nu_mutex_take(nu_mutex_t mutex, rt_int32_t timeout)
{
rt_err_t ret = RT_EOK;
nu_mutex_priv_t priv = (nu_mutex_priv_t)mutex;
nu_hwsem_t dev = (nu_hwsem_t)priv->user_data;
uint8_t u8PrivKey = priv->key;
#ifdef RT_USING_SMP
u8PrivKey |= (rt_hw_cpu_id() << 6);
#endif /* RT_USING_SMP */
if (priv->owner != rt_thread_self())
{
return -RT_ERROR;
}
rt_completion_init(&priv->completion);
while (1)
{
if (HWSEM_IS_LOCKED(dev->base, mutex->id) != HWSEM_NOLOCK)
{
/* LOCKED */
if (HWSEM_GET_KEY(dev->base, mutex->id) != u8PrivKey)
{
/* Enable interrupt */
HWSEM_ENABLE_INT(dev->base, mutex->id);
/* owner is NOT me. */
if (rt_completion_wait(&priv->completion, timeout) != RT_EOK)
{
ret = -RT_EBUSY;
break;
}
else
{
/* Got notification, do lock. */
}
}
else
{
/* owner is me. */
priv->hold++;
break;
}
}
else
{
/* NOLOCK, To lock */
HWSEM_LOCK(dev->base, mutex->id, u8PrivKey);
if (HWSEM_GET_KEY(dev->base, mutex->id) == u8PrivKey)
{
/* owner is me. */
priv->hold = 1;
/* Disable interrupt */
HWSEM_DISABLE_INT(dev->base, mutex->id);
break;
}
else
{
/* Failed to lock, owner is not me. wait notification. */
}
}
} //while(1)
return ret;
}
RTM_EXPORT(nu_mutex_take);
rt_err_t nu_mutex_release(nu_mutex_t mutex)
{
rt_err_t ret = RT_EOK;
nu_mutex_priv_t priv = (nu_mutex_priv_t)mutex;
nu_hwsem_t dev = (nu_hwsem_t)priv->user_data;
uint8_t u8PrivKey = priv->key;
if (priv->owner != rt_thread_self())
{
return -RT_ERROR;
}
#ifdef RT_USING_SMP
u8PrivKey |= (rt_hw_cpu_id() << 6);
#endif /* RT_USING_SMP */
if (HWSEM_IS_LOCKED(dev->base, mutex->id) != 0 &&
HWSEM_GET_KEY(dev->base, mutex->id) == u8PrivKey)
{
priv->hold--;
if (priv->hold == 0)
{
/* Unlocked */
HWSEM_UNLOCK(dev->base, mutex->id, u8PrivKey);
}
}
else
{
ret = -RT_ERROR;
}
return ret;
}
RTM_EXPORT(nu_mutex_release);
static rt_err_t hwsem_register(struct rt_device *device, const char *name, void *user_data)
{
RT_ASSERT(device);
device->type = RT_Device_Class_Miscellaneous;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
device->ops = RT_NULL;
#else
device->init = RT_NULL;
device->open = RT_NULL;
device->close = RT_NULL;
device->read = RT_NULL;
device->write = RT_NULL;
device->control = RT_NULL;
#endif
device->user_data = user_data;
return rt_device_register(device, name, RT_DEVICE_FLAG_RDONLY | RT_DEVICE_FLAG_STANDALONE);
}
/**
* Hardware Sem Initialization
*/
int rt_hw_hwsem_init(void)
{
int i, j;
rt_err_t ret = RT_EOK;
for (i = (HWSEM_START + 1); i < HWSEM_END; i++)
{
#if !defined(USE_MA35D1_SUBM)
/* Reset this module */
nu_sys_ip_reset(nu_hwsem_arr[i].rstidx);
#endif
for (j = 0; j < evHWSEM_CNT; j++)
{
nu_hwsem_arr[i].mutex[j].parent.id = (E_HWSEM_ID)j;
nu_hwsem_arr[i].mutex[j].user_data = (void *)&nu_hwsem_arr[i];
nu_hwsem_arr[i].mutex[j].key = (HWSEM_LOCK_BY_OWNER << 4) | j; // CoreID + SemID
nu_hwsem_arr[i].mutex[j].hold = 0;
nu_hwsem_arr[i].mutex[j].owner = RT_NULL;
if (HWSEM_IS_LOCKED(nu_hwsem_arr[i].base, j) == HWSEM_LOCK_BY_OWNER)
HWSEM_UNLOCK(nu_hwsem_arr[i].base, j, nu_hwsem_arr[i].mutex[j].key);
/* Disable interrupt */
HWSEM_DISABLE_INT(nu_hwsem_arr[i].base, j);
}
rt_hw_interrupt_install(nu_hwsem_arr[i].irqn, nu_hwsem_isr, &nu_hwsem_arr[i], nu_hwsem_arr[i].name);
rt_hw_interrupt_umask(nu_hwsem_arr[i].irqn);
ret = hwsem_register(&nu_hwsem_arr[i].dev, (const char *)nu_hwsem_arr[i].name, (void *)&nu_hwsem_arr[i]);
RT_ASSERT(ret == RT_EOK);
}
return 0;
}
INIT_BOARD_EXPORT(rt_hw_hwsem_init);
#endif //#if defined(BSP_USING_UART)

43
bsp/nuvoton/libraries/ma35/rtt_port/drv_hwsem.h Normal file
View File

@ -0,0 +1,43 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#ifndef __DRV_HWSEM_H__
#define __DRV_HWSEM_H__
#include <rtdevice.h>
typedef enum
{
evHWSEM0 = 0,
evHWSEM1,
evHWSEM2,
evHWSEM3,
evHWSEM4,
evHWSEM5,
evHWSEM6,
evHWSEM7,
evHWSEM_CNT,
} E_HWSEM_ID;
struct nu_mutex
{
E_HWSEM_ID id;
};
typedef struct nu_mutex *nu_mutex_t;
nu_mutex_t nu_mutex_init(struct rt_device *device, E_HWSEM_ID id);
rt_err_t nu_mutex_take(nu_mutex_t mutex, rt_int32_t timeout);
rt_err_t nu_mutex_release(nu_mutex_t mutex);
void nu_mutex_deinit(struct rt_device *device, E_HWSEM_ID id);
#endif /* __DRV_HWSEM_H__ */

109
bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.c
View File

@ -328,22 +328,6 @@ static inline void nu_pdma_channel_reset(int i32ChannID)
while ((PDMA->CHCTL & (1 << u32ModChannId)));
}
void nu_pdma_channel_terminate(int i32ChannID)
{
if (nu_pdma_check_is_nonallocated(i32ChannID))
goto exit_pdma_channel_terminate;
/* Reset specified channel. */
nu_pdma_channel_reset(i32ChannID);
/* Enable specified channel after reset. */
nu_pdma_channel_enable(i32ChannID);
exit_pdma_channel_terminate:
return;
}
static rt_err_t nu_pdma_timeout_set(int i32ChannID, int i32Timeout_us)
{
rt_err_t ret = RT_EINVAL;
@ -396,6 +380,25 @@ exit_nu_pdma_timeout_set:
return -(ret);
}
void nu_pdma_channel_terminate(int i32ChannID)
{
if (nu_pdma_check_is_nonallocated(i32ChannID))
goto exit_pdma_channel_terminate;
/* Disable timeout function of specified channel. */
nu_pdma_timeout_set(i32ChannID, 0);
/* Reset specified channel. */
nu_pdma_channel_reset(i32ChannID);
/* Enable specified channel after reset. */
nu_pdma_channel_enable(i32ChannID);
exit_pdma_channel_terminate:
return;
}
int nu_pdma_channel_allocate(int32_t i32PeripType)
{
int ChnId, i32PeripCtlIdx, j;
@ -595,6 +598,22 @@ exit_nu_pdma_transferred_byte_get:
return -1;
}
nu_pdma_desc_t nu_pdma_get_channel_desc(int32_t i32ChannID)
{
PDMA_T *PDMA;
if (nu_pdma_check_is_nonallocated(i32ChannID))
goto exit_nu_pdma_get_srcaddr;
PDMA = NU_PDMA_GET_BASE(i32ChannID);
return &PDMA->DSCT[NU_PDMA_GET_MOD_CHIDX(i32ChannID)];
exit_nu_pdma_get_srcaddr:
return RT_NULL;
}
nu_pdma_memctrl_t nu_pdma_channel_memctrl_get(int i32ChannID)
{
nu_pdma_memctrl_t eMemCtrl = eMemCtl_Undefined;
@ -727,31 +746,31 @@ exit_nu_pdma_desc_setup:
rt_err_t nu_pdma_sgtbls_allocate(nu_pdma_desc_t *ppsSgtbls, int num)
{
int i;
nu_pdma_desc_t psSgTblHead;
RT_ASSERT(ppsSgtbls != NULL);
RT_ASSERT(num > 0);
psSgTblHead = (nu_pdma_desc_t) rt_malloc_align(RT_ALIGN(sizeof(DSCT_T) * num, 64), 64);
RT_ASSERT(psSgTblHead != RT_NULL);
rt_memset((void *)psSgTblHead, 0, sizeof(DSCT_T) * num);
for (i = 0; i < num; i++)
ppsSgtbls[i] = &psSgTblHead[i];
{
ppsSgtbls[i] = (nu_pdma_desc_t) rt_malloc_align(RT_ALIGN(sizeof(DSCT_T), 64), 64);
RT_ASSERT(ppsSgtbls[i] != RT_NULL);
rt_memset((void *)ppsSgtbls[i], 0, RT_ALIGN(sizeof(DSCT_T), 64));
}
return RT_EOK;
}
void nu_pdma_sgtbls_free(nu_pdma_desc_t *ppsSgtbls, int num)
{
nu_pdma_desc_t psSgTblHead;
int i;
RT_ASSERT(ppsSgtbls != NULL);
psSgTblHead = *ppsSgtbls;
RT_ASSERT(psSgTblHead != NULL);
RT_ASSERT(num > 0);
rt_free_align(psSgTblHead);
for (i = 0; i < num; i++)
{
rt_free_align(ppsSgtbls[i]);
}
}
static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_desc_t head, uint32_t u32IdleTimeout_us)
@ -781,18 +800,20 @@ static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_de
rt_kprintf("[%s] u32SrcCtl=0x%08x\n", __func__, u32SrcCtl);
rt_kprintf("[%s] u32DstCtl=0x%08x\n", __func__, u32DstCtl);
rt_kprintf("[%s] u32FlushLen=%d\n", __func__, u32FlushLen);
rt_kprintf("[%s] DA=%08x\n", __func__, next->DA);
rt_kprintf("[%s] SA=%08x\n", __func__, next->SA);
#endif
/* Flush Src buffer into memory. */
if ((u32SrcCtl == PDMA_SAR_INC)) // for M2P, M2M
rt_hw_cpu_dcache_clean_inv((void *)next->SA, u32FlushLen);
rt_hw_cpu_dcache_clean_and_invalidate((void *)next->SA, u32FlushLen);
/* Flush Dst buffer into memory. */
if ((u32DstCtl == PDMA_DAR_INC)) // for P2M, M2M
rt_hw_cpu_dcache_clean_inv((void *)next->DA, u32FlushLen);
rt_hw_cpu_dcache_clean_and_invalidate((void *)next->DA, u32FlushLen);
/* Flush descriptor into memory */
rt_hw_cpu_dcache_clean_inv((void *)next, sizeof(DSCT_T));
rt_hw_cpu_dcache_clean_and_invalidate((void *)next, sizeof(DSCT_T));
if (bNonCacheAlignedWarning)
{
@ -806,7 +827,7 @@ static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_de
Source, destination, DMA descriptor address and length should be aligned at len(CACHE_LINE_SIZE)
*/
bNonCacheAlignedWarning = 0;
rt_kprintf("[PDMA-W]\n");
//rt_kprintf("[PDMA-W]\n");
}
}
@ -817,19 +838,29 @@ static void _nu_pdma_transfer(int i32ChannID, uint32_t u32Peripheral, nu_pdma_de
}
#endif
nu_pdma_desc_t psDesc = nu_pdma_get_channel_desc(i32ChannID);
PDMA_DisableTimeout(PDMA, 1 << NU_PDMA_GET_MOD_CHIDX(i32ChannID));
PDMA_EnableInt(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID), PDMA_INT_TRANS_DONE);
nu_pdma_timeout_set(i32ChannID, u32IdleTimeout_us);
/* Set scatter-gather mode and head */
/* Take care the head structure, you should make sure cache-coherence. */
PDMA_SetTransferMode(PDMA,
NU_PDMA_GET_MOD_CHIDX(i32ChannID),
u32Peripheral,
(head->NEXT != 0) ? 1 : 0,
(uint32_t)head);
NU_PDMA_GET_MOD_CHIDX(i32ChannID),
u32Peripheral,
(head->NEXT != 0) ? 1 : 0,
(uint32_t)head);
/* PDMA fetchs description on-demand if SG enabled. We check it valid in here. */
if ( (u32Peripheral != PDMA_MEM) &&
(head->NEXT != 0) &&
(head->DA != psDesc->DA) )
{
RT_ASSERT(0);
}
PDMA_EnableInt(PDMA, NU_PDMA_GET_MOD_CHIDX(i32ChannID), PDMA_INT_TRANS_DONE);
nu_pdma_timeout_set(i32ChannID, u32IdleTimeout_us);
/* If peripheral is M2M, trigger it. */
if (u32Peripheral == PDMA_MEM)

1
bsp/nuvoton/libraries/ma35/rtt_port/drv_pdma.h
View File

@ -73,6 +73,7 @@ rt_err_t nu_pdma_channel_memctrl_set(int i32ChannID, nu_pdma_memctrl_t eMemCtrl)
nu_pdma_cb_handler_t nu_pdma_callback_hijack(int i32ChannID, nu_pdma_cbtype_t eCBType, nu_pdma_chn_cb_t psChnCb_Hijack);
rt_err_t nu_pdma_filtering_set(int i32ChannID, uint32_t u32EventFilter);
uint32_t nu_pdma_filtering_get(int i32ChannID);
nu_pdma_desc_t nu_pdma_get_channel_desc(int32_t i32ChannID);
// For scatter-gather DMA
rt_err_t nu_pdma_desc_setup(int i32ChannID, nu_pdma_desc_t dma_desc, uint32_t u32DataWidth, uint32_t u32AddrSrc, uint32_t u32AddrDst, int32_t TransferCnt, nu_pdma_desc_t next, uint32_t u32BeSilent);

2
bsp/nuvoton/libraries/ma35/rtt_port/drv_qspi.c
View File

@ -402,7 +402,7 @@ static int rt_hw_qspi_init(void)
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_qspi_init);
INIT_PREV_EXPORT(rt_hw_qspi_init);
rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
{

28
bsp/nuvoton/libraries/ma35/rtt_port/drv_rtp.c
View File

@ -11,12 +11,11 @@
#include <rtconfig.h>
#if !defined(USE_MA35D1_SUBM)
#if defined(BSP_USING_RTP) && defined(RT_USING_DFS)
#define LOG_TAG "drv.rtp"
#undef DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_LEVEL LOG_LVL_INFO
#define DBG_COLOR
#include <rtdbg.h>
@ -28,17 +27,12 @@
#include <sys/stat.h>
#include <sys/statfs.h>
#define RTP_USING_AT_STARTUP
#include "drv_sspcc.h"
/* Link to rtthread.bin in ma35-rtp folder. */
#define PATH_RTP_INCBIN "..//ma35-rtp//rtthread.bin"
#define READ_BLOCK_SIZE 128
#define REGION_ADDR_SRAM0 0x24000000
#define REGION_ADDR_DDR (0x80020000|UNCACHEABLE)
#define REGION_MAXSIZE_SRAM0 (128*1024)
#define REGION_MAXSIZE_DDR (4*1024*1024-REGION_MAXSIZE_SRAM0)
#define REGION_MAXSIZE_LIMIT (REGION_MAXSIZE_SRAM0+REGION_MAXSIZE_DDR)
#if !defined(PATH_RTP_FW_FILE)
#define PATH_RTP_FW_FILE "/mnt/sd1p0/rtp.bin"
@ -106,7 +100,7 @@ exit_nu_rtp_load_from_memory:
}
#endif
rt_weak void nu_rtp_sspcc_setup(void)
RT_WEAK void nu_rtp_sspcc_setup(void)
{
SSPCC_SET_REALM(SSPCC_UART16, SSPCC_SSET_SUBM);
@ -216,7 +210,7 @@ int nu_rtp_load_run(int argc, char *argv[])
if (!szFilePath || nu_rtp_load_from_file(szFilePath) < 0)
return -1;
rt_kprintf("Loaded %s, then run...\n", szFilePath);
LOG_I("Loaded %s, then run...", szFilePath);
nu_rtp_start();
@ -227,11 +221,11 @@ MSH_CMD_EXPORT(nu_rtp_load_run, load rtp code then run);
int rt_hw_rtp_init(void)
{
int fw_size;
fw_size = (int)((char *)&incbin_rtp_end - (char *)&incbin_rtp_start);
rt_kprintf("INCBIN RTP Start = %p\n", &incbin_rtp_start);
rt_kprintf("INCBIN RTP Size = %p\n", fw_size);
#if defined(RTP_USING_AT_STARTUP)
int fw_size = (int)((char *)&incbin_rtp_end - (char *)&incbin_rtp_start);
LOG_I("INCBIN RTP Start = %p", &incbin_rtp_start);
LOG_I("INCBIN RTP Size = %p", fw_size);
#endif
/* Enable RTP and reset M4 reset */
nu_rtp_init();
@ -247,4 +241,4 @@ int rt_hw_rtp_init(void)
}
INIT_BOARD_EXPORT(rt_hw_rtp_init);
#endif //#if defined(USE_MA35D1_SUBM)
#endif //#if defined(BSP_USING_RTP)

8
bsp/nuvoton/libraries/ma35/rtt_port/drv_sdio.c
View File

@ -59,12 +59,12 @@ typedef struct nu_sdh *nu_sdh_t;
/* Private variables ------------------------------------------------------------*/
#if defined(BSP_USING_SDH0)
rt_align(SDH_ALIGN_LEN)
ALIGN(SDH_ALIGN_LEN)
static uint8_t g_au8CacheBuf_SDH0[SDH_BUFF_SIZE];
#endif
#if defined(BSP_USING_SDH1)
rt_align(SDH_ALIGN_LEN)
ALIGN(SDH_ALIGN_LEN)
static uint8_t g_au8CacheBuf_SDH1[SDH_BUFF_SIZE];
#endif
@ -481,7 +481,7 @@ static void nu_sdh_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
}
}
rt_hw_cpu_dcache_clean_inv((void *)data.dest, size);
rt_hw_cpu_dcache_clean_and_invalidate((void *)data.dest, size);
req->cmd->err = nu_sdh_send_command(sdh->base, &cmd, &data);
rt_hw_cpu_dcache_invalidate((void *)data.dest, size);
@ -766,7 +766,7 @@ void nu_sdh_host_initial(nu_sdh_t sdh)
nu_sdh_irq_update(host, 1);
/* ready to change */
mmcsd_change(host);
//mmcsd_change(host);
}
void nu_sd_attach(void)

29
bsp/nuvoton/libraries/ma35/rtt_port/drv_ssmcc.c Normal file
View File

@ -0,0 +1,29 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#include "rtthread.h"
#if defined(BSP_USING_SSMCC)
#include "drv_common.h"
rt_err_t nu_ssmcc_init(void)
{
CLK->APBCLK2 |= CLK_APBCLK2_SSMCCEN_Msk;
/* set region 0 to secure region, non-secure and m4 all can access */
SSMCC_SetRegion0(SSMCC_SECURE_READ | SSMCC_SECURE_WRITE | SSMCC_NONSECURE_READ | SSMCC_NONSECURE_WRITE | SSMCC_M4NS_READ | SSMCC_M4NS_WRITE);
return RT_EOK;
}
#endif //#if defined(BSP_USING_SSMCC)

18
bsp/nuvoton/libraries/ma35/rtt_port/drv_ssmcc.h Normal file
View File

@ -0,0 +1,18 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#ifndef __DRV_SSMCC_H__
#define __DRV_SSMCC_H__
rt_err_t nu_ssmcc_init(void);
#endif /* __DRV_SSMCC_H__ */

41
bsp/nuvoton/libraries/ma35/rtt_port/drv_sspcc.c Normal file
View File

@ -0,0 +1,41 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#include "rtthread.h"
#if defined(BSP_USING_SSPCC)
#include "drv_common.h"
rt_err_t nu_sspcc_init(void)
{
int i, j;
/* Enable SSPCC clock. */
CLK->APBCLK2 |= CLK_APBCLK2_SSPCCEN_Msk;
/* Assign all SRAM1 capacity to TZNS. */
SSPCC->SRAMSB = 0;
/* Set all GPIO security set to TZNS. */
for (i = 0; i < 16; i++)
{
for (j = 0; j < 14; j++)
{
SSPCC_SetRealm_GPIO(GPIO_BASE + (j * 0x40), i, SSPCC_SSET_TZNS);
}
}
return RT_EOK;
}
#endif //#if defined(BSP_USING_SSPCC)

34
bsp/nuvoton/libraries/ma35/rtt_port/drv_sspcc.h Normal file
View File

@ -0,0 +1,34 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#ifndef __DRV_SSPCC_H__
#define __DRV_SSPCC_H__
#include "rtthread.h"
#define SSPCC_SET_REALM(IP, REALM) \
do { \
rt_kprintf("Set %s realm to %s(%d)\n", #IP, #REALM, REALM); \
SSPCC_SetRealm(IP, REALM); \
rt_kprintf("Get %s realm is %d ....%s\n", #IP, SSPCC_GetRealm(IP), (SSPCC_GetRealm(IP)==REALM)?"Success":"Failure"); \
} while(0)
#define SSPCC_SET_GPIO_REALM(PORT, PIN, REALM) \
do { \
rt_kprintf("Set %s%s realm to %s(%d)\n", #PORT, #PIN, #REALM, REALM); \
SSPCC_SetRealm_GPIO((uint32_t)PORT, PIN, REALM); \
rt_kprintf("Get %s%s realm is %d ....%s\n", #PORT, #PIN, SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN), (SSPCC_GetRealm_GPIO((uint32_t)PORT, PIN)==REALM)?"Success":"Failure"); \
} while(0)
rt_err_t nu_sspcc_init(void);
#endif /* __DRV_SSPCC_H__ */

167
bsp/nuvoton/libraries/ma35/rtt_port/drv_sys.c
View File

@ -15,6 +15,13 @@
#include "drv_sys.h"
#include <stdio.h>
#define LOG_TAG "drv.sys"
#undef DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL LOG_LVL_DBG
#define DBG_COLOR
#include <rtdbg.h>
#define DEF_RAISING_CPU_FREQUENCY
//Dont enable #define DEF_RAISING_CPU_VOLTAGE
@ -80,14 +87,14 @@ void nu_sys_check_register(S_NU_REG *psNuReg)
{
vu32 vc32RegValue = *((vu32 *)psNuReg->vu32RegAddr);
vu32 vc32BMValue = vc32RegValue & psNuReg->vu32BitMask;
rt_kprintf("[%3s] %32s(0x%08x) %24s(0x%08x): 0x%08x(AndBitMask:0x%08x)\n",
(psNuReg->vu32Value == vc32BMValue) ? "Ok" : "!OK",
psNuReg->szVName,
psNuReg->vu32Value,
psNuReg->szRegName,
psNuReg->vu32RegAddr,
vc32RegValue,
vc32BMValue);
LOG_I("[%3s] %32s(0x%08x) %24s(0x%08x): 0x%08x(AndBitMask:0x%08x)\n",
(psNuReg->vu32Value == vc32BMValue) ? "Ok" : "!OK",
psNuReg->szVName,
psNuReg->vu32Value,
psNuReg->szRegName,
psNuReg->vu32RegAddr,
vc32RegValue,
vc32BMValue);
psNuReg++;
}
}
@ -122,7 +129,7 @@ static int nu_tempsen_get_value()
count = 0;
temp = (double)((SYS->TSENSRFCR & 0x0FFF0000) >> 16) * 274.3531 / 4096.0 - 93.3332;
snprintf(sztmp, sizeof(sztmp), "Temperature: %.1f\n", temp);
rt_kprintf("%s", sztmp);
LOG_I("%s", sztmp);
}
// Clear Valid bit
@ -142,7 +149,7 @@ static int nu_tempsen_go(void)
if (err != RT_EOK)
{
rt_kprintf("set %s idle hook failed!\n", __func__);
LOG_E("set %s idle hook failed!\n", __func__);
return -1;
}
@ -153,32 +160,51 @@ static int nu_tempsen_go(void)
//INIT_APP_EXPORT(nu_tempsen_go);
MSH_CMD_EXPORT(nu_tempsen_go, go tempsen);
void nu_clock_dump(void)
#define REG_SYS_CHIPCFG (SYS_BASE + 0x1F4)
uint32_t nu_chipcfg_ddrsize(void)
{
rt_kprintf("HXT: %d Hz\n", CLK_GetHXTFreq());
rt_kprintf("LXT: %d Hz\n", CLK_GetLXTFreq());
rt_kprintf("CAPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(CAPLL), CLK_GetPLLOpMode(CAPLL));
rt_kprintf("DDRPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(DDRPLL), CLK_GetPLLOpMode(DDRPLL));
rt_kprintf("APLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(APLL), CLK_GetPLLOpMode(APLL));
rt_kprintf("EPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(EPLL), CLK_GetPLLOpMode(EPLL));
rt_kprintf("VPLL: %d Hz(OpMode=%d)\n", CLK_GetPLLClockFreq(VPLL), CLK_GetPLLOpMode(VPLL));
uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG);
rt_kprintf("M4-CPU: %d Hz\n", CLK_GetCPUFreq());
rt_kprintf("SYSCLK0: %d Hz\n", CLK_GetSYSCLK0Freq());
rt_kprintf("SYSCLK1: %d Hz\n", CLK_GetSYSCLK1Freq());
rt_kprintf("HCLK0: %d Hz\n", CLK_GetHCLK0Freq());
rt_kprintf("HCLK1: %d Hz\n", CLK_GetHCLK1Freq());
rt_kprintf("HCLK2: %d Hz\n", CLK_GetHCLK2Freq());
rt_kprintf("HCLK3: %d Hz\n", CLK_GetHCLK3Freq());
rt_kprintf("PCLK0: %d Hz\n", CLK_GetPCLK0Freq());
rt_kprintf("PCLK1: %d Hz\n", CLK_GetPCLK1Freq());
rt_kprintf("PCLK2: %d Hz\n", CLK_GetPCLK2Freq());
rt_kprintf("PCLK3: %d Hz\n", CLK_GetPCLK3Freq());
rt_kprintf("PCLK4: %d Hz\n", CLK_GetPCLK4Freq());
return ((u32ChipCfg & 0xF0000) != 0) ? (1 << ((u32ChipCfg & 0xF0000) >> 16)) << 20 : 0;
}
const char *szClockName [] =
void nu_chipcfg_dump(void)
{
uint32_t u32ChipCfg = *((vu32 *)REG_SYS_CHIPCFG);
uint32_t u32ChipCfg_DDRSize = ((u32ChipCfg & 0xF0000) != 0) ? 1 << ((u32ChipCfg & 0xF0000) >> 16) : 0;
uint32_t u32ChipCfg_DDRType = ((u32ChipCfg & 0x8000) >> 15);
LOG_I("CHIPCFG: 0x%08x ", u32ChipCfg);
LOG_I("DDR SDRAM Size: %d MB", u32ChipCfg_DDRSize);
LOG_I("MCP DDR TYPE: %s", u32ChipCfg_DDRSize ? (u32ChipCfg_DDRType ? "DDR2" : "DDR3/3L") : "Unknown");
}
void nu_clock_dump(void)
{
LOG_I("HXT: %d Hz", CLK_GetHXTFreq());
LOG_I("LXT: %d Hz", CLK_GetLXTFreq());
LOG_I("CAPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(CAPLL), CLK_GetPLLOpMode(CAPLL));
LOG_I("DDRPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(DDRPLL), CLK_GetPLLOpMode(DDRPLL));
LOG_I("APLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(APLL), CLK_GetPLLOpMode(APLL));
LOG_I("EPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(EPLL), CLK_GetPLLOpMode(EPLL));
LOG_I("VPLL: %d Hz(OpMode=%d)", CLK_GetPLLClockFreq(VPLL), CLK_GetPLLOpMode(VPLL));
LOG_I("M4-CPU: %d Hz", CLK_GetCPUFreq());
LOG_I("SYSCLK0: %d Hz", CLK_GetSYSCLK0Freq());
LOG_I("SYSCLK1: %d Hz", CLK_GetSYSCLK1Freq());
LOG_I("HCLK0: %d Hz", CLK_GetHCLK0Freq());
LOG_I("HCLK1: %d Hz", CLK_GetHCLK1Freq());
LOG_I("HCLK2: %d Hz", CLK_GetHCLK2Freq());
LOG_I("HCLK3: %d Hz", CLK_GetHCLK3Freq());
LOG_I("PCLK0: %d Hz", CLK_GetPCLK0Freq());
LOG_I("PCLK1: %d Hz", CLK_GetPCLK1Freq());
LOG_I("PCLK2: %d Hz", CLK_GetPCLK2Freq());
LOG_I("PCLK3: %d Hz", CLK_GetPCLK3Freq());
LOG_I("PCLK4: %d Hz", CLK_GetPCLK4Freq());
}
static const char *szClockName [] =
{
"HXT",
"LXT",
@ -202,7 +228,7 @@ void nu_clock_isready(void)
{
if (i == 5 || i == 7 || i == 2) continue;
u32IsReady = CLK_WaitClockReady(1 << i);
rt_kprintf("%s: %s\n", szClockName[i], (u32IsReady == 1) ? "[Stable]" : "[Unstable]");
LOG_I("%s: %s\n", szClockName[i], (u32IsReady == 1) ? "[Stable]" : "[Unstable]");
}
}
@ -230,7 +256,7 @@ void nu_clock_raise(void)
}
CLK_SetPLLFreq(VPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 102000000ul);
CLK_SetPLLFreq(APLL, PLL_OPMODE_INTEGER, u32PllRefClk, 160000000ul);
CLK_SetPLLFreq(APLL, PLL_OPMODE_INTEGER, u32PllRefClk, 144000000ul);
CLK_SetPLLFreq(EPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 500000000ul);
/* Waiting clock ready */
@ -247,7 +273,9 @@ void nu_clock_raise(void)
else
#endif
{
#if defined(DEF_RAISING_CPU_VOLTAGE)
ma35d1_set_cpu_voltage(CLK_GetPLLClockFreq(SYSPLL), 0x5F);
#endif
CLK_SetPLLFreq(CAPLL, PLL_OPMODE_INTEGER, u32PllRefClk, 800000000ul);
}
@ -267,3 +295,74 @@ void nu_clock_raise(void)
#endif
void devmem(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, mode = 0;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "0x%x", &value) != 1)
goto exit_devmem;
mode = 1; //Write
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (mode)
{
*((volatile uint32_t *)u32Addr) = value;
}
LOG_I("0x%08x\n", *((volatile uint32_t *)u32Addr));
return;
exit_devmem:
rt_kprintf("Read: devmem <physical address in hex>\n");
rt_kprintf("Write: devmem <physical address in hex> <value in hex format>\n");
return;
}
MSH_CMD_EXPORT(devmem, dump device registers);
void devmem2(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, word_count = 1;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "%d", &value) != 1)
goto exit_devmem;
word_count = value;
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (word_count > 0)
{
LOG_HEX("devmem", 16, (void *)u32Addr, word_count * sizeof(rt_base_t));
}
return;
exit_devmem:
rt_kprintf("devmem2: <physical address in hex> <count in dec>\n");
return;
}
MSH_CMD_EXPORT(devmem2, dump device registers);

519
bsp/nuvoton/libraries/ma35/rtt_port/drv_uart.c
View File

File diff suppressed because it is too large Load Diff

34
bsp/nuvoton/libraries/ma35/rtt_port/drv_umctl2.c Normal file
View File

@ -0,0 +1,34 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#include "rtthread.h"
#if defined(BSP_USING_UMCTL2)
#include "drv_common.h"
rt_err_t nu_umctl2_init(void)
{
UMCTL2->PCTRL_0 = UMCTL2_PCTRL_0_port_en_Msk; //[0x0490]
UMCTL2->PCTRL_1 = UMCTL2_PCTRL_1_port_en_Msk; //[0x0540]
UMCTL2->PCTRL_2 = UMCTL2_PCTRL_2_port_en_Msk; //[0x05f0]
UMCTL2->PCTRL_3 = UMCTL2_PCTRL_3_port_en_Msk; //[0x06a0]
UMCTL2->PCTRL_4 = UMCTL2_PCTRL_4_port_en_Msk; //[0x0750]
UMCTL2->PCTRL_5 = UMCTL2_PCTRL_5_port_en_Msk; //[0x0800]
UMCTL2->PCTRL_6 = UMCTL2_PCTRL_6_port_en_Msk; //[0x08b0]
UMCTL2->PCTRL_7 = UMCTL2_PCTRL_7_port_en_Msk; //[0x0960]
return RT_EOK;
}
#endif //#if defined(BSP_USING_UMCTL2)

18
bsp/nuvoton/libraries/ma35/rtt_port/drv_umctl2.h Normal file
View File

@ -0,0 +1,18 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-20 Wayne First version
*
******************************************************************************/
#ifndef __DRV_UMCTL2_H__
#define __DRV_UMCTL2_H__
rt_err_t nu_umctl2_init(void);
#endif /* __DRV_UMCTL2_H__*/

2
bsp/nuvoton/libraries/ma35/rtt_port/drv_usbhost.c
View File

@ -517,7 +517,7 @@ static int nu_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes
if ((pipe->ep.bEndpointAddress & USB_DIR_MASK) == USB_DIR_OUT)
{
rt_memcpy(buffer_nonch, buffer, nbytes);
rt_hw_cpu_dcache_clean_inv((void *)buffer_nonch, nbytes);
rt_hw_cpu_dcache_clean_and_invalidate((void *)buffer_nonch, nbytes);
}
}

268
bsp/nuvoton/libraries/ma35/rtt_port/drv_whc.c Normal file
View File

@ -0,0 +1,268 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#include <rtconfig.h>
#if defined(BSP_USING_WHC)
#include <rthw.h>
#include "drv_whc.h"
#include "drv_sys.h"
#include "nu_bitutil.h"
/* Private define ---------------------------------------------------------------*/
enum
{
WHC_START = -1,
#if defined(BSP_USING_WHC0)
WHC0_IDX,
#endif
#if defined(BSP_USING_WHC1)
WHC1_IDX,
#endif
WHC_CNT
};
/* Private typedef --------------------------------------------------------------*/
struct nu_whc_priv
{
char *name;
WHC_T *base;
IRQn_Type irqn;
uint32_t rstidx;
rt_device_t psChDev[WHC_CH];
};
typedef struct nu_whc_priv *nu_whc_priv_t;
struct nu_whc
{
struct rt_device dev;
nu_whc_priv_t psPriv;
uint32_t u32WhcChNum;
void *pvTxBuf;
};
typedef struct nu_whc *nu_whc_t;
static struct nu_whc_priv nu_whc_priv_arr [] =
{
#if defined(BSP_USING_WHC0)
{
.name = "whc0",
.base = WHC0,
.irqn = WHC0_IRQn,
.rstidx = WHC0_RST,
},
#endif
#if defined(BSP_USING_WHC1)
{
.name = "whc1",
.base = WHC1,
.irqn = WHC1_IRQn,
.rstidx = WHC1_RST,
},
#endif
}; /* nu_whc_priv */
/**
* All WHC interrupt service routine
*/
static void nu_whc_isr(int vector, void *param)
{
nu_whc_priv_t psNuWhcPriv = (nu_whc_priv_t)param;
volatile uint32_t vu32Intsts = psNuWhcPriv->base->INTSTS;
uint32_t irqidx;
while ((irqidx = nu_ctz(vu32Intsts)) != 32)
{
uint32_t u32IsrBitMask = 1 << irqidx ;
switch (irqidx)
{
/* Process TX-complete interrupt event */
case WHC_INTSTS_TX0IF_Pos:
case WHC_INTSTS_TX1IF_Pos:
case WHC_INTSTS_TX2IF_Pos:
case WHC_INTSTS_TX3IF_Pos:
{
uint32_t u32ChNum = irqidx - WHC_INTSTS_TX0IF_Pos;
rt_device_t device = psNuWhcPriv->psChDev[u32ChNum];
nu_whc_t psWhc = (nu_whc_t)device;
if (device->tx_complete && psWhc->pvTxBuf)
{
device->tx_complete(device, psWhc->pvTxBuf);
psWhc->pvTxBuf = RT_NULL;
}
}
break;
/* Process RX-indicate interrupt event */
case WHC_INTSTS_RX0IF_Pos:
case WHC_INTSTS_RX1IF_Pos:
case WHC_INTSTS_RX2IF_Pos:
case WHC_INTSTS_RX3IF_Pos:
{
uint32_t u32ChNum = irqidx - WHC_INTSTS_RX0IF_Pos;
rt_device_t device = psNuWhcPriv->psChDev[u32ChNum];
if (device->rx_indicate)
{
device->rx_indicate(device, 1);
}
}
break;
default:
break;
}
/* Clear interrupt bit. */
WHC_CLR_INT_FLAG(psNuWhcPriv->base, u32IsrBitMask);
/* Clear served bit */
vu32Intsts &= ~(u32IsrBitMask);
}
}
rt_err_t nu_whc_init(rt_device_t dev)
{
return RT_EOK;
}
rt_err_t nu_whc_open(rt_device_t dev, rt_uint16_t oflag)
{
nu_whc_t psWhc = (nu_whc_t)dev;
nu_whc_priv_t psWhcPriv = psWhc->psPriv;
WHC_ENABLE_INT(psWhcPriv->base, WHC_INTEN_TX0IEN_Msk << psWhc->u32WhcChNum |
WHC_INTEN_RX0IEN_Msk << psWhc->u32WhcChNum);
return RT_EOK;
}
rt_err_t nu_whc_close(rt_device_t dev)
{
nu_whc_t psWhc = (nu_whc_t)dev;
nu_whc_priv_t psWhcPriv = psWhc->psPriv;
WHC_DISABLE_INT(psWhcPriv->base, WHC_INTEN_TX0IEN_Msk << psWhc->u32WhcChNum |
WHC_INTEN_RX0IEN_Msk << psWhc->u32WhcChNum);
return RT_EOK;
}
rt_size_t nu_whc_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
{
nu_whc_t psWhc = (nu_whc_t)dev;
nu_whc_priv_t psWhcPriv = psWhc->psPriv;
if ((sizeof(nu_whc_msg) != size) || ((uint32_t)buffer & 0x3))
goto exit_nu_whc_read;
if (WHC_Recv(psWhcPriv->base, psWhc->u32WhcChNum, (uint32_t *)buffer) < 0)
goto exit_nu_whc_read;
return size;
exit_nu_whc_read:
return 0;
}
rt_size_t nu_whc_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
{
nu_whc_t psWhc = (nu_whc_t)dev;
nu_whc_priv_t psWhcPriv = psWhc->psPriv;
if ((sizeof(nu_whc_msg) != size) || ((uint32_t)buffer & 0x3))
goto exit_nu_whc_write;
psWhc->pvTxBuf = (void *)buffer;
if (WHC_Send(psWhcPriv->base, psWhc->u32WhcChNum, (uint32_t *)buffer) < 0)
goto exit_nu_whc_write;
return size;
exit_nu_whc_write:
return 0;
}
rt_err_t nu_whc_control(rt_device_t dev, int cmd, void *args)
{
return RT_EOK;
}
static rt_err_t whc_register(nu_whc_priv_t psWhcPriv)
{
int i;
char szDevName[16];
for (i = 0; i < WHC_CH; i++)
{
nu_whc_t psWhc;
rt_device_t device = rt_device_create(RT_Device_Class_Miscellaneous, sizeof(struct nu_whc) - sizeof(struct rt_device));
RT_ASSERT(device);
psWhcPriv->psChDev[i] = device;
psWhc = (nu_whc_t)device;
psWhc->psPriv = psWhcPriv;
psWhc->u32WhcChNum = i;
device->type = RT_Device_Class_Miscellaneous;
device->rx_indicate = RT_NULL;
device->tx_complete = RT_NULL;
#ifdef RT_USING_DEVICE_OPS
device->ops = RT_NULL;
#else
device->init = nu_whc_init;
device->open = nu_whc_open;
device->close = nu_whc_close;
device->read = nu_whc_read;
device->write = nu_whc_write;
device->control = nu_whc_control;
#endif
device->user_data = (void *)psWhcPriv;
rt_snprintf(szDevName, sizeof(szDevName), "%s-%d", psWhcPriv->name, psWhc->u32WhcChNum);
RT_ASSERT(rt_device_register(device, szDevName, RT_DEVICE_FLAG_STANDALONE) == RT_EOK);
}
return RT_EOK;
}
/**
* Hardware Sem Initialization
*/
int rt_hw_whc_init(void)
{
int i;
for (i = (WHC_START + 1); i < WHC_CNT; i++)
{
nu_whc_priv_t psNuWhcPriv = &nu_whc_priv_arr[i];
whc_register(psNuWhcPriv);
rt_hw_interrupt_install(psNuWhcPriv->irqn, nu_whc_isr, psNuWhcPriv, psNuWhcPriv->name);
rt_hw_interrupt_umask(nu_whc_priv_arr[i].irqn);
}
return 0;
}
INIT_BOARD_EXPORT(rt_hw_whc_init);
#endif //#if defined(BSP_USING_WHC)

24
bsp/nuvoton/libraries/ma35/rtt_port/drv_whc.h Normal file
View File

@ -0,0 +1,24 @@
/**************************************************************************//**
*
* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#ifndef __DRV_WHC_H__
#define __DRV_WHC_H__
#include "drv_common.h"
typedef struct
{
uint32_t content[WHC_BUFFER_LEN];
} nu_whc_msg;
typedef nu_whc_msg *nu_whc_msg_t;
#endif /* __DRV_WHC_H__ */

23
bsp/nuvoton/libraries/ma35/rtt_port/nu_clock_init.c
View File

@ -191,11 +191,11 @@ static void nu_clock_i2s_init(void)
{
#if defined(BSP_USING_I2S0)
CLK_EnableModuleClock(I2S0_MODULE);
CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL4_I2S0SEL_SYSCLK1_DIV2, MODULE_NoMsk);
CLK_SetModuleClock(I2S0_MODULE, CLK_CLKSEL4_I2S0SEL_APLL, MODULE_NoMsk);
#endif
#if defined(BSP_USING_I2S1)
CLK_EnableModuleClock(I2S1_MODULE);
CLK_SetModuleClock(I2S1_MODULE, CLK_CLKSEL4_I2S1SEL_SYSCLK1_DIV2, MODULE_NoMsk);
CLK_SetModuleClock(I2S1_MODULE, CLK_CLKSEL4_I2S1SEL_APLL, MODULE_NoMsk);
#endif
}
@ -365,6 +365,23 @@ void nu_clock_base_init(void)
}
#endif
static void nu_clock_hwsem_init(void)
{
#if defined(BSP_USING_HWSEM0)
CLK_EnableModuleClock(HWSEM0_MODULE);
#endif
}
static void nu_clock_whc_init(void)
{
#if defined(BSP_USING_WHC0)
CLK_EnableModuleClock(WHC0_MODULE);
#endif
#if defined(BSP_USING_WHC1)
CLK_EnableModuleClock(WHC1_MODULE);
#endif
}
void nu_clock_init(void)
{
#if !defined(USE_MA35D1_SUBM)
@ -377,6 +394,8 @@ void nu_clock_init(void)
nu_clock_disp_init();
#endif
nu_clock_whc_init();
nu_clock_hwsem_init();
nu_clock_pdma_init();
nu_clock_gpio_init();
nu_clock_uart_init();

1
bsp/nuvoton/libraries/n9h30/rtt_port/Kconfig
View File

@ -12,6 +12,7 @@ config SOC_SERIES_N9H30
config BSP_USING_MMU
bool "Enable MMU"
select ARCH_ARM_MMU
default y
config BSP_USING_GPIO

10
bsp/nuvoton/libraries/nu_packages/AudioCodec/acodec_nau8822.c
View File

@ -370,9 +370,13 @@ static rt_err_t nau8822_mixer_control(rt_uint32_t ui32Units, rt_uint32_t ui32Val
break;
case AUDIO_MIXER_VOLUME:
{
uint8_t u8DACGAIN = 256 * ui32Value / 100;
I2C_WriteNAU8822(11, u8DACGAIN);
I2C_WriteNAU8822(12, u8DACGAIN);
uint8_t u8GAIN = 256 * ui32Value / 100;
I2C_WriteNAU8822(11, 0x100 | u8GAIN);
I2C_WriteNAU8822(12, 0x100 | u8GAIN);
u8GAIN = 0x3F * ui32Value / 100;
I2C_WriteNAU8822(54, 0x100 | u8GAIN);
I2C_WriteNAU8822(55, 0x100 | u8GAIN);
}
break;
case AUDIO_MIXER_QUERY:

2
bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMG160_driver/bmg160.h
View File

@ -1570,7 +1570,7 @@ FOR THE AUTO OFFSET INTERRUPT */
/***********************************************/
/**\name NUMERIC DEFINITIONS*/
/**********************************************/
#define BMG160_INIT_VALUE ((u8)0)
#define BMG160_INIT_VALUE (0)
#define BMG160_GEN_READ_WRITE_DATA_LENGTH ((u8)1)
#define BMG160_X_DATA_LENGTH ((u8)2)
#define BMG160_Y_DATA_LENGTH ((u8)2)

2
bsp/nuvoton/libraries/nu_packages/BMX055/libraries/BMM050_driver/bmm050.h
View File

@ -709,7 +709,7 @@ delay_func(delay_in_msec)
#define E_BMM050_NULL_PTR ((s8)-127)
#define ERROR ((s8)-1)
#define E_BMM050_OUT_OF_RANGE ((s8)-2)
#define BMM050_NULL ((u8)0)
#define BMM050_NULL (0)
#define E_BMM050_UNDEFINED_MODE (0)
/********************************************/

107
bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.c
View File

@ -248,14 +248,15 @@ static double get_mdps_value(int32_t i32AccelVal)
return 0.0f;
}
static rt_size_t bmx055_fetch_data(rt_sensor_t sensor, void *buf, rt_size_t len)
static rt_ssize_t bmx055_fetch_data(rt_sensor_t sensor, rt_sensor_data_t data, rt_size_t len)
{
struct rt_sensor_data *data = (struct rt_sensor_data *)buf;
RT_ASSERT(data);
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
bma2x2_read_accel_xyzt(&g_sbmx055.accel_xyzt);
data->type = RT_SENSOR_CLASS_ACCE;
data->type = RT_SENSOR_TYPE_ACCE;
/* Report mg */
data->data.acce.x = (int32_t)get_mg_value(g_sbmx055.accel_xyzt.x);
@ -263,9 +264,9 @@ static rt_size_t bmx055_fetch_data(rt_sensor_t sensor, void *buf, rt_size_t len)
data->data.acce.z = (int32_t)get_mg_value(g_sbmx055.accel_xyzt.z);
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
bmg160_get_data_XYZI(&g_sbmx055.gyro_xyzi);
data->type = RT_SENSOR_CLASS_GYRO;
data->type = RT_SENSOR_TYPE_GYRO;
/* Report mdps */
data->data.gyro.x = (int32_t)get_mdps_value(g_sbmx055.gyro_xyzi.datax);
@ -273,9 +274,9 @@ static rt_size_t bmx055_fetch_data(rt_sensor_t sensor, void *buf, rt_size_t len)
data->data.gyro.z = (int32_t)get_mdps_value(g_sbmx055.gyro_xyzi.dataz);
break;
case RT_SENSOR_CLASS_MAG:
case RT_SENSOR_TYPE_MAG:
bmm050_read_mag_data_XYZ(&g_sbmx055.mag_data);
data->type = RT_SENSOR_CLASS_MAG;
data->type = RT_SENSOR_TYPE_MAG;
/* Report mquass */
data->data.mag.x = g_sbmx055.mag_data.datax;
@ -307,15 +308,15 @@ static rt_err_t bmx055_getid(rt_sensor_t sensor, rt_uint8_t *pu8)
{
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
*pu8 = g_sbmx055.accel.chip_id;
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
*pu8 = g_sbmx055.gyro.chip_id;
break;
case RT_SENSOR_CLASS_MAG:
case RT_SENSOR_TYPE_MAG:
*pu8 = g_sbmx055.mag.company_id;
break;
}
@ -329,19 +330,19 @@ static rt_err_t bmx055_set_power(rt_sensor_t sensor, rt_uint8_t power_mode)
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
{
switch (power_mode)
{
case RT_SENSOR_POWER_DOWN:
case RT_SENSOR_MODE_POWER_DOWN:
power_ctr = BMA2x2_MODE_STANDBY;
break;
case RT_SENSOR_POWER_NORMAL:
case RT_SENSOR_MODE_POWER_MEDIUM:
power_ctr = BMA2x2_MODE_NORMAL;
break;
case RT_SENSOR_POWER_LOW:
case RT_SENSOR_MODE_POWER_LOW:
power_ctr = BMA2x2_MODE_LOWPOWER1;
break;
@ -355,15 +356,15 @@ static rt_err_t bmx055_set_power(rt_sensor_t sensor, rt_uint8_t power_mode)
}
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
{
switch (power_mode)
{
case RT_SENSOR_POWER_DOWN:
case RT_SENSOR_MODE_POWER_DOWN:
power_ctr = BMG160_MODE_DEEPSUSPEND;
break;
case RT_SENSOR_POWER_NORMAL:
case RT_SENSOR_MODE_POWER_MEDIUM:
power_ctr = BMG160_MODE_NORMAL;
break;
@ -377,15 +378,15 @@ static rt_err_t bmx055_set_power(rt_sensor_t sensor, rt_uint8_t power_mode)
}
break;
case RT_SENSOR_CLASS_MAG:
case RT_SENSOR_TYPE_MAG:
{
switch (power_mode)
{
case RT_SENSOR_POWER_DOWN:
case RT_SENSOR_MODE_POWER_DOWN:
power_ctr = 0;
break;
case RT_SENSOR_POWER_NORMAL:
case RT_SENSOR_MODE_POWER_MEDIUM:
power_ctr = 1;
break;
@ -412,7 +413,7 @@ static rt_err_t bmx055_set_range(rt_sensor_t sensor, rt_uint16_t range)
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
{
idx = find_param_index(range, accel_ranges, sizeof(accel_ranges));
if (bma2x2_set_range(accel_ranges[idx].reg) != 0)
@ -422,7 +423,7 @@ static rt_err_t bmx055_set_range(rt_sensor_t sensor, rt_uint16_t range)
}
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
{
idx = find_param_index(range, gyro_ranges, sizeof(gyro_ranges));
if (bmg160_set_range_reg(gyro_ranges[idx].reg) != 0)
@ -446,7 +447,7 @@ static rt_err_t bmx055_set_odr(rt_sensor_t sensor, rt_uint16_t odr_hz)
int idx;
switch (sensor->info.type)
{
case RT_SENSOR_CLASS_ACCE:
case RT_SENSOR_TYPE_ACCE:
{
idx = find_param_index(odr_hz, accel_odr, sizeof(accel_odr));
if (bma2x2_set_bw(accel_odr[idx].reg) != 0)
@ -454,7 +455,7 @@ static rt_err_t bmx055_set_odr(rt_sensor_t sensor, rt_uint16_t odr_hz)
}
break;
case RT_SENSOR_CLASS_GYRO:
case RT_SENSOR_TYPE_GYRO:
{
idx = find_param_index(odr_hz, gyro_odr, sizeof(gyro_odr));
if (bmg160_set_bw(gyro_odr[idx].reg) != 0)
@ -462,7 +463,7 @@ static rt_err_t bmx055_set_odr(rt_sensor_t sensor, rt_uint16_t odr_hz)
}
break;
case RT_SENSOR_CLASS_MAG:
case RT_SENSOR_TYPE_MAG:
{
idx = find_param_index(odr_hz, mag_odr, sizeof(mag_odr));
if (bmm050_set_data_rate(mag_odr[idx].reg) != 0)
@ -483,8 +484,8 @@ exit_bmx055_set_power:
static rt_err_t bmx055_control(rt_sensor_t sensor, int cmd, void *args)
{
RT_ASSERT(sensor != RT_NULL);
RT_ASSERT(args != RT_NULL);
RT_ASSERT(sensor);
RT_ASSERT(args);
switch (cmd)
{
@ -496,7 +497,7 @@ static rt_err_t bmx055_control(rt_sensor_t sensor, int cmd, void *args)
case RT_SENSOR_CTRL_SET_RANGE:
return bmx055_set_range(sensor, (rt_uint32_t)args);
case RT_SENSOR_CTRL_SET_POWER:
case RT_SENSOR_CTRL_SET_POWER_MODE:
return bmx055_set_power(sensor, ((rt_uint32_t)args & 0xff));
case RT_SENSOR_CTRL_SET_ODR:
@ -521,14 +522,14 @@ static int rt_hw_bmx055_accel_init(const char *name, struct rt_sensor_config *cf
if (sensor == RT_NULL)
return -(RT_ENOMEM);
sensor->info.type = RT_SENSOR_CLASS_ACCE;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.model = "bmx055_acce";
sensor->info.unit = RT_SENSOR_UNIT_MG;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.range_max = 16000;
sensor->info.range_min = 2000;
sensor->info.period_min = 100;
sensor->info.type = RT_SENSOR_TYPE_ACCE;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.name = "bmx055_acce";
sensor->info.unit = RT_SENSOR_UNIT_MG;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.scale.range_max = 16000;
sensor->info.scale.range_min = 2000;
sensor->info.acquire_min = 100;
rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config));
sensor->ops = &sensor_ops;
@ -552,14 +553,14 @@ static int rt_hw_bmx055_gyro_init(const char *name, struct rt_sensor_config *cfg
if (sensor == RT_NULL)
return -(RT_ENOMEM);
sensor->info.type = RT_SENSOR_CLASS_GYRO;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.model = "bmx055_gyro";
sensor->info.unit = RT_SENSOR_UNIT_MDPS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.range_max = 2000;
sensor->info.range_min = 125;
sensor->info.period_min = 100;
sensor->info.type = RT_SENSOR_TYPE_GYRO;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.name = "bmx055_gyro";
sensor->info.unit = RT_SENSOR_UNIT_MDPS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.scale.range_max = 2000;
sensor->info.scale.range_min = 125;
sensor->info.acquire_min = 100;
rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config));
sensor->ops = &sensor_ops;
@ -583,14 +584,14 @@ static int rt_hw_bmx055_mag_init(const char *name, struct rt_sensor_config *cfg)
if (sensor == RT_NULL)
return -(RT_ENOMEM);
sensor->info.type = RT_SENSOR_CLASS_MAG;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.model = "bmx055_mag";
sensor->info.unit = RT_SENSOR_UNIT_MGAUSS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.range_max = 25000; // 1uT = 10*mGauss, X/Y: 1300uT=13000mGauss, Z: 2500uT=25000mG
sensor->info.range_min = 0;
sensor->info.period_min = 100;
sensor->info.type = RT_SENSOR_TYPE_MAG;
sensor->info.vendor = RT_SENSOR_VENDOR_BOSCH;
sensor->info.name = "bmx055_mag";
sensor->info.unit = RT_SENSOR_UNIT_MGAUSS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.scale.range_max = 25000; // 1uT = 10*mGauss, X/Y: 1300uT=13000mGauss, Z: 2500uT=25000mG
sensor->info.scale.range_min = 0;
sensor->info.acquire_min = 100;
rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config));
sensor->ops = &sensor_ops;

3
bsp/nuvoton/libraries/nu_packages/BMX055/sensor_bmx055.h
View File

@ -13,7 +13,8 @@
#ifndef __SENSOR_BMX055_H__
#define __SENSOR_BMX055_H__
#include "sensor.h"
#include "rtdevice.h"
#include "bma2x2.h"
#include "bmm050.h"
#include "bmg160.h"

8
bsp/nuvoton/libraries/nu_packages/Demo/SConscript
View File

@ -1,13 +1,9 @@
Import('RTT_ROOT')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c') + Glob('*.cpp')
CPPPATH = [cwd]
src = Split("""
usbd_hid_dance_mouse.c
slcd_show_tick.c
usbd_cdc_vcom_echo.c
atdev_utils.c
""")
group = DefineGroup('nu_pkgs_demo', src, depend = ['NU_PKG_USING_DEMO'], CPPPATH = CPPPATH)
Return('group')

9
bsp/nuvoton/libraries/nu_packages/CCAP_Sensors/ccap_demo.c → bsp/nuvoton/libraries/nu_packages/Demo/ccap_demo.c
View File

@ -12,6 +12,8 @@
#include <rtthread.h>
#if defined(BSP_USING_CCAP)
#include "drv_ccap.h"
#include <dfs_posix.h>
@ -504,7 +506,9 @@ static void ccap_grabber(void *parameter)
exit_ccap_grabber:
ccap_sensor_fini(rt_device_find(psGrabberParam->devname_ccap), rt_device_find(psGrabberParam->devname_sensor));
rt_device_close(psDevLcd);
if (psDevLcd != RT_NULL)
rt_device_close(psDevLcd);
return;
}
@ -539,4 +543,5 @@ int ccap_demo(void)
return 0;
}
MSH_CMD_EXPORT(ccap_demo, camera capture demo);
//INIT_APP_EXPORT(ccap_demo);
//INIT_ENV_EXPORT(ccap_demo);
#endif

409
bsp/nuvoton/libraries/nu_packages/Demo/ccap_saver.c Normal file
View File

@ -0,0 +1,409 @@
/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-8-16 Wayne First version
*
******************************************************************************/
#include <rtthread.h>
#if defined(BSP_USING_CCAP)
#include "drv_ccap.h"
#include <dfs_posix.h>
#define DBG_ENABLE
#define DBG_LEVEL DBG_LOG
#define DBG_SECTION_NAME "ccap.saver"
#define DBG_COLOR
#include <rtdbg.h>
#define THREAD_PRIORITY 5
#define THREAD_STACK_SIZE 4096
#define THREAD_TIMESLICE 5
#define DEF_FRAME_WIDTH 640
#define DEF_FRAME_HEIGHT 480
typedef struct
{
char *thread_name;
char *devname_ccap;
char *devname_sensor;
} ccap_grabber_param;
typedef ccap_grabber_param *ccap_grabber_param_t;
typedef struct
{
ccap_config sCcapConfig;
uint32_t u32CurFBPointer;
uint32_t u32FrameEnd;
rt_sem_t semFrameEnd;
} ccap_grabber_context;
typedef ccap_grabber_context *ccap_grabber_context_t;
static void nu_ccap_event_hook(void *pvData, uint32_t u32EvtMask)
{
ccap_grabber_context_t psGrabberContext = (ccap_grabber_context_t)pvData;
if (u32EvtMask & NU_CCAP_FRAME_END)
{
rt_sem_release(psGrabberContext->semFrameEnd);
}
if (u32EvtMask & NU_CCAP_ADDRESS_MATCH)
{
LOG_I("Address matched");
}
if (u32EvtMask & NU_CCAP_MEMORY_ERROR)
{
LOG_E("Access memory error");
}
}
static rt_device_t ccap_sensor_init(ccap_grabber_context_t psGrabberContext, ccap_grabber_param_t psGrabberParam)
{
rt_err_t ret;
ccap_view_info_t psViewInfo;
sensor_mode_info *psSensorModeInfo;
rt_device_t psDevSensor = RT_NULL;
rt_device_t psDevCcap = RT_NULL;
ccap_config_t psCcapConfig = &psGrabberContext->sCcapConfig;
psDevCcap = rt_device_find(psGrabberParam->devname_ccap);
if (psDevCcap == RT_NULL)
{
LOG_E("Can't find %s", psGrabberParam->devname_ccap);
goto exit_ccap_sensor_init;
}
psDevSensor = rt_device_find(psGrabberParam->devname_sensor);
if (psDevSensor == RT_NULL)
{
LOG_E("Can't find %s", psGrabberParam->devname_sensor);
goto exit_ccap_sensor_init;
}
/* Packet pipe for preview */
psCcapConfig->sPipeInfo_Packet.u32Width = DEF_FRAME_WIDTH;
psCcapConfig->sPipeInfo_Packet.u32Height = DEF_FRAME_HEIGHT;
psCcapConfig->sPipeInfo_Packet.pu8FarmAddr = rt_malloc_align(psCcapConfig->sPipeInfo_Packet.u32Height * psCcapConfig->sPipeInfo_Packet.u32Width * 2, 32);
if (psCcapConfig->sPipeInfo_Packet.pu8FarmAddr == RT_NULL)
{
LOG_E("Can't malloc");
goto exit_ccap_sensor_init;
}
psCcapConfig->sPipeInfo_Packet.u32PixFmt = CCAP_PAR_OUTFMT_RGB565;
psCcapConfig->u32Stride_Packet = psCcapConfig->sPipeInfo_Packet.u32Width;
/* Planar pipe for encoding */
psCcapConfig->sPipeInfo_Planar.u32Width = psCcapConfig->sPipeInfo_Packet.u32Width;
psCcapConfig->sPipeInfo_Planar.u32Height = psCcapConfig->sPipeInfo_Packet.u32Height;
psCcapConfig->sPipeInfo_Planar.pu8FarmAddr = rt_malloc_align(psCcapConfig->sPipeInfo_Planar.u32Height * psCcapConfig->sPipeInfo_Planar.u32Width * 2, 32);
if (psCcapConfig->sPipeInfo_Planar.pu8FarmAddr == RT_NULL)
{
LOG_E("Can't malloc");
goto exit_ccap_sensor_init;
}
psCcapConfig->sPipeInfo_Planar.u32PixFmt = CCAP_PAR_PLNFMT_YUV422;
psCcapConfig->u32Stride_Planar = psCcapConfig->sPipeInfo_Planar.u32Width;
LOG_I("Packet.FarmAddr@0x%08X", psCcapConfig->sPipeInfo_Packet.pu8FarmAddr);
LOG_I("Packet.FarmWidth: %d", psCcapConfig->sPipeInfo_Packet.u32Width);
LOG_I("Packet.FarmHeight: %d", psCcapConfig->sPipeInfo_Packet.u32Height);
LOG_I("Planar.FarmAddr@0x%08X", psCcapConfig->sPipeInfo_Planar.pu8FarmAddr);
LOG_I("Planar.FarmWidth: %d", psCcapConfig->sPipeInfo_Planar.u32Width);
LOG_I("Planar.FarmHeight: %d", psCcapConfig->sPipeInfo_Planar.u32Height);
/* open CCAP */
ret = rt_device_open(psDevCcap, 0);
if (ret != RT_EOK)
{
LOG_E("Can't open %s", psGrabberParam->devname_ccap);
goto exit_ccap_sensor_init;
}
/* Find suit mode for packet pipe */
if (psCcapConfig->sPipeInfo_Packet.pu8FarmAddr != RT_NULL)
{
/* Check view window of packet pipe */
psViewInfo = &psCcapConfig->sPipeInfo_Packet;
if ((rt_device_control(psDevSensor, CCAP_SENSOR_CMD_GET_SUIT_MODE, (void *)&psViewInfo) != RT_EOK)
|| (psViewInfo == RT_NULL))
{
LOG_E("Can't get suit mode for packet.");
goto fail_ccap_init;
}
}
/* Find suit mode for planner pipe */
if (psCcapConfig->sPipeInfo_Planar.pu8FarmAddr != RT_NULL)
{
int recheck = 1;
if (psViewInfo != RT_NULL)
{
if ((psCcapConfig->sPipeInfo_Planar.u32Width <= psViewInfo->u32Width) ||
(psCcapConfig->sPipeInfo_Planar.u32Height <= psViewInfo->u32Height))
recheck = 0;
}
if (recheck)
{
/* Check view window of planner pipe */
psViewInfo = &psCcapConfig->sPipeInfo_Planar;
/* Find suit mode */
if ((rt_device_control(psDevSensor, CCAP_SENSOR_CMD_GET_SUIT_MODE, (void *)&psViewInfo) != RT_EOK)
|| (psViewInfo == RT_NULL))
{
LOG_E("Can't get suit mode for planner.");
goto exit_ccap_sensor_init;
}
}
}
/* Set cropping rectangle */
psCcapConfig->sRectCropping.x = 0;
psCcapConfig->sRectCropping.y = 0;
psCcapConfig->sRectCropping.width = psViewInfo->u32Width;
psCcapConfig->sRectCropping.height = psViewInfo->u32Height;
/* ISR Hook */
psCcapConfig->pfnEvHndler = nu_ccap_event_hook;
psCcapConfig->pvData = (void *)psGrabberContext;
/* Get Suitable mode. */
psSensorModeInfo = (sensor_mode_info *)psViewInfo;
/* Feed CCAP configuration */
ret = rt_device_control(psDevCcap, CCAP_CMD_CONFIG, (void *)psCcapConfig);
if (ret != RT_EOK)
{
LOG_E("Can't feed configuration %s", psGrabberParam->devname_ccap);
goto fail_ccap_init;
}
{
int i32SenClk = psSensorModeInfo->u32SenClk;
/* speed up pixel clock */
if (rt_device_control(psDevCcap, CCAP_CMD_SET_SENCLK, (void *)&i32SenClk) != RT_EOK)
{
LOG_E("Can't feed setting.");
goto fail_ccap_init;
}
}
/* Initial CCAP sensor */
if (rt_device_open(psDevSensor, 0) != RT_EOK)
{
LOG_E("Can't open sensor.");
goto fail_sensor_init;
}
/* Feed settings to sensor */
if (rt_device_control(psDevSensor, CCAP_SENSOR_CMD_SET_MODE, (void *)psSensorModeInfo) != RT_EOK)
{
LOG_E("Can't feed setting.");
goto fail_sensor_init;
}
ret = rt_device_control(psDevCcap, CCAP_CMD_SET_PIPES, (void *)psViewInfo);
if (ret != RT_EOK)
{
LOG_E("Can't set pipes %s", psGrabberParam->devname_ccap);
goto fail_ccap_init;
}
return psDevCcap;
fail_sensor_init:
if (psDevSensor)
rt_device_close(psDevSensor);
fail_ccap_init:
if (psDevCcap)
rt_device_close(psDevCcap);
exit_ccap_sensor_init:
psDevCcap = psDevSensor = RT_NULL;
return psDevCcap;
}
static void ccap_sensor_fini(rt_device_t psDevCcap, rt_device_t psDevSensor)
{
if (psDevSensor)
rt_device_close(psDevSensor);
if (psDevCcap)
rt_device_close(psDevCcap);
}
static int ccap_save_frame(char *szFilename, const void *data, size_t size)
{
int fd;
int wrote_size = 0;
fd = open(szFilename, O_WRONLY | O_CREAT);
if (fd < 0)
{
LOG_E("Could not open %s for writing.", szFilename);
goto exit_ccap_save_planar_frame;
}
if ((wrote_size = write(fd, data, size)) != size)
{
LOG_E("Could not write to %s (%d != %d).", szFilename, wrote_size, size);
goto exit_ccap_save_planar_frame;
}
wrote_size = size;
LOG_I("Output %s", szFilename);
exit_ccap_save_planar_frame:
if (fd >= 0)
close(fd);
return wrote_size;
}
static void ccap_grabber(void *parameter)
{
ccap_grabber_param_t psGrabberParam = (ccap_grabber_param_t)parameter;
ccap_grabber_context sGrabberContext;
rt_device_t psDevCcap = RT_NULL;
rt_memset((void *)&sGrabberContext, 0, sizeof(ccap_grabber_context));
sGrabberContext.semFrameEnd = rt_sem_create(psGrabberParam->devname_ccap, 0, RT_IPC_FLAG_FIFO);
if (sGrabberContext.semFrameEnd == RT_NULL)
{
LOG_E("Can't allocate sem resource %s", psGrabberParam->devname_ccap);
goto exit_ccap_grabber;
}
/* initial ccap & sensor*/
psDevCcap = ccap_sensor_init(&sGrabberContext, psGrabberParam);
if (psDevCcap == RT_NULL)
{
LOG_E("Can't init %s and %s", psGrabberParam->devname_ccap, psGrabberParam->devname_sensor);
goto exit_ccap_grabber;
}
/* Start to capture */
if (rt_device_control(psDevCcap, CCAP_CMD_START_CAPTURE, RT_NULL) != RT_EOK)
{
LOG_E("Can't start %s", psGrabberParam->devname_ccap);
goto exit_ccap_grabber;
}
while (1)
{
if (sGrabberContext.semFrameEnd)
{
rt_sem_take(sGrabberContext.semFrameEnd, RT_WAITING_FOREVER);
}
sGrabberContext.u32FrameEnd++;
LOG_I("%s Grabbed %d", psGrabberParam->devname_ccap, sGrabberContext.u32FrameEnd);
if (sGrabberContext.u32FrameEnd == 30)
{
char szFilename[64];
uint32_t u32Factor = 0;
LOG_I("%s Capturing %d", psGrabberParam->devname_ccap, sGrabberContext.u32FrameEnd);
if (sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV420)
{
u32Factor = 3;
rt_snprintf(szFilename, sizeof(szFilename), "/%08d_%dx%d.yuv420p",
rt_tick_get(),
sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Width,
sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Height);
}
else if (sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32PixFmt == CCAP_PAR_PLNFMT_YUV422)
{
u32Factor = 4;
rt_snprintf(szFilename, sizeof(szFilename), "/%08d_%s_%dx%d.yuv422p",
rt_tick_get(),
psGrabberParam->devname_ccap,
sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Width,
sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Height);
}
if (u32Factor > 0)
{
/* Save YUV422 or YUV420 frame from packet pipe*/
ccap_save_frame(szFilename, (const void *)sGrabberContext.sCcapConfig.sPipeInfo_Planar.pu8FarmAddr, sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Width * sGrabberContext.sCcapConfig.sPipeInfo_Planar.u32Height * u32Factor / 2);
}
/* Save RGB565 frame from packet pipe*/
rt_snprintf(szFilename, sizeof(szFilename), "/%08d_%s_%dx%d.rgb565",
rt_tick_get(),
psGrabberParam->devname_ccap,
sGrabberContext.sCcapConfig.sPipeInfo_Packet.u32Width,
sGrabberContext.sCcapConfig.sPipeInfo_Packet.u32Height);
ccap_save_frame(szFilename, (const void *)sGrabberContext.sCcapConfig.sPipeInfo_Packet.pu8FarmAddr, sGrabberContext.sCcapConfig.sPipeInfo_Packet.u32Width * sGrabberContext.sCcapConfig.sPipeInfo_Packet.u32Height * 2);
break;
}
}
exit_ccap_grabber:
ccap_sensor_fini(rt_device_find(psGrabberParam->devname_ccap), rt_device_find(psGrabberParam->devname_sensor));
return;
}
static void ccap_grabber_create(ccap_grabber_param_t psGrabberParam)
{
rt_thread_t ccap_thread = rt_thread_find(psGrabberParam->thread_name);
if (ccap_thread == RT_NULL)
{
ccap_thread = rt_thread_create(psGrabberParam->thread_name,
ccap_grabber,
psGrabberParam,
THREAD_STACK_SIZE,
THREAD_PRIORITY,
THREAD_TIMESLICE);
if (ccap_thread != RT_NULL)
rt_thread_startup(ccap_thread);
}
}
int ccap_saver(void)
{
#if defined(BSP_USING_CCAP0)
static ccap_grabber_param ccap0_grabber_param = {"grab0", "ccap0", "sensor0"};
ccap_grabber_create(&ccap0_grabber_param);
#endif
#if defined(BSP_USING_CCAP1)
static ccap_grabber_param ccap1_grabber_param = {"grab1", "ccap1", "sensor1"};
ccap_grabber_create(&ccap1_grabber_param);
#endif
return 0;
}
MSH_CMD_EXPORT(ccap_saver, camera saver demo);
#endif

93
bsp/nuvoton/libraries/nu_packages/Demo/hwsem_counter.c Normal file
View File

@ -0,0 +1,93 @@
/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-5 Wayne First version
*
******************************************************************************/
#include <rtthread.h>
#if defined(BSP_USING_HWSEM)
#include "drv_common.h"
#include "drv_hwsem.h"
#define DEF_COUNTER_ADDR_RTP (3*1024*1024)
#define DEF_COUNTER_ADDR_A35 ((0x80000000+DEF_COUNTER_ADDR_RTP)|UNCACHEABLE)
#if defined(USE_MA35D1_SUBM)
#define DEF_COUNTER_ADDR DEF_COUNTER_ADDR_RTP
#else
#define DEF_COUNTER_ADDR DEF_COUNTER_ADDR_A35
#endif
static void hwsem_counter_go(void *parameter)
{
rt_err_t ret;
rt_device_t psNuHwSem = (rt_device_t)parameter;
uint32_t *pu32Counter = (uint32_t *)DEF_COUNTER_ADDR;
nu_mutex_t psNuMutex = nu_mutex_init(psNuHwSem, evHWSEM0);
if (psNuMutex == RT_NULL)
return;
*pu32Counter = 0;
while (1)
{
ret = nu_mutex_take(psNuMutex, RT_WAITING_FOREVER);
if (ret != RT_EOK)
continue;
if (*pu32Counter >= 10)
{
nu_mutex_release(psNuMutex);
break;
}
else
*pu32Counter = *pu32Counter + 1;
#ifdef RT_USING_SMP
rt_kprintf("[%08x@CPU-%d] ->Inc %d@%08x\n", rt_thread_self(), rt_hw_cpu_id(), *pu32Counter, DEF_COUNTER_ADDR);
#else
rt_kprintf("[%08x]-> Inc %d@%08x\n", rt_thread_self(), *pu32Counter, DEF_COUNTER_ADDR);
#endif /* RT_USING_SMP */
nu_mutex_release(psNuMutex);
/* Relax, fair to get the mutex. */
rt_thread_mdelay(500);
}
nu_mutex_deinit(psNuHwSem, evHWSEM0);
}
static int hwsem_counter_app(void)
{
rt_err_t result = 0;
rt_thread_t thread;
rt_device_t psNuHwSem = rt_device_find("hwsem0");
if (psNuHwSem == RT_NULL)
return -1;
thread = rt_thread_create("hwsa35", hwsem_counter_go, (void *)psNuHwSem, 2048, 25, 20);
if (thread != RT_NULL)
{
#ifdef RT_USING_SMP
rt_thread_control(thread, RT_THREAD_CTRL_BIND_CPU, (void *)0);
#endif
result = rt_thread_startup(thread);
RT_ASSERT(result == RT_EOK);
}
return 0;
}
INIT_APP_EXPORT(hwsem_counter_app);
MSH_CMD_EXPORT(hwsem_counter_app, demo hwsem);
#endif /* #if defined(BSP_USING_HWSEM)*/

177
bsp/nuvoton/libraries/nu_packages/Demo/smp_demo.c Normal file
View File

@ -0,0 +1,177 @@
/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-8-16 Wayne First version
*
******************************************************************************/
#include <rtthread.h>
#if defined(RT_USING_SMP)
#include "drv_common.h"
#define DEF_COUNTER_ADDR_RTP (3*1024*1024)
#define DEF_COUNTER_ADDR_A35 ((0x80000000+DEF_COUNTER_ADDR_RTP)|UNCACHEABLE)
#if defined(USE_MA35D1_SUBM)
#define DEF_COUNTER_ADDR DEF_COUNTER_ADDR_RTP
#else
#define DEF_COUNTER_ADDR DEF_COUNTER_ADDR_A35
#endif
void happy_counter(void *pdata)
{
uint32_t counter = 0;
while (1)
{
rt_kprintf("cpu-%d %d\r\n", rt_hw_cpu_id(), counter++);
rt_thread_mdelay(1000);
}
}
void go_happy_counter(void)
{
rt_thread_t tid = rt_thread_create("cpu-1", happy_counter, RT_NULL, 2048, 10, 20);
RT_ASSERT(tid != RT_NULL);
rt_thread_control(tid, RT_THREAD_CTRL_BIND_CPU, (void *)1);
rt_thread_startup(tid);
}
MSH_CMD_EXPORT(go_happy_counter, go happy counter);
void happy_memcpy(void *pdata)
{
volatile uint32_t counter = 0;
void *srcbuf, *dstbuf;
rt_tick_t last, now;
#define DEF_BUF_SIZE 4096
#define DEF_TIMES 500000
srcbuf = rt_malloc_align(DEF_BUF_SIZE, nu_cpu_dcache_line_size());
dstbuf = rt_malloc_align(DEF_BUF_SIZE, nu_cpu_dcache_line_size());
now = rt_tick_get();
while (counter < DEF_TIMES)
{
rt_memcpy(dstbuf, srcbuf, DEF_BUF_SIZE);
counter++;
}
last = rt_tick_get();
if (rt_hw_cpu_id() == 1)
rt_thread_mdelay(1000);
rt_kprintf("%d Bytes copied by cpu-%d in %d ms\n", DEF_TIMES * DEF_BUF_SIZE, rt_hw_cpu_id(), last - now);
rt_free_align(srcbuf);
rt_free_align(dstbuf);
}
void go_happy_memcpy_0_1(void)
{
rt_thread_t tid0, tid1;
tid0 = rt_thread_create("cpu-0", happy_memcpy, RT_NULL, 2048, 10, 20);
RT_ASSERT(tid0 != RT_NULL);
rt_thread_control(tid0, RT_THREAD_CTRL_BIND_CPU, (void *)0);
tid1 = rt_thread_create("cpu-1", happy_memcpy, RT_NULL, 2048, 10, 20);
RT_ASSERT(tid1 != RT_NULL);
rt_thread_control(tid1, RT_THREAD_CTRL_BIND_CPU, (void *)1);
rt_thread_startup(tid0);
rt_thread_startup(tid1);
}
MSH_CMD_EXPORT(go_happy_memcpy_0_1, go happy memcpy on dual - core);
void go_happy_memcpy_0(void)
{
rt_thread_t tid0;
tid0 = rt_thread_create("cpu-0", happy_memcpy, RT_NULL, 2048, 10, 20);
RT_ASSERT(tid0 != RT_NULL);
rt_thread_control(tid0, RT_THREAD_CTRL_BIND_CPU, (void *)0);
rt_thread_startup(tid0);
}
MSH_CMD_EXPORT(go_happy_memcpy_0, go happy memcpy on core0);
void go_happy_memcpy_1(void)
{
rt_thread_t tid1;
tid1 = rt_thread_create("cpu-1", happy_memcpy, RT_NULL, 2048, 10, 20);
RT_ASSERT(tid1 != RT_NULL);
rt_thread_control(tid1, RT_THREAD_CTRL_BIND_CPU, (void *)1);
rt_thread_startup(tid1);
}
MSH_CMD_EXPORT(go_happy_memcpy_1, go happy memcpy on core1);
static void happy_mutex(void *parameter)
{
rt_err_t ret;
rt_mutex_t psMutex = (rt_mutex_t)parameter;
uint32_t *pu32Counter = (uint32_t *)DEF_COUNTER_ADDR;
*pu32Counter = 0;
while (1)
{
ret = rt_mutex_take(psMutex, RT_WAITING_FOREVER);
if (ret != RT_EOK)
continue;
if (*pu32Counter >= 1000)
{
rt_mutex_release(psMutex);
break;
}
else
*pu32Counter = *pu32Counter + 1;
#ifdef RT_USING_SMP
rt_kprintf("[%08x@CPU-%d] ->Inc %d@%08x\n", rt_thread_self(), rt_hw_cpu_id(), *pu32Counter, DEF_COUNTER_ADDR);
#else
rt_kprintf("[%08x]-> Inc %d@%08x\n", rt_thread_self(), *pu32Counter, DEF_COUNTER_ADDR);
#endif /* RT_USING_SMP */
rt_mutex_release(psMutex);
}
}
static int go_happy_mutex(void)
{
rt_thread_t thread;
rt_mutex_t sem = rt_mutex_create("mutexsem", RT_IPC_FLAG_PRIO);
thread = rt_thread_create("mutex0", happy_mutex, (void *)sem, 2048, 25, 20);
if (thread != RT_NULL)
{
#ifdef RT_USING_SMP
rt_thread_control(thread, RT_THREAD_CTRL_BIND_CPU, (void *)0);
#endif
rt_thread_startup(thread);
}
thread = rt_thread_create("mutex1", happy_mutex, (void *)sem, 2048, 25, 20);
if (thread != RT_NULL)
{
#ifdef RT_USING_SMP
rt_thread_control(thread, RT_THREAD_CTRL_BIND_CPU, (void *)1);
#endif
rt_thread_startup(thread);
}
return 0;
}
MSH_CMD_EXPORT(go_happy_mutex, demo mutex);
#endif

325
bsp/nuvoton/libraries/nu_packages/Demo/wormhole_demo.c Normal file
View File

@ -0,0 +1,325 @@
/**************************************************************************//**
*
* @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-10 Wayne First version
*
******************************************************************************/
#include <rtthread.h>
#if defined(BSP_USING_WHC)
#include "drv_whc.h"
#include <stdio.h>
#define DBG_ENABLE
#define DBG_LEVEL DBG_LOG
#define DBG_SECTION_NAME "whc.demo"
#define DBG_COLOR
#include <rtdbg.h>
#define USE_WORMHOLE_CHNAME "whc0-0"
typedef enum
{
evCMD_MEM_ALLOCATE,
evCMD_MEM_FREE,
evCMD_MEM_COPY,
evCMD_DEVMEM_WRITE,
evCMD_DEVMEM_READ,
evCMD_MEM_SET
} nu_whc_cmd;
typedef enum
{
evCMD_REQ,
evCMD_RESP,
} nu_whc_cmd_type;
#define CMD_TYPE_Pos 16
#define CMD_TYPE_Msk (3<<CMD_TYPE_Pos)
#define PACK_MSG_CMD(t, x) (((t<<CMD_TYPE_Pos)&CMD_TYPE_Msk)|x)
#define CMD_IS_REQ(m) (((m.u32Cmd&CMD_TYPE_Msk)>>CMD_TYPE_Pos)==evCMD_REQ)
#define CMD_IS_RESP(m) (((m.u32Cmd&CMD_TYPE_Msk)>>CMD_TYPE_Pos)==evCMD_RESP)
typedef struct
{
union
{
nu_whc_msg sMsgBuf;
struct
{
uint32_t u32Cmd;
uint32_t u32Addr0; //Dst, free, allocate, set
uint32_t u32Addr1; //Src, value
uint32_t u32Size;
} msg;
};
} whc_mem;
typedef whc_mem *whc_mem_t;
static struct rt_semaphore tx_sem;
static struct rt_semaphore rx_sem;
static rt_device_t device = RT_NULL;
static rt_err_t whc_tx_complete(rt_device_t dev, void *buffer)
{
return rt_sem_release(&tx_sem);
}
static rt_err_t whc_rx_indicate(rt_device_t dev, rt_size_t size)
{
return rt_sem_release(&rx_sem);
}
static rt_err_t proc_msg(whc_mem_t req, whc_mem_t resp)
{
switch ((nu_whc_cmd)req->msg.u32Cmd)
{
case evCMD_MEM_ALLOCATE:
resp->msg.u32Addr0 = (uint32_t)rt_malloc(req->msg.u32Size);
resp->msg.u32Size = req->msg.u32Size;
resp->msg.u32Cmd = PACK_MSG_CMD(evCMD_RESP, evCMD_MEM_ALLOCATE);
break;
case evCMD_MEM_FREE:
rt_free((void *)req->msg.u32Addr0);
resp->msg.u32Addr0 = (uint32_t)req->msg.u32Addr0;
resp->msg.u32Cmd = PACK_MSG_CMD(evCMD_RESP, evCMD_MEM_FREE);
resp->msg.u32Size = 0;
break;
case evCMD_MEM_COPY:
rt_memcpy((void *)req->msg.u32Addr0, (void *)req->msg.u32Addr1, req->msg.u32Size);
resp->msg.u32Cmd = PACK_MSG_CMD(evCMD_RESP, evCMD_MEM_COPY);
resp->msg.u32Addr0 = (uint32_t)req->msg.u32Addr0;
resp->msg.u32Addr1 = (uint32_t)req->msg.u32Addr1;
resp->msg.u32Size = req->msg.u32Size;
break;
case evCMD_MEM_SET:
rt_memset((void *)req->msg.u32Addr0, (req->msg.u32Addr1 & 0xff), req->msg.u32Size);
resp->msg.u32Cmd = PACK_MSG_CMD(evCMD_RESP, evCMD_MEM_SET);
resp->msg.u32Addr0 = (uint32_t)req->msg.u32Addr0;
resp->msg.u32Addr1 = (uint32_t)(req->msg.u32Addr1 & 0xff);
resp->msg.u32Size = req->msg.u32Size;
break;
case evCMD_DEVMEM_WRITE:
*((vu32 *)req->msg.u32Addr0) = req->msg.u32Addr1;
resp->msg.u32Cmd = PACK_MSG_CMD(evCMD_RESP, evCMD_DEVMEM_WRITE);
resp->msg.u32Addr0 = 0;
resp->msg.u32Addr1 = 0;
resp->msg.u32Size = sizeof(uint32_t);
break;
case evCMD_DEVMEM_READ:
resp->msg.u32Cmd = PACK_MSG_CMD(evCMD_RESP, evCMD_DEVMEM_READ);
resp->msg.u32Addr0 = *((vu32 *)req->msg.u32Addr0);
resp->msg.u32Addr1 = 0;
resp->msg.u32Size = sizeof(uint32_t);
break;
default:
return -RT_ERROR;
}
return -RT_ERROR;
}
static rt_err_t send_msg(whc_mem_t req)
{
if (device)
{
if (sizeof(nu_whc_msg) != rt_device_write(device, 0, req, sizeof(nu_whc_msg)))
{
LOG_E("Failed to send msg.");
return -RT_ERROR;
}
if (-RT_ETIMEOUT == rt_sem_take(&tx_sem, 100))
LOG_E("Timeout cant get ACK.");
}
return RT_EOK;
}
static void whc_daemon(void *parameter)
{
rt_err_t ret;
device = rt_device_find(USE_WORMHOLE_CHNAME);
RT_ASSERT(device);
/* Init semaphores */
ret = rt_sem_init(&tx_sem, "whc_tx", 0, RT_IPC_FLAG_PRIO);
RT_ASSERT(ret == RT_EOK);
ret = rt_sem_init(&rx_sem, "whc_rx", 0, RT_IPC_FLAG_PRIO);
RT_ASSERT(ret == RT_EOK);
/* Set tx complete function */
ret = rt_device_set_tx_complete(device, whc_tx_complete);
RT_ASSERT(ret == RT_EOK);
/* Set rx indicate function */
ret = rt_device_set_rx_indicate(device, whc_rx_indicate);
RT_ASSERT(ret == RT_EOK);
ret = rt_device_open(device, 0);
if (!device)
{
LOG_E("Failed to open %s", USE_WORMHOLE_CHNAME);
return;
}
while (1)
{
if (rt_sem_take(&rx_sem, RT_WAITING_FOREVER) == RT_EOK)
{
nu_whc_msg sNuWhcMsg;
whc_mem_t psWhcMem = (whc_mem_t)&sNuWhcMsg;
if (sizeof(nu_whc_msg) != rt_device_read(device, 0, psWhcMem, sizeof(nu_whc_msg)))
continue;
if (CMD_IS_REQ(psWhcMem->msg))
{
nu_whc_msg sNuWhcMsg_Resp;
proc_msg((whc_mem_t)&sNuWhcMsg, (whc_mem_t)&sNuWhcMsg_Resp);
send_msg((whc_mem_t)&sNuWhcMsg_Resp);
}
else if (CMD_IS_RESP(psWhcMem->msg))
{
LOG_I("Get Resp. 0x%08x 0x%08x 0x%08x %d",
psWhcMem->msg.u32Cmd,
psWhcMem->msg.u32Addr0,
psWhcMem->msg.u32Addr1,
psWhcMem->msg.u32Size);
}
} //if
} //while
}
static int wormhole_app(void)
{
rt_err_t result = 0;
rt_thread_t thread;
thread = rt_thread_create("whcD", whc_daemon, RT_NULL, 2048, 25, 20);
if (thread != RT_NULL)
{
result = rt_thread_startup(thread);
RT_ASSERT(result == RT_EOK);
}
return 0;
}
INIT_COMPONENT_EXPORT(wormhole_app);
void *whc_malloc(uint32_t u32Size)
{
whc_mem sWhcMem;
sWhcMem.msg.u32Cmd = PACK_MSG_CMD(evCMD_REQ, evCMD_MEM_ALLOCATE);
sWhcMem.msg.u32Size = (uint32_t)u32Size;
send_msg(&sWhcMem);
return 0;
}
RTM_EXPORT(whc_malloc);
void *whc_memcpy(void *pvDst, void *pvSrc, uint32_t u32Size)
{
whc_mem sWhcMem;
sWhcMem.msg.u32Cmd = PACK_MSG_CMD(evCMD_REQ, evCMD_MEM_COPY);
sWhcMem.msg.u32Addr0 = (uint32_t)pvDst;
sWhcMem.msg.u32Addr1 = (uint32_t)pvSrc;
sWhcMem.msg.u32Size = (uint32_t)u32Size;
send_msg(&sWhcMem);
return 0;
}
RTM_EXPORT(whc_memcpy);
uint32_t whc_devmem_write(void *pvaddr, uint32_t u32value)
{
whc_mem sWhcMem;
sWhcMem.msg.u32Cmd = PACK_MSG_CMD(evCMD_REQ, evCMD_DEVMEM_WRITE);
sWhcMem.msg.u32Addr0 = (uint32_t)pvaddr;
sWhcMem.msg.u32Addr1 = u32value;
sWhcMem.msg.u32Size = sizeof(uint32_t);
send_msg(&sWhcMem);
return 0;
}
RTM_EXPORT(whc_devmem_write);
uint32_t whc_devmem_read(void *pvaddr)
{
whc_mem sWhcMem;
sWhcMem.msg.u32Cmd = PACK_MSG_CMD(evCMD_REQ, evCMD_DEVMEM_READ);
sWhcMem.msg.u32Addr0 = (uint32_t)pvaddr;
sWhcMem.msg.u32Addr1 = 0;
sWhcMem.msg.u32Size = sizeof(uint32_t);
send_msg(&sWhcMem);
return 0;
}
RTM_EXPORT(whc_devmem_read);
void whc_devmem(int argc, char *argv[])
{
volatile unsigned int u32Addr;
unsigned int value = 0, mode = 0;
if (argc < 2 || argc > 3)
{
goto exit_devmem;
}
if (argc == 3)
{
if (sscanf(argv[2], "0x%x", &value) != 1)
goto exit_devmem;
mode = 1; //Write
}
if (sscanf(argv[1], "0x%x", &u32Addr) != 1)
goto exit_devmem;
else if (u32Addr & (4 - 1))
goto exit_devmem;
if (mode)
{
whc_devmem_write((void *) u32Addr, value);
}
rt_kprintf("0x%08x\n", whc_devmem_read((void *)u32Addr));
return;
exit_devmem:
rt_kprintf("Read: whc_devmem <physical address in hex>\n");
rt_kprintf("Write: whc_devmem <physical address in hex> <value in hex format>\n");
return;
}
MSH_CMD_EXPORT(whc_devmem, dump device registers);
#endif /* #if defined(BSP_USING_HWSEM)*/

4
bsp/nuvoton/libraries/nu_packages/Kconfig
View File

@ -7,10 +7,6 @@ menu "Nuvoton Packages Config"
bool "Enable demos"
default y
config NU_PKG_USING_LVGL
bool "Enable LVGL demos"
default n
config NU_PKG_USING_BMX055
bool "BMX055 9-axis sensor."
select RT_USING_I2C

7
bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.c
View File

@ -15,8 +15,7 @@
#if defined(NU_PKG_USING_MAX31875)
#include <sys/time.h>
#include "sensor.h"
#include "max31875_c.h"
#include "sensor_max31875.h"
#define DBG_ENABLE
#define DBG_LEVEL DBG_LOG
@ -65,9 +64,9 @@ static int max31875_i2c_read_reg(int address, const char *reg, int reg_length, c
return RT_EOK;
}
static rt_size_t max31875_fetch_data(struct rt_sensor_device *sensor, void *buf, rt_size_t len)
static rt_ssize_t max31875_fetch_data(rt_sensor_t sensor, rt_sensor_data_t data, rt_size_t len)
{
struct rt_sensor_data *data = (struct rt_sensor_data *)buf;
RT_ASSERT(data);
if (sensor->info.type == RT_SENSOR_CLASS_TEMP)
{

3
bsp/nuvoton/libraries/nu_packages/MAX31875/sensor_max31875.h
View File

@ -13,7 +13,8 @@
#ifndef __SENSOR_MAX31875_H__
#define __SENSOR_MAX31875_H__
#include "sensor.h"
#include "rtdevice.h"
#include "max31875_c.h"
int rt_hw_max31875_init(const char *name, struct rt_sensor_config *cfg);

31
bsp/nuvoton/libraries/nu_packages/NCT7717U/sensor_nct7717u.c
View File

@ -13,7 +13,6 @@
#include <rtthread.h>
#include <sys/time.h>
#include "sensor.h"
#include "sensor_nct7717u.h"
#define DBG_ENABLE
@ -116,19 +115,19 @@ static rt_err_t nct7717u_ldt_readout(struct rt_i2c_bus_device *i2c_bus_dev, uint
return nct7717u_i2c_read_reg(i2c_bus_dev, (const char *)&u8Reg, sizeof(u8Reg), (char *)u8Temp, sizeof(uint8_t));
}
static rt_size_t nct7717u_fetch_data(struct rt_sensor_device *sensor, void *buf, rt_size_t len)
static rt_ssize_t nct7717u_fetch_data(rt_sensor_t sensor, rt_sensor_data_t data, rt_size_t len)
{
struct rt_sensor_data *data = (struct rt_sensor_data *)buf;
RT_ASSERT(data);
if (sensor->info.type == RT_SENSOR_CLASS_TEMP)
if (sensor->info.type == RT_SENSOR_TYPE_TEMP)
{
rt_int8_t i8Temp;
struct rt_i2c_bus_device *i2c_bus_dev = sensor->config.intf.user_data;
struct rt_i2c_bus_device *i2c_bus_dev = sensor->config.intf.arg;
if (nct7717u_ldt_readout(i2c_bus_dev, (uint8_t *)&i8Temp) == RT_EOK)
{
rt_int32_t i32TempValue = i8Temp;
data->type = RT_SENSOR_CLASS_TEMP;
data->type = RT_SENSOR_TYPE_TEMP;
data->data.temp = i32TempValue * 10;
data->timestamp = rt_sensor_get_ts();
return 1;
@ -143,7 +142,7 @@ static rt_err_t nct7717u_control(struct rt_sensor_device *sensor, int cmd, void
{
case RT_SENSOR_CTRL_GET_ID:
{
struct rt_i2c_bus_device *i2c_bus_dev = sensor->config.intf.user_data;
struct rt_i2c_bus_device *i2c_bus_dev = sensor->config.intf.arg;
uint8_t u8Did;
RT_ASSERT(args);
@ -174,14 +173,14 @@ int rt_hw_nct7717u_temp_init(const char *name, struct rt_sensor_config *cfg)
if (sensor == RT_NULL)
return -(RT_ENOMEM);
sensor->info.type = RT_SENSOR_CLASS_TEMP;
sensor->info.vendor = RT_SENSOR_VENDOR_UNKNOWN;
sensor->info.model = "nct7717u_temp";
sensor->info.unit = RT_SENSOR_UNIT_DCELSIUS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.range_max = 127;
sensor->info.range_min = -128;
sensor->info.period_min = 100; //100ms
sensor->info.type = RT_SENSOR_TYPE_TEMP;
sensor->info.vendor = RT_SENSOR_VENDOR_UNKNOWN;
sensor->info.name = "nct7717u_temp";
sensor->info.unit = RT_SENSOR_UNIT_CELSIUS;
sensor->info.intf_type = RT_SENSOR_INTF_I2C;
sensor->info.scale.range_max = 127;
sensor->info.scale.range_min = -128;
sensor->info.acquire_min = 100; //100ms
rt_memcpy(&sensor->config, cfg, sizeof(struct rt_sensor_config));
sensor->ops = &sensor_ops;
@ -213,7 +212,7 @@ int rt_hw_nct7717u_init(const char *name, struct rt_sensor_config *cfg)
{
goto exit_rt_hw_nct7717u_init;
}
intf->user_data = i2c_bus_dev;
intf->arg = i2c_bus_dev;
if (nct7717u_probe(i2c_bus_dev) != RT_EOK)
goto exit_rt_hw_nct7717u_init;

2
bsp/nuvoton/libraries/nu_packages/NCT7717U/sensor_nct7717u.h
View File

@ -13,7 +13,7 @@
#ifndef __SENSOR_NCT7717U_H__
#define __SENSOR_NCT7717U_H__
#include "sensor.h"
#include "rtdevice.h"
int rt_hw_nct7717u_init(const char *name, struct rt_sensor_config *cfg);

18
bsp/nuvoton/libraries/nu_packages/SPINAND/drv_spinand.c
View File

@ -864,14 +864,14 @@ static int nid(int argc, char **argv)
*/
#include "drv_spi.h"
static int find_valid_window(const char* pcDevName)
static int find_valid_window(const char *pcDevName)
{
rt_device_t psRtDev;
nu_spi_t psNuSpiBus;
int i, j, k;
psRtDev = rt_device_find(pcDevName);
if (!psRtDev || (psRtDev->type != RT_Device_Class_SPIDevice) )
if (!psRtDev || (psRtDev->type != RT_Device_Class_SPIDevice))
{
LOG_E("Usage %s: %s <spi device name>.\n", __func__, __func__);
return -1;
@ -887,21 +887,21 @@ static int find_valid_window(const char* pcDevName)
LOG_I("Probe JEDEC[%08X] on %s bus.", u32JedecId, psNuSpiBus->name);
rt_kprintf(" ");
for (i=0; i<8; i++) // Pin driving
for (i = 0; i < 8; i++) // Pin driving
rt_kprintf("%d ", i);
rt_kprintf("\n");
for (j=0; j<0xC; j++) // Master RX delay cycle
for (j = 0; j < 0xC; j++) // Master RX delay cycle
{
rt_kprintf("%X: ", j);
for (i=0; i<8; i++) // Pin driving
for (i = 0; i < 8; i++) // Pin driving
{
SPI_SET_MRXPHASE(psNuSpiBus->spi_base, j);
GPIO_SetDrivingCtl(PD, (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5), i);
GPIO_SetDrivingCtl(PD, (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5), i);
spinand_jedecid_get((struct rt_qspi_device *)psRtDev, &id);
if ( id==u32JedecId )
if (id == u32JedecId)
{
rt_kprintf("O ");
}
@ -934,9 +934,9 @@ static int nprobe(int argc, char **argv)
static int nprobe_auto(int argc, char **argv)
{
int count=0;
int count = 0;
while( count++ < 100 )
while (count++ < 100)
find_valid_window("qspi01");
return 0;

10
bsp/nuvoton/libraries/nu_packages/TPC/ft5446.c
View File

@ -318,11 +318,11 @@ int rt_hw_ft5446_init(const char *name, struct rt_touch_config *cfg)
ft5446_init(&ft5446_client);
rt_memset(&pre_x[0], 0xff, FT_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_y[0], 0xff, FT_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_w[0], 0xff, FT_MAX_TOUCH * sizeof(int16_t));
rt_memset(&s_tp_dowm[0], 0, FT_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_id[0], 0xff, FT_MAX_TOUCH * sizeof(int8_t));
rt_memset(&pre_x[0], 0xff, FT_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&pre_y[0], 0xff, FT_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&pre_w[0], 0xff, FT_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&s_tp_dowm[0], 0, FT_MAX_TOUCH * sizeof(rt_int8_t));
rt_memset(&pre_id[0], 0xff, FT_MAX_TOUCH * sizeof(rt_int8_t));
/* register touch device */
touch_device->info.type = RT_TOUCH_TYPE_CAPACITANCE;

2
bsp/nuvoton/libraries/nu_packages/TPC/gt911.c
View File

@ -471,7 +471,7 @@ int rt_hw_gt911_init(const char *name, struct rt_touch_config *cfg)
rt_memset(&pre_x[0], 0xff, GT911_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&pre_y[0], 0xff, GT911_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&pre_w[0], 0xff, GT911_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&s_tp_dowm[0], 0, GT911_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&s_tp_dowm[0], 0, GT911_MAX_TOUCH * sizeof(rt_int8_t));
rt_memset(&pre_id[0], 0xff, GT911_MAX_TOUCH * sizeof(rt_uint8_t));
/* register touch device */

10
bsp/nuvoton/libraries/nu_packages/TPC/ili.c
View File

@ -615,11 +615,11 @@ int rt_hw_ili_tpc_init(const char *name, struct rt_touch_config *cfg)
goto exit_rt_hw_ili_tpc_init;
}
rt_memset(&pre_x[0], 0xff, ILI_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_y[0], 0xff, ILI_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_w[0], 0xff, ILI_MAX_TOUCH * sizeof(int16_t));
rt_memset(&s_tp_dowm[0], 0, ILI_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_id[0], 0xff, ILI_MAX_TOUCH * sizeof(int8_t));
rt_memset(&pre_x[0], 0xff, ILI_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&pre_y[0], 0xff, ILI_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&pre_w[0], 0xff, ILI_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&s_tp_dowm[0], 0, ILI_MAX_TOUCH * sizeof(rt_uint8_t));
rt_memset(&pre_id[0], 0xff, ILI_MAX_TOUCH * sizeof(rt_uint8_t));
/* register touch device */
rt_memcpy(&touch_device->config, cfg, sizeof(struct rt_touch_config));

10
bsp/nuvoton/libraries/nu_packages/TPC/st1663i.c
View File

@ -313,11 +313,11 @@ int rt_hw_st1663i_init(const char *name, struct rt_touch_config *cfg)
st1663i_init(&st1663i_client);
rt_memset(&pre_x[0], 0xff, ST_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_y[0], 0xff, ST_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_w[0], 0xff, ST_MAX_TOUCH * sizeof(int16_t));
rt_memset(&s_tp_dowm[0], 0, ST_MAX_TOUCH * sizeof(int16_t));
rt_memset(&pre_id[0], 0xff, ST_MAX_TOUCH * sizeof(int8_t));
rt_memset(&pre_x[0], 0xff, ST_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&pre_y[0], 0xff, ST_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&pre_w[0], 0xff, ST_MAX_TOUCH * sizeof(rt_int16_t));
rt_memset(&s_tp_dowm[0], 0, ST_MAX_TOUCH * sizeof(rt_int8_t));
rt_memset(&pre_id[0], 0xff, ST_MAX_TOUCH * sizeof(rt_int8_t));
/* register touch device */
touch_device->info.type = RT_TOUCH_TYPE_CAPACITANCE;

2
bsp/nuvoton/libraries/nuc980/Driver/Source/nu_rtc.c
View File

@ -349,7 +349,7 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
{
uint32_t u32RegCAL, u32RegTIME;
if (sPt == 0ul)
if (sPt == NULL)
{
}
else

1
bsp/nuvoton/libraries/nuc980/rtt_port/Kconfig
View File

@ -12,6 +12,7 @@ config SOC_SERIES_NUC980
config BSP_USING_MMU
bool "Enable MMU"
select ARCH_ARM_MMU
default y
menuconfig BSP_USING_PDMA

333
bsp/nuvoton/ma35-rtp/.config
View File

@ -9,6 +9,7 @@ CONFIG_USE_MA35D1_SUBM=y
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@ -77,16 +78,19 @@ CONFIG_RT_USING_HEAP=y
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart16"
CONFIG_RT_VER_NUM=0x50000
CONFIG_ARCH_ARM=y
# CONFIG_RT_USING_CACHE is not set
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M4=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
@ -113,12 +117,12 @@ CONFIG_FINSH_USING_DESCRIPTION=y
CONFIG_FINSH_ARG_MAX=10
# CONFIG_RT_USING_DFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
@ -133,10 +137,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=256
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
@ -144,10 +152,13 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
@ -353,6 +364,7 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -360,6 +372,7 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
#
# security packages
@ -451,7 +464,6 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
@ -485,8 +497,8 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
@ -522,7 +534,6 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
@ -557,19 +568,93 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@ -592,12 +677,9 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
@ -612,7 +694,6 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
@ -643,10 +724,11 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
#
# AI packages
@ -661,6 +743,12 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
@ -712,7 +800,6 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
@ -722,6 +809,213 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
#
# Hardware Drivers Config
@ -768,6 +1062,10 @@ CONFIG_BSP_USING_UART16=y
# CONFIG_BSP_USING_QEI is not set
# CONFIG_BSP_USING_SOFT_I2C is not set
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_HWSEM=y
CONFIG_BSP_USING_HWSEM0=y
CONFIG_BSP_USING_WHC=y
CONFIG_BSP_USING_WHC0=y
# CONFIG_BSP_USING_EBI is not set
#
@ -783,8 +1081,7 @@ CONFIG_BSP_USING_NULINKME=y
# Nuvoton Packages Config
#
CONFIG_NU_PKG_USING_UTILS=y
# CONFIG_NU_PKG_USING_DEMO is not set
# CONFIG_NU_PKG_USING_LVGL is not set
CONFIG_NU_PKG_USING_DEMO=y
# CONFIG_NU_PKG_USING_BMX055 is not set
# CONFIG_NU_PKG_USING_MAX31875 is not set
# CONFIG_NU_PKG_USING_NCT7717U is not set
@ -797,5 +1094,3 @@ CONFIG_NU_PKG_USING_UTILS=y
# CONFIG_NU_PKG_USING_TPC is not set
# CONFIG_NU_PKG_USING_ADC_TOUCH is not set
# CONFIG_NU_PKG_USING_SPINAND is not set
CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest."
CONFIG_BOARD_USE_UTEST=y

BIN
bsp/nuvoton/ma35-rtp/rtthread.bin
View File

Binary file not shown.

347
bsp/nuvoton/nk-980iot/.config
View File

@ -8,6 +8,7 @@
#
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@ -61,7 +62,7 @@ CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BSET_MODE is not set
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
@ -76,15 +77,20 @@ CONFIG_RT_USING_HEAP=y
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x50000
CONFIG_ARCH_ARM=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARM_ARM9=y
CONFIG_RT_USING_CACHE=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_MM_MMU=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_MMU=y
CONFIG_ARCH_ARM_ARM9=y
#
# RT-Thread Components
@ -141,15 +147,17 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
@ -171,11 +179,15 @@ CONFIG_RT_USING_I2C_BITOPS=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
CONFIG_RT_USING_MTD_NAND=y
CONFIG_RT_MTD_NAND_DEBUG=y
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
CONFIG_RT_USING_RTC=y
CONFIG_RT_USING_ALARM=y
# CONFIG_RT_USING_SOFT_RTC is not set
@ -194,6 +206,7 @@ CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2
CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
CONFIG_RT_USING_HWCRYPTO=y
CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto"
CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16
@ -220,7 +233,9 @@ CONFIG_RT_HWCRYPTO_USING_RNG=y
# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
@ -424,7 +439,6 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_NETUTILS_LATEST_VERSION is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
@ -472,6 +486,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -479,6 +494,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
#
# security packages
@ -578,7 +594,6 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
@ -612,8 +627,8 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
@ -649,7 +664,6 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
@ -661,16 +675,7 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
CONFIG_PKG_USING_DFS_UFFS=y
CONFIG_PKG_UFFS_PATH="/packages/system/uffs"
CONFIG_RT_USING_DFS_UFFS=y
# CONFIG_RT_UFFS_ECC_MODE_0 is not set
# CONFIG_RT_UFFS_ECC_MODE_1 is not set
# CONFIG_RT_UFFS_ECC_MODE_2 is not set
CONFIG_RT_UFFS_ECC_MODE_3=y
CONFIG_RT_UFFS_ECC_MODE=3
CONFIG_PKG_USING_DFS_UFFS_LATEST_VERSION=y
CONFIG_PKG_UFFS_VER="latest"
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
@ -697,19 +702,93 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@ -732,12 +811,9 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
@ -752,7 +828,6 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
@ -783,10 +858,11 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
#
# AI packages
@ -801,6 +877,12 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
@ -856,7 +938,6 @@ CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
@ -866,6 +947,213 @@ CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
#
# Hardware Drivers Config
@ -982,7 +1270,6 @@ CONFIG_BOARD_USING_USB1_HOST=y
#
CONFIG_NU_PKG_USING_UTILS=y
CONFIG_NU_PKG_USING_DEMO=y
# CONFIG_NU_PKG_USING_LVGL is not set
# CONFIG_NU_PKG_USING_BMX055 is not set
# CONFIG_NU_PKG_USING_MAX31875 is not set
# CONFIG_NU_PKG_USING_NCT7717U is not set
@ -995,5 +1282,3 @@ CONFIG_NU_PKG_USING_NAU8822=y
# CONFIG_NU_PKG_USING_TPC is not set
# CONFIG_NU_PKG_USING_ADC_TOUCH is not set
CONFIG_NU_PKG_USING_SPINAND=y
CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest."
CONFIG_BOARD_USE_UTEST=y

7
bsp/nuvoton/nk-980iot/applications/lvgl/lv_demo.c
View File

@ -17,16 +17,15 @@ void lv_user_gui_init(void)
#if LV_USE_DEMO_BENCHMARK
extern void lv_demo_benchmark(void);
lv_demo_benchmark();
#endif
#if LV_USE_DEMO_WIDGETS
#elif LV_USE_DEMO_WIDGETS
extern void lv_demo_widgets(void);
lv_demo_widgets();
#endif
#if LV_USE_DEMO_MUSIC || LV_USE_DEMO_RTT_MUSIC
#elif (LV_USE_DEMO_MUSIC || LV_USE_DEMO_RTT_MUSIC)
extern void lv_demo_music(void);
lv_demo_music();
#endif
}

6
bsp/nuvoton/nk-980iot/applications/lvgl/lv_port_disp.c
View File

@ -16,6 +16,10 @@
#define DBG_COLOR
#include <rtdbg.h>
#if !defined(NU_PKG_LVGL_RENDERING_LAYER)
#define NU_PKG_LVGL_RENDERING_LAYER "lcd"
#endif
/*A static or global variable to store the buffers*/
static lv_disp_draw_buf_t disp_buf;
static lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/
@ -47,7 +51,7 @@ void lv_port_disp_init(void)
rt_err_t result;
void *buf1 = RT_NULL;
lcd_device = rt_device_find("lcd");
lcd_device = rt_device_find(NU_PKG_LVGL_RENDERING_LAYER);
if (lcd_device == 0)
{
LOG_E("error!");

23
bsp/nuvoton/nk-980iot/applications/lvgl/lv_port_disp.h
View File

@ -1,23 +0,0 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-18 Meco Man The first version
*/
#ifndef LV_PORT_DISP_H
#define LV_PORT_DISP_H
#ifdef __cplusplus
extern "C" {
#endif
void lv_port_disp_init(void);
#ifdef __cplusplus
} /*extern "C"*/
#endif
#endif

28
bsp/nuvoton/nk-980iot/applications/lvgl/lv_port_indev.h
View File

@ -1,28 +0,0 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-18 Meco Man The first version
*/
#ifndef LV_PORT_INDEV_H
#define LV_PORT_INDEV_H
#ifdef __cplusplus
extern "C" {
#endif
#include <lv_hal_indev.h>
extern lv_indev_t *button_indev;
void lv_port_indev_init(void);
void lv_port_indev_input(rt_int16_t x, rt_int16_t y, lv_indev_state_t state);
#ifdef __cplusplus
} /*extern "C"*/
#endif
#endif

2133
bsp/nuvoton/nk-980iot/project.uvproj
View File

File diff suppressed because it is too large Load Diff

442
bsp/nuvoton/nk-980iot/rtconfig.h
View File

@ -1,442 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 2048
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_SIGNALS
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_MEMTRACE
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40101
#define ARCH_ARM
#define ARCH_ARM_ARM9
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 16
#define DFS_FILESYSTEM_TYPES_MAX 16
#define DFS_FD_MAX 64
#define RT_USING_DFS_MNTTABLE
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 8
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 2048
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_USING_HWTIMER
#define RT_USING_CPUTIME
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
#define RT_USING_ADC
#define RT_USING_PWM
#define RT_USING_MTD_NAND
#define RT_MTD_NAND_DEBUG
#define RT_USING_RTC
#define RT_USING_ALARM
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_WDT
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_HWCRYPTO
#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto"
#define RT_HWCRYPTO_IV_MAX_SIZE 16
#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256
#define RT_HWCRYPTO_USING_AES
#define RT_HWCRYPTO_USING_AES_ECB
#define RT_HWCRYPTO_USING_AES_CBC
#define RT_HWCRYPTO_USING_AES_CFB
#define RT_HWCRYPTO_USING_AES_CTR
#define RT_HWCRYPTO_USING_AES_OFB
#define RT_HWCRYPTO_USING_SHA1
#define RT_HWCRYPTO_USING_SHA2
#define RT_HWCRYPTO_USING_SHA2_224
#define RT_HWCRYPTO_USING_SHA2_256
#define RT_HWCRYPTO_USING_SHA2_384
#define RT_HWCRYPTO_USING_SHA2_512
#define RT_HWCRYPTO_USING_RNG
/* Using USB */
#define RT_USING_USB
#define RT_USING_USB_HOST
#define RT_USBH_MSTORAGE
#define UDISK_MOUNTPOINT "/mnt/udisk"
#define RT_USING_USB_DEVICE
#define RT_USBD_THREAD_STACK_SZ 4096
#define USB_VENDOR_ID 0x0FFE
#define USB_PRODUCT_ID 0x0001
#define RT_USB_DEVICE_COMPOSITE
#define RT_USB_DEVICE_CDC
#define RT_USB_DEVICE_NONE
#define RT_USB_DEVICE_MSTORAGE
#define RT_VCOM_TASK_STK_SIZE 2048
#define RT_CDC_RX_BUFSIZE 128
#define RT_VCOM_SERNO "32021919830108"
#define RT_VCOM_SER_LEN 14
#define RT_VCOM_TX_TIMEOUT 1000
#define RT_USB_MSTORAGE_DISK_NAME "ramdisk1"
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_SOCKET
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
#define RT_USING_SAL
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.31.55"
#define RT_LWIP_GWADDR "192.168.31.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 16
#define RT_LWIP_PBUF_NUM 256
#define RT_LWIP_RAW_PCB_NUM 16
#define RT_LWIP_UDP_PCB_NUM 16
#define RT_LWIP_TCP_PCB_NUM 16
#define RT_LWIP_TCP_SEG_NUM 64
#define RT_LWIP_TCP_SND_BUF 16384
#define RT_LWIP_TCP_WND 65535
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 256
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 4096
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 256
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define RT_LWIP_NETIF_LOOPBACK
#define LWIP_NETIF_LOOPBACK 1
#define RT_LWIP_STATS
#define RT_LWIP_USING_PING
/* Utilities */
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
#define PKG_USING_NETUTILS
#define PKG_NETUTILS_TFTP
#define PKG_NETUTILS_IPERF
#define PKG_NETUTILS_NTP
#define NTP_USING_AUTO_SYNC
#define NTP_AUTO_SYNC_FIRST_DELAY 30
#define NTP_AUTO_SYNC_PERIOD 3600
#define NETUTILS_NTP_HOSTNAME "0.tw.pool.ntp.org"
#define NETUTILS_NTP_HOSTNAME2 "1.tw.pool.ntp.org"
#define NETUTILS_NTP_HOSTNAME3 "2.tw.pool.ntp.org"
#define PKG_USING_NETUTILS_LATEST_VERSION
#define PKG_NETUTILS_VER_NUM 0x99999
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
#define PKG_USING_WAVPLAYER
#define PKG_WP_USING_PLAY
#define PKG_WP_PLAY_DEVICE "sound0"
#define PKG_WP_USING_RECORD
#define PKG_WP_RECORD_DEVICE "sound0"
#define PKG_USING_WAVPLAYER_LATEST_VERSION
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
#define PKG_USING_DFS_UFFS
#define RT_USING_DFS_UFFS
#define RT_UFFS_ECC_MODE_3
#define RT_UFFS_ECC_MODE 3
#define PKG_USING_DFS_UFFS_LATEST_VERSION
#define PKG_USING_RAMDISK
#define PKG_USING_RAMDISK_LATEST_VERSION
/* peripheral libraries and drivers */
/* Kendryte SDK */
/* AI packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
#define PKG_USING_OPTPARSE
#define PKG_USING_OPTPARSE_LATEST_VERSION
/* Privated Packages of RealThread */
/* Network Utilities */
/* RT-Thread Smart */
/* Hardware Drivers Config */
/* On-chip Peripheral Drivers */
#define SOC_SERIES_NUC980
#define BSP_USE_STDDRIVER_SOURCE
#define BSP_USING_MMU
#define BSP_USING_PDMA
#define NU_PDMA_MEMFUN_ACTOR_MAX 2
#define BSP_USING_GPIO
#define BSP_USING_EMAC
#define BSP_USING_EMAC0
#define BSP_USING_RTC
#define NU_RTC_SUPPORT_IO_RW
#define NU_RTC_SUPPORT_MSH_CMD
#define BSP_USING_ADC
#define BSP_USING_TMR
#define BSP_USING_TIMER
#define BSP_USING_TMR0
#define BSP_USING_TIMER0
#define BSP_USING_TMR1
#define BSP_USING_TIMER1
#define BSP_USING_TMR2
#define BSP_USING_TIMER2
#define BSP_USING_TMR3
#define BSP_USING_TIMER3
#define BSP_USING_TMR4
#define BSP_USING_TIMER4
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_USING_UART1
#define BSP_USING_UART1_TX_DMA
#define BSP_USING_UART1_RX_DMA
#define BSP_USING_I2C
#define BSP_USING_I2C0
#define BSP_USING_I2C2
#define BSP_USING_SDH
#define BSP_USING_SDH1
#define NU_SDH_USING_PDMA
#define NU_SDH_HOTPLUG
#define BSP_USING_PWM
#define BSP_USING_PWM0
#define BSP_USING_SPI
#define BSP_USING_SPI_PDMA
#define BSP_USING_SPI0
#define BSP_USING_SPI0_PDMA
#define BSP_USING_SPI1_NONE
#define BSP_USING_I2S
#define NU_I2S_DMA_FIFO_SIZE 4096
#define BSP_USING_QSPI
#define BSP_USING_QSPI_PDMA
#define BSP_USING_QSPI0
#define BSP_USING_QSPI0_PDMA
#define BSP_USING_CRYPTO
#define BSP_USING_WDT
#define BSP_USING_USBD
#define BSP_USING_USBH
/* On-board Peripheral Drivers */
#define BSP_USING_CONSOLE
#define BOARD_USING_IP101GR
#define BOARD_USING_NAU8822
#define BOARD_USING_STORAGE_SDCARD
#define BOARD_USING_STORAGE_SPINAND
#define BOARD_USING_USB0_DEVICE_HOST
#define BOARD_USING_USB1_HOST
/* Board extended module drivers */
/* Nuvoton Packages Config */
#define NU_PKG_USING_UTILS
#define NU_PKG_USING_DEMO
#define NU_PKG_USING_NAU8822
#define NU_PKG_USING_SPINAND
#endif

373
bsp/nuvoton/nk-n9h30/.config
View File

@ -8,6 +8,7 @@
#
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@ -61,7 +62,7 @@ CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BSET_MODE is not set
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
@ -76,15 +77,20 @@ CONFIG_RT_USING_HEAP=y
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
CONFIG_RT_USING_INTERRUPT_INFO=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40101
CONFIG_ARCH_ARM=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARM_ARM9=y
CONFIG_RT_VER_NUM=0x50000
CONFIG_RT_USING_CACHE=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_MM_MMU=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_MMU=y
CONFIG_ARCH_ARM_ARM9=y
#
# RT-Thread Components
@ -141,7 +147,9 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
CONFIG_RT_USING_FAL=y
CONFIG_FAL_DEBUG_CONFIG=y
@ -149,12 +157,12 @@ CONFIG_FAL_DEBUG=1
CONFIG_FAL_PART_HAS_TABLE_CFG=y
CONFIG_FAL_USING_SFUD_PORT=y
CONFIG_FAL_USING_NOR_FLASH_DEV_NAME="norflash0"
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
@ -165,6 +173,7 @@ CONFIG_RT_USING_SERIAL_V1=y
CONFIG_RT_SERIAL_RB_BUFSZ=2048
CONFIG_RT_USING_CAN=y
# CONFIG_RT_CAN_USING_HDR is not set
# CONFIG_RT_CAN_USING_CANFD is not set
CONFIG_RT_USING_HWTIMER=y
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
@ -175,11 +184,15 @@ CONFIG_RT_USING_I2C_BITOPS=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
CONFIG_RT_USING_MTD_NAND=y
# CONFIG_RT_MTD_NAND_DEBUG is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
CONFIG_RT_USING_RTC=y
CONFIG_RT_USING_ALARM=y
# CONFIG_RT_USING_SOFT_RTC is not set
@ -204,11 +217,14 @@ CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048
# CONFIG_RT_USING_SENSOR is not set
CONFIG_RT_USING_TOUCH=y
# CONFIG_RT_TOUCH_PIN_IRQ is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
CONFIG_RT_USING_INPUT_CAPTURE=y
CONFIG_RT_INPUT_CAPTURE_RB_SIZE=100
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
@ -459,6 +475,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -466,6 +483,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
#
# security packages
@ -490,6 +508,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PARSON is not set
#
# XML: Extensible Markup Language
@ -515,10 +534,19 @@ CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL"
CONFIG_PKG_LVGL_THREAD_PRIO=20
CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096
CONFIG_PKG_LVGL_DISP_REFR_PERIOD=30
# CONFIG_PKG_USING_LVGL_SQUARELINE is not set
# CONFIG_PKG_LVGL_USING_EXAMPLES is not set
CONFIG_PKG_LVGL_USING_DEMOS=y
CONFIG_PKG_LVGL_VER_NUM=0x99999
CONFIG_PKG_LVGL_VER="latest"
CONFIG_PKG_LVGL_USING_V08034=y
# CONFIG_PKG_LVGL_USING_V08033 is not set
# CONFIG_PKG_LVGL_USING_V08032 is not set
# CONFIG_PKG_LVGL_USING_V08031 is not set
# CONFIG_PKG_LVGL_USING_V08030 is not set
# CONFIG_PKG_LVGL_USING_V08020 is not set
# CONFIG_PKG_LVGL_USING_V8_3_LATEST_VERSION is not set
# CONFIG_PKG_LVGL_USING_LATEST_VERSION is not set
CONFIG_PKG_LVGL_VER_NUM=0x08034
CONFIG_PKG_LVGL_VER="v8.3.4"
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
@ -564,7 +592,6 @@ CONFIG_PKG_LVGL_VER="latest"
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
@ -598,7 +625,8 @@ CONFIG_PKG_LVGL_VER="latest"
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
@ -611,14 +639,6 @@ CONFIG_PKG_LVGL_VER="latest"
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# POSIX extension functions
#
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
# CONFIG_PKG_USING_POSIX_STRINGS is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@ -642,10 +662,11 @@ CONFIG_PKG_LVGL_VER="latest"
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_PERF_COUNTER is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
@ -679,17 +700,93 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@ -700,6 +797,11 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
#
# Kendryte SDK
#
# CONFIG_PKG_USING_K210_SDK is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_MULTI_INFRARED is not set
@ -707,12 +809,9 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
@ -727,7 +826,6 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
@ -758,8 +856,11 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
#
# AI packages
@ -774,6 +875,12 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
@ -825,7 +932,6 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
@ -835,6 +941,213 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
#
# Hardware Drivers Config
@ -958,9 +1271,9 @@ CONFIG_BOARD_USING_ADCTOUCH=y
#
CONFIG_NU_PKG_USING_UTILS=y
# CONFIG_NU_PKG_USING_DEMO is not set
# CONFIG_NU_PKG_USING_LVGL is not set
# CONFIG_NU_PKG_USING_BMX055 is not set
# CONFIG_NU_PKG_USING_MAX31875 is not set
# CONFIG_NU_PKG_USING_NCT7717U is not set
# CONFIG_NU_PKG_USING_NAU88L25 is not set
CONFIG_NU_PKG_USING_NAU8822=y
# CONFIG_NU_PKG_USING_DA9062 is not set
@ -971,5 +1284,3 @@ CONFIG_NU_PKG_USING_NAU8822=y
CONFIG_NU_PKG_USING_ADC_TOUCH=y
# CONFIG_NU_PKG_USING_ADC_TOUCH_SW is not set
# CONFIG_NU_PKG_USING_SPINAND is not set
CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest."
CONFIG_BOARD_USE_UTEST=y

4
bsp/nuvoton/nk-n9h30/applications/SConscript
View File

@ -1,15 +1,11 @@
from building import *
import os
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
list = os.listdir(cwd)
for item in list:
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
group = group + SConscript(os.path.join(item, 'SConscript'))
Return('group')

9
bsp/nuvoton/nk-n9h30/applications/lvgl/lv_conf.h
View File

@ -14,9 +14,8 @@
#include "rtconfig.h"
#if defined(SOC_SERIES_N9H30)
#define LV_USE_GPU_N9H30_GE2D 1
//#define LV_USE_ANTI_TEARING 1
//#define LV_DISP_DEF_REFR_PERIOD 16
//#define LV_DISP_DEF_REFR_PERIOD 30
#ifndef BIT31
#define BIT31 (0x80000000) ///< Bit 31 mask of an 32 bit integer
@ -25,8 +24,6 @@
#define IS_CACHEABLE_VRAM(addr) !((uint32_t)addr & BIT31)
#endif
#define LV_VERSION_EQUAL(x,y,z) (x == LVGL_VERSION_MAJOR && y==LVGL_VERSION_MINOR && z==LVGL_VERSION_PATCH )
#define LV_COLOR_DEPTH BSP_LCD_BPP
#define LV_HOR_RES_MAX BSP_LCD_WIDTH
#define LV_VER_RES_MAX BSP_LCD_HEIGHT
@ -36,7 +33,7 @@
#define LV_USE_PERF_MONITOR 1
//#define CONFIG_LV_LOG_LEVEL LV_LOG_LEVEL_TRACE
//#define LV_USE_DEMO_RTT_MUSIC 1
#define LV_USE_DEMO_RTT_MUSIC 1
#if LV_USE_DEMO_RTT_MUSIC
#define LV_COLOR_SCREEN_TRANSP 1
#define LV_DEMO_RTT_MUSIC_AUTO_PLAY 1
@ -46,7 +43,7 @@
#endif
/* Please comment LV_USE_DEMO_RTT_MUSIC declaration before un-comment below */
#define LV_USE_DEMO_WIDGETS 1
//#define LV_USE_DEMO_WIDGETS 1
//#define LV_USE_DEMO_BENCHMARK 1
#endif

7
bsp/nuvoton/nk-n9h30/applications/lvgl/lv_demo.c
View File

@ -17,16 +17,15 @@ void lv_user_gui_init(void)
#if LV_USE_DEMO_BENCHMARK
extern void lv_demo_benchmark(void);
lv_demo_benchmark();
#endif
#if LV_USE_DEMO_WIDGETS
#elif LV_USE_DEMO_WIDGETS
extern void lv_demo_widgets(void);
lv_demo_widgets();
#endif
#if LV_USE_DEMO_MUSIC || LV_USE_DEMO_RTT_MUSIC
#elif (LV_USE_DEMO_MUSIC || LV_USE_DEMO_RTT_MUSIC)
extern void lv_demo_music(void);
lv_demo_music();
#endif
}

64
bsp/nuvoton/nk-n9h30/applications/lvgl/lv_gpu_n9h30_ge2d.c
View File

@ -17,8 +17,6 @@
*********************/
#include <lvgl.h>
#if LV_USE_GPU_N9H30_GE2D && LV_VERSION_CHECK(8, 2, 0)
#include "lv_gpu_n9h30_ge2d.h"
#include "nu_2d.h"
#include "mmu.h"
@ -119,7 +117,10 @@ void lv_draw_n9h30_ge2d_blend(lv_draw_ctx_t *draw_ctx, const lv_draw_sw_blend_ds
}
}
if (!done) lv_draw_sw_blend_basic(draw_ctx, dsc);
if (!done)
{
lv_draw_sw_blend_basic(draw_ctx, dsc);
}
}
static void lv_draw_n9h30_ge2d_blend_fill(lv_color_t *dest_buf, lv_coord_t dest_stride, const lv_area_t *fill_area,
@ -130,7 +131,7 @@ static void lv_draw_n9h30_ge2d_blend_fill(lv_color_t *dest_buf, lv_coord_t dest_
lv_color_t *start_buf = dest_buf - (fill_area->y1 * dest_stride) - fill_area->x1;
//rt_kprintf("[blend_fill %d %08x] %dx%d %d %d\n", lv_area_get_size(fill_area), dest_buf, fill_area_w, fill_area_h, fill_area->x1, fill_area->y1 );
// rt_kprintf("[blend_fill %d %08x] %dx%d %d %d\n", lv_area_get_size(fill_area), dest_buf, fill_area_w, fill_area_h, fill_area->x1, fill_area->y1 );
if (IS_CACHEABLE_VRAM(dest_buf))
mmu_clean_invalidated_dcache((uint32_t)dest_buf, sizeof(lv_color_t) * (dest_stride * fill_area_h + fill_area_w));
@ -153,34 +154,51 @@ static void lv_draw_n9h30_ge2d_blend_fill(lv_color_t *dest_buf, lv_coord_t dest_
static void lv_draw_n9h30_ge2d_blend_map(lv_color_t *dest_buf, const lv_area_t *dest_area, lv_coord_t dest_stride,
const lv_color_t *src_buf, lv_coord_t src_stride, lv_opa_t opa)
{
/*Simple copy*/
int32_t dest_x = dest_area->x1;
int32_t dest_y = dest_area->y1;
int32_t dest_w = lv_area_get_width(dest_area);
int32_t dest_h = lv_area_get_height(dest_area);
const lv_color_t *dest_start_buf = dest_buf - (dest_area->y1 * dest_stride) - dest_area->x1;
//rt_kprintf("[blend_map %d %08x -> %08x] (x:%d y:%d, %dx%d) <stride src:%d dst:%d>\n", lv_area_get_size(dest_area), src_buf, dest_buf, dest_x, dest_y, dest_w, dest_h, src_stride, dest_stride);
// Enter GE2D ->
ge2dInit(sizeof(lv_color_t) * 8, dest_stride, dest_area->y2, (void *)dest_start_buf);
if (opa >= LV_OPA_MAX)
if (!IS_CACHEABLE_VRAM(dest_buf))
{
ge2dBitblt_SetAlphaMode(0, 0, 0);
ge2dBitblt_SetDrawMode(0, 0, 0);
const lv_color_t *dest_start_buf = dest_buf - (dest_area->y1 * dest_stride) - dest_area->x1;
int32_t dest_x = dest_area->x1;
int32_t dest_y = dest_area->y1;
// Enter GE2D ->
ge2dInit(sizeof(lv_color_t) * 8, dest_stride, dest_area->y2, (void *)dest_start_buf);
if (opa >= LV_OPA_MAX)
{
ge2dBitblt_SetAlphaMode(0, 0, 0);
ge2dBitblt_SetDrawMode(0, 0, 0);
}
else
{
ge2dBitblt_SetAlphaMode(1, opa, opa);
}
if (IS_CACHEABLE_VRAM(src_buf))
mmu_clean_dcache((uint32_t)src_buf, sizeof(lv_color_t) * (src_stride * dest_h + dest_w));
ge2dSpriteBlt_Screen(dest_x, dest_y, dest_w, dest_h, (void *)src_buf);
// -> Leave GE2D
}
else
{
ge2dBitblt_SetAlphaMode(1, opa, opa);
int32_t x, y;
/*Simple copy*/
for (y = 0; y < dest_h; y++)
{
for (x = 0; x < dest_w; x++)
{
dest_buf[x] = src_buf[x];
}
dest_buf += dest_stride;
src_buf += src_stride;
}
}
// flush
mmu_clean_dcache((uint32_t)src_buf, sizeof(lv_color_t) * (src_stride * dest_h + dest_w));
ge2dSpriteBlt_Screen(dest_x, dest_y, dest_w, dest_h, (void *)src_buf);
// -> Leave GE2D
}
void lv_gpu_n9h30_ge2d_wait_cb(lv_draw_ctx_t *draw_ctx)
@ -191,5 +209,3 @@ void lv_gpu_n9h30_ge2d_wait_cb(lv_draw_ctx_t *draw_ctx)
/**********************
* STATIC FUNCTIONS
**********************/
#endif // #if (LV_USE_GPU_N9H30_GE2D && LV_VERSION_CHECK(8, 2, 0))

4
bsp/nuvoton/nk-n9h30/applications/lvgl/lv_gpu_n9h30_ge2d.h
View File

@ -21,8 +21,6 @@ extern "C" {
#include "../../hal/lv_hal_disp.h"
#include "../sw/lv_draw_sw.h"
#if LV_USE_GPU_N9H30_GE2D && LV_VERSION_CHECK(8, 2, 0)
/*********************
* DEFINES
*********************/
@ -54,8 +52,6 @@ void lv_gpu_n9h30_ge2d_wait_cb(lv_draw_ctx_t *draw_ctx);
* MACROS
**********************/
#endif /*#if LV_USE_GPU_N9H30_GE2D && LV_VERSION_CHECK(8, 2, 0)*/
#ifdef __cplusplus
} /*extern "C"*/
#endif

119
bsp/nuvoton/nk-n9h30/applications/lvgl/lv_port_disp.c
View File

@ -8,20 +8,20 @@
* 2021-12-17 Wayne The first version
*/
#include <lvgl.h>
#include "nu_2d.h"
#include "mmu.h"
#if (LV_USE_GPU_N9H30_GE2D && LV_VERSION_CHECK(8, 2, 0))
#include "lv_gpu_n9h30_ge2d.h"
#endif
#include "lv_gpu_n9h30_ge2d.h"
#define LOG_TAG "lvgl.disp"
#define DBG_ENABLE
#define DBG_SECTION_NAME LOG_TAG
#define DBG_LEVEL DBG_ERROR
#define DBG_LEVEL DBG_INFO
#define DBG_COLOR
#include <rtdbg.h>
#if !defined(NU_PKG_LVGL_RENDERING_LAYER)
#define NU_PKG_LVGL_RENDERING_LAYER "lcd"
#endif
/*A static or global variable to store the buffers*/
static lv_disp_draw_buf_t disp_buf;
static rt_device_t lcd_device = 0;
@ -32,6 +32,8 @@ static void *buf3_next = RT_NULL;
static uint32_t u32FirstFlush = 0;
static uint32_t LV_USE_GPU_N9H30_GE2D = 1;
static void nu_antitearing(lv_disp_draw_buf_t *draw_buf, lv_color_t *color_p)
{
if (buf3_next)
@ -74,11 +76,15 @@ static void nu_flush_full_refresh(lv_disp_drv_t *disp_drv, const lv_area_t *area
static void nu_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t *color_p)
{
#if (LV_USE_GPU_N9H30_GE2D==1)
int32_t area_w = lv_area_get_width(area);
int32_t area_h = lv_area_get_height(area);
lv_draw_sw_blend_dsc_t blend_flush = {0};
lv_draw_ctx_t draw_flush = {0};
lv_area_t flush_area = {0, 0, info.width - 1, info.height - 1 };
//rt_kprintf("[nu_flush %d %08x] %dx%d %d %d\n", lv_area_get_size(area), color_p, area_w, area_h, area->x1, area->y1 );
blend_flush.blend_area = area;
blend_flush.src_buf = color_p;
blend_flush.mask_buf = NULL;
@ -91,23 +97,6 @@ static void nu_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t
lv_draw_n9h30_ge2d_blend(&draw_flush, (const lv_draw_sw_blend_dsc_t *)&blend_flush);
#else
int32_t flush_area_w = lv_area_get_width(area);
int32_t flush_area_h = lv_area_get_height(area);
//if ( flush_area_w&0x3 != 0 )
// rt_kprintf("[%s %08x] %dx%d %d %d\n", __func__, color_p, flush_area_w, flush_area_h, area->x1, area->y1 );
/* Update dirty region. */
// Enter GE2D ->
ge2dInit(sizeof(lv_color_t) * 8, info.width, info.height, (void *)info.framebuffer);
ge2dBitblt_SetAlphaMode(-1, 0, 0);
ge2dBitblt_SetDrawMode(-1, 0, 0);
ge2dSpriteBlt_Screen(area->x1, area->y1, flush_area_w, flush_area_h, (void *)color_p);
// -> Leave GE2D
#endif
if (!u32FirstFlush)
{
/* Enable backlight at first flushing. */
@ -118,52 +107,9 @@ static void nu_flush(lv_disp_drv_t *disp_drv, const lv_area_t *area, lv_color_t
lv_disp_flush_ready(disp_drv);
}
#if LV_VERSION_EQUAL(8, 1, 0)
static void nu_fill_cb(struct _lv_disp_drv_t *disp_drv, lv_color_t *dest_buf, lv_coord_t dest_width,
const lv_area_t *fill_area, lv_color_t color)
{
int32_t fill_area_w = lv_area_get_width(fill_area);
int32_t fill_area_h = lv_area_get_height(fill_area);
if (lv_area_get_size(fill_area) < 3600)
{
/*Software filling*/
int y;
lv_color_t *disp_buf_first = dest_buf + dest_width * fill_area->y1 + fill_area->x1;
for (y = 0; y < fill_area_h; y++)
{
lv_color_fill(disp_buf_first, color, fill_area_w);
disp_buf_first += dest_width;
}
}
else
{
//rt_kprintf("[blend_fill %d %08x] %dx%d %d %d\n", lv_area_get_size(fill_area), dest_buf, fill_area_w, fill_area_h, fill_area->x1, fill_area->y1 );
if (IS_CACHEABLE_VRAM(dest_buf))
mmu_clean_invalidated_dcache((uint32_t)dest_buf, sizeof(lv_color_t) * (dest_width * fill_area_h + fill_area_w));
/*Hardware filling*/
// Enter GE2D ->
ge2dInit(sizeof(lv_color_t) * 8, fill_area_w, fill_area_h, (void *)dest_buf);
ge2dClip_SetClip(fill_area->x1, fill_area->y1, fill_area->x2, fill_area->y2);
if (sizeof(lv_color_t) == 4)
ge2dFill_Solid(fill_area->x1, fill_area->y1, fill_area_w, fill_area_h, color.full);
else if (sizeof(lv_color_t) == 2)
ge2dFill_Solid_RGB565(fill_area->x1, fill_area->y1, fill_area_w, fill_area_h, color.full);
ge2dClip_SetClip(-1, 0, 0, 0);
// -> Leave GE2D
}
}
#endif
void nu_perf_monitor(struct _lv_disp_drv_t *disp_drv, uint32_t time, uint32_t px)
{
rt_kprintf("Elapsed: %dms, Pixel: %d, Bytes:%d, %d%\n", time, px, px * sizeof(lv_color_t), px * 100 / disp_drv->draw_buf->size);
LOG_I("Elapsed: %dms, Pixel: %d, Bytes:%d, %d%\n", time, px, px * sizeof(lv_color_t), px * 100 / disp_drv->draw_buf->size);
}
void lv_port_disp_init(void)
@ -173,13 +119,19 @@ void lv_port_disp_init(void)
void *buf2 = RT_NULL;
uint32_t u32FBSize;
lcd_device = rt_device_find("lcd");
if (lcd_device == 0)
lcd_device = rt_device_find(NU_PKG_LVGL_RENDERING_LAYER);
if (lcd_device == RT_NULL)
{
LOG_E("error!");
return;
}
if (!LV_VERSION_CHECK(8, 3, 0))
{
LV_USE_GPU_N9H30_GE2D = 0;
}
LOG_I("LVGL: %s drawing using 2DGE", LV_USE_GPU_N9H30_GE2D ? "Enabled" : "Disabled");
/* get framebuffer address */
result = rt_device_control(lcd_device, RTGRAPHIC_CTRL_GET_INFO, &info);
if (result != RT_EOK)
@ -205,25 +157,22 @@ void lv_port_disp_init(void)
#if (LV_USE_ANTI_TEARING==1)
disp_drv.full_refresh = 1;
#endif
LOG_I("LVGL: %s anti-tearing", disp_drv.full_refresh ? "Enabled" : "Disabled");
if (disp_drv.full_refresh)
{
#if (LV_USE_GPU_N9H30_GE2D==1)
buf1 = (void *)info.framebuffer; // Use Non-cacheable VRAM
#else
buf1 = (void *)((uint32_t)info.framebuffer & ~BIT31); // Use Cacheable VRAM
#endif
buf2 = (void *)((uint32_t)buf1 + u32FBSize);
buf3_next = (void *)((uint32_t)buf2 + u32FBSize);
rt_kprintf("LVGL: Use triple screen-sized buffers(full_refresh) - buf1@%08x, buf2@%08x, buf3_next@%08x\n", buf1, buf2, buf3_next);
LOG_I("LVGL: Use triple screen-sized buffers(full_refresh) - buf1@%08x, buf2@%08x, buf3_next@%08x", buf1, buf2, buf3_next);
disp_drv.flush_cb = nu_flush_full_refresh;
}
else
{
buf1 = (void *)(((uint32_t)info.framebuffer) + u32FBSize);
buf1 = (void *)(((uint32_t)info.framebuffer & ~BIT31) + u32FBSize); // Use Cacheable VRAM
buf2 = (void *)((uint32_t)buf1 + u32FBSize);
rt_kprintf("LVGL: Use two screen-sized buffers - buf1@%08x, buf2@%08x\n", buf1, buf2);
LOG_I("LVGL: Use two screen-sized buffers - buf1@%08x, buf2@%08x", buf1, buf2);
rt_device_control(lcd_device, RTGRAPHIC_CTRL_PAN_DISPLAY, info.framebuffer);
disp_drv.flush_cb = nu_flush;
@ -242,16 +191,12 @@ void lv_port_disp_init(void)
/*Set a display buffer*/
disp_drv.draw_buf = &disp_buf;
#if LV_VERSION_EQUAL(8, 1, 0)
/*Fill a memory with a color (GPU only)*/
disp_drv.gpu_fill_cb = nu_fill_cb;
#endif
#if (LV_USE_GPU_N9H30_GE2D && LV_VERSION_CHECK(8, 2, 0))
disp_drv.draw_ctx_init = lv_draw_n9h30_ge2d_ctx_init;
disp_drv.draw_ctx_deinit = lv_draw_n9h30_ge2d_ctx_init;
disp_drv.draw_ctx_size = sizeof(lv_draw_n9h30_ge2d_ctx_t);
#endif
if (LV_USE_GPU_N9H30_GE2D)
{
disp_drv.draw_ctx_init = lv_draw_n9h30_ge2d_ctx_init;
disp_drv.draw_ctx_deinit = lv_draw_n9h30_ge2d_ctx_init;
disp_drv.draw_ctx_size = sizeof(lv_draw_n9h30_ge2d_ctx_t);
}
/*Called after every refresh cycle to tell the rendering and flushing time + the number of flushed pixels*/
//disp_drv.monitor_cb = nu_perf_monitor;

23
bsp/nuvoton/nk-n9h30/applications/lvgl/lv_port_disp.h
View File

@ -1,23 +0,0 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-18 Meco Man The first version
*/
#ifndef LV_PORT_DISP_H
#define LV_PORT_DISP_H
#ifdef __cplusplus
extern "C" {
#endif
void lv_port_disp_init(void);
#ifdef __cplusplus
} /*extern "C"*/
#endif
#endif

28
bsp/nuvoton/nk-n9h30/applications/lvgl/lv_port_indev.h
View File

@ -1,28 +0,0 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-18 Meco Man The first version
*/
#ifndef LV_PORT_INDEV_H
#define LV_PORT_INDEV_H
#ifdef __cplusplus
extern "C" {
#endif
#include <lv_hal_indev.h>
extern lv_indev_t *button_indev;
void lv_port_indev_init(void);
void lv_port_indev_input(rt_int16_t x, rt_int16_t y, lv_indev_state_t state);
#ifdef __cplusplus
} /*extern "C"*/
#endif
#endif

25
bsp/nuvoton/nk-n9h30/applications/mnt.c
View File

@ -12,6 +12,8 @@
#include <rtthread.h>
#if defined(RT_USING_DFS)
#define LOG_TAG "mnt"
#define DBG_ENABLE
#define DBG_SECTION_NAME "mnt"
@ -160,9 +162,10 @@ exit_mkdir_p:
#if defined(PKG_USING_DFS_YAFFS) && defined(RT_USING_DFS_MNTTABLE)
#include "yaffs_guts.h"
void yaffs_dev_init(void)
int yaffs_dev_init(void)
{
int i;
for (i = 0; i < sizeof(mount_table) / sizeof(struct dfs_mount_tbl); i++)
{
if (mount_table[i].filesystemtype && !rt_strcmp(mount_table[i].filesystemtype, "yaffs"))
@ -170,11 +173,26 @@ void yaffs_dev_init(void)
struct rt_mtd_nand_device *psMtdNandDev = RT_MTD_NAND_DEVICE(rt_device_find(mount_table[i].device_name));
if (psMtdNandDev)
{
LOG_I("yaffs start [%s].", mount_table[i].device_name);
yaffs_start_up(psMtdNandDev, (const char *)mount_table[i].path);
LOG_I("dfs mount [%s].", mount_table[i].device_name);
if (dfs_mount(mount_table[i].device_name,
mount_table[i].path,
mount_table[i].filesystemtype,
mount_table[i].rwflag,
mount_table[i].data) != 0)
{
LOG_E("mount fs[%s] on %s failed.", mount_table[i].filesystemtype, mount_table[i].path);
}
}
}
}
return 0;
}
INIT_APP_EXPORT(yaffs_dev_init);
#endif
/* Initialize the filesystem */
@ -246,13 +264,10 @@ int filesystem_init(void)
}
#endif
#if defined(PKG_USING_DFS_YAFFS) && defined(RT_USING_DFS_MNTTABLE)
yaffs_dev_init();
#endif
exit_filesystem_init:
return -result;
}
INIT_ENV_EXPORT(filesystem_init);
#endif
#endif

5
bsp/nuvoton/nk-n9h30/linking_scripts/n9h30.ld
View File

@ -53,6 +53,11 @@ SECTIONS
. = ALIGN(4);
}
. = ALIGN(4);
__exidx_start = .;
.ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
__exidx_end = .;
. = ALIGN(4);
.rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }

6990
bsp/nuvoton/nk-n9h30/project.uvproj
View File

File diff suppressed because it is too large Load Diff

422
bsp/nuvoton/nk-n9h30/rtconfig.h
View File

@ -1,422 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 2048
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_SIGNALS
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_MEMTRACE
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_INTERRUPT_INFO
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40101
#define ARCH_ARM
#define ARCH_ARM_ARM9
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 16
#define DFS_FILESYSTEM_TYPES_MAX 16
#define DFS_FD_MAX 64
#define RT_USING_DFS_MNTTABLE
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 8
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_FAL
#define FAL_DEBUG_CONFIG
#define FAL_DEBUG 1
#define FAL_PART_HAS_TABLE_CFG
#define FAL_USING_SFUD_PORT
#define FAL_USING_NOR_FLASH_DEV_NAME "norflash0"
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_RB_BUFSZ 2048
#define RT_USING_CAN
#define RT_USING_HWTIMER
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
#define RT_USING_ADC
#define RT_USING_PWM
#define RT_USING_MTD_NAND
#define RT_USING_RTC
#define RT_USING_ALARM
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_SFUD_USING_QSPI
#define RT_SFUD_SPI_MAX_HZ 50000000
#define RT_USING_WDT
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 4096
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 2048
#define RT_USING_TOUCH
#define RT_USING_INPUT_CAPTURE
#define RT_INPUT_CAPTURE_RB_SIZE 100
/* Using USB */
#define RT_USING_USB
#define RT_USING_USB_HOST
#define RT_USBH_MSTORAGE
#define UDISK_MOUNTPOINT "/mnt/udisk"
#define RT_USING_USB_DEVICE
#define RT_USBD_THREAD_STACK_SZ 4096
#define USB_VENDOR_ID 0x0FFE
#define USB_PRODUCT_ID 0x0001
#define RT_USB_DEVICE_COMPOSITE
#define RT_USB_DEVICE_CDC
#define RT_USB_DEVICE_NONE
#define RT_USB_DEVICE_MSTORAGE
#define RT_VCOM_TASK_STK_SIZE 512
#define RT_CDC_RX_BUFSIZE 128
#define RT_VCOM_SERNO "32021919830108"
#define RT_VCOM_SER_LEN 14
#define RT_VCOM_TX_TIMEOUT 1000
#define RT_USB_MSTORAGE_DISK_NAME "ramdisk1"
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
#define RT_USING_SAL
#define SAL_INTERNET_CHECK
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP203
#define RT_USING_LWIP_VER_NUM 0x20003
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 32
#define RT_LWIP_PBUF_NUM 256
#define RT_LWIP_RAW_PCB_NUM 32
#define RT_LWIP_UDP_PCB_NUM 32
#define RT_LWIP_TCP_PCB_NUM 32
#define RT_LWIP_TCP_SEG_NUM 256
#define RT_LWIP_TCP_SND_BUF 32768
#define RT_LWIP_TCP_WND 10240
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define RT_LWIP_NETIF_LOOPBACK
#define LWIP_NETIF_LOOPBACK 1
#define RT_LWIP_STATS
#define RT_LWIP_USING_PING
/* Utilities */
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
#define PKG_USING_LVGL
#define PKG_LVGL_THREAD_PRIO 20
#define PKG_LVGL_THREAD_STACK_SIZE 4096
#define PKG_LVGL_DISP_REFR_PERIOD 30
#define PKG_LVGL_USING_DEMOS
#define PKG_LVGL_USING_V08031
#define PKG_LVGL_VER_NUM 0x08031
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
#define PKG_USING_RAMDISK
#define PKG_USING_RAMDISK_LATEST_VERSION
/* peripheral libraries and drivers */
/* Kendryte SDK */
/* AI packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
/* Privated Packages of RealThread */
/* Network Utilities */
/* RT-Thread Smart */
/* Hardware Drivers Config */
/* On-chip Peripheral Drivers */
#define SOC_SERIES_N9H30
#define BSP_USING_MMU
#define BSP_USING_GPIO
#define BSP_USING_EMAC
#define BSP_USING_EMAC0
#define BSP_USING_EMAC1
#define BSP_USING_RTC
#define BSP_USING_ADC
#define BSP_USING_ADC_TOUCH
#define BSP_USING_ETMR
#define BSP_USING_ETIMER
#define BSP_USING_ETIMER_CAPTURE
#define BSP_USING_ETMR0
#define BSP_USING_ETIMER0
#define BSP_USING_ETMR1
#define BSP_USING_ETIMER1
#define BSP_USING_ETMR2
#define BSP_USING_ETIMER2_CAPTURE
#define BSP_USING_ETMR3
#define BSP_USING_ETIMER3_CAPTURE
#define BSP_USING_TMR
#define BSP_USING_TIMER
#define BSP_USING_TIMER0
#define BSP_USING_TIMER1
#define BSP_USING_TIMER2
#define BSP_USING_TIMER3
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_USING_I2C
#define BSP_USING_I2C0
#define BSP_USING_SDH
#define BSP_USING_SDH0
#define BSP_USING_SDH1
#define NU_SDH_HOTPLUG
#define BSP_USING_CAN
#define BSP_USING_CAN0
#define BSP_USING_PWM
#define BSP_USING_PWM0
#define BSP_USING_QSPI
#define BSP_USING_QSPI0
#define BSP_USING_QSPI1_NONE
#define BSP_USING_I2S
#define NU_I2S_DMA_FIFO_SIZE 2048
#define BSP_USING_WDT
#define BSP_USING_EBI
#define BSP_USING_VPOST
#define LCM_USING_FW070TFT
#define VPOST_USING_LCD_IDX 3
#define BSP_LCD_BPP 32
#define BSP_LCD_WIDTH 800
#define BSP_LCD_HEIGHT 480
#define BSP_USING_VPOST_OSD
#define BSP_USING_USBD
#define BSP_USING_USBH
/* On-board Peripheral Drivers */
#define BSP_USING_CONSOLE
#define BOARD_USING_IP101GR
#define BOARD_USING_NAU8822
#define BOARD_USING_STORAGE_SDCARD
#define BOARD_USING_STORAGE_SPIFLASH
#define BOARD_USING_BUZZER
#define BOARD_USING_USB0_DEVICE_HOST
#define BOARD_USING_USB1_HOST
/* Board extended module drivers */
#define BOARD_USING_LCM
#define BOARD_USING_LCM_FW070TFT_WVGA
#define BOARD_USING_ADCTOUCH
/* Nuvoton Packages Config */
#define NU_PKG_USING_UTILS
#define NU_PKG_USING_NAU8822
#define NU_PKG_USING_ADC_TOUCH
#endif

4
bsp/nuvoton/nk-n9h30/rtconfig.py
View File

@ -23,8 +23,8 @@ elif CROSS_TOOL == 'keil':
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
#BUILD = ''
#BUILD = 'debug'
BUILD = ''
CORE = 'arm926ej-s'
MAP_FILE = 'rtthread_n9h30.map'

336
bsp/nuvoton/nk-rtu980/.config
View File

@ -8,6 +8,7 @@
#
CONFIG_RT_NAME_MAX=16
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
@ -61,7 +62,7 @@ CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BSET_MODE is not set
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
@ -76,15 +77,20 @@ CONFIG_RT_USING_HEAP=y
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=256
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x50000
CONFIG_ARCH_ARM=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARM_ARM9=y
CONFIG_RT_USING_CACHE=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_MM_MMU=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_MMU=y
CONFIG_ARCH_ARM_ARM9=y
#
# RT-Thread Components
@ -141,7 +147,9 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
CONFIG_RT_USING_FAL=y
CONFIG_FAL_DEBUG_CONFIG=y
@ -149,12 +157,12 @@ CONFIG_FAL_DEBUG=1
CONFIG_FAL_PART_HAS_TABLE_CFG=y
CONFIG_FAL_USING_SFUD_PORT=y
CONFIG_FAL_USING_NOR_FLASH_DEV_NAME="norflash0"
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
@ -176,10 +184,14 @@ CONFIG_RT_USING_I2C_BITOPS=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
CONFIG_RT_USING_SOFT_RTC=y
@ -200,6 +212,7 @@ CONFIG_RT_USING_WDT=y
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
CONFIG_RT_USING_HWCRYPTO=y
CONFIG_RT_HWCRYPTO_DEFAULT_NAME="hwcryto"
CONFIG_RT_HWCRYPTO_IV_MAX_SIZE=16
@ -226,7 +239,9 @@ CONFIG_RT_HWCRYPTO_USING_RNG=y
# CONFIG_RT_HWCRYPTO_USING_BIGNUM is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
@ -430,7 +445,6 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_NETUTILS_LATEST_VERSION is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
@ -478,6 +492,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -485,6 +500,7 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
#
# security packages
@ -576,7 +592,6 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
@ -610,8 +625,8 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
@ -647,7 +662,6 @@ CONFIG_UTEST_THR_PRIORITY=20
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
@ -686,19 +700,93 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@ -721,12 +809,9 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
@ -741,7 +826,6 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
@ -772,10 +856,11 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
#
# AI packages
@ -790,6 +875,12 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
@ -845,7 +936,6 @@ CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
@ -855,6 +945,213 @@ CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
#
# Hardware Drivers Config
@ -962,7 +1259,6 @@ CONFIG_BOARD_USING_IP101GR=y
#
CONFIG_NU_PKG_USING_UTILS=y
CONFIG_NU_PKG_USING_DEMO=y
# CONFIG_NU_PKG_USING_LVGL is not set
# CONFIG_NU_PKG_USING_BMX055 is not set
# CONFIG_NU_PKG_USING_MAX31875 is not set
# CONFIG_NU_PKG_USING_NCT7717U is not set
@ -975,5 +1271,3 @@ CONFIG_NU_PKG_USING_DEMO=y
# CONFIG_NU_PKG_USING_TPC is not set
# CONFIG_NU_PKG_USING_ADC_TOUCH is not set
# CONFIG_NU_PKG_USING_SPINAND is not set
CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest."
CONFIG_BOARD_USE_UTEST=y

2284
bsp/nuvoton/nk-rtu980/project.uvproj
View File

File diff suppressed because it is too large Load Diff

427
bsp/nuvoton/nk-rtu980/rtconfig.h
View File

@ -1,427 +0,0 @@
#ifndef RT_CONFIG_H__
#define RT_CONFIG_H__
/* Automatically generated file; DO NOT EDIT. */
/* RT-Thread Configuration */
/* RT-Thread Kernel */
#define RT_NAME_MAX 16
#define RT_ALIGN_SIZE 4
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 2048
/* kservice optimization */
#define RT_DEBUG
#define RT_DEBUG_COLOR
/* Inter-Thread communication */
#define RT_USING_SEMAPHORE
#define RT_USING_MUTEX
#define RT_USING_EVENT
#define RT_USING_MAILBOX
#define RT_USING_MESSAGEQUEUE
#define RT_USING_SIGNALS
/* Memory Management */
#define RT_USING_MEMPOOL
#define RT_USING_SMALL_MEM
#define RT_USING_MEMHEAP
#define RT_MEMHEAP_FAST_MODE
#define RT_USING_SMALL_MEM_AS_HEAP
#define RT_USING_MEMTRACE
#define RT_USING_HEAP
/* Kernel Device Object */
#define RT_USING_DEVICE
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 256
#define RT_CONSOLE_DEVICE_NAME "uart0"
#define RT_VER_NUM 0x40101
#define ARCH_ARM
#define ARCH_ARM_ARM9
/* RT-Thread Components */
#define RT_USING_COMPONENTS_INIT
#define RT_USING_USER_MAIN
#define RT_MAIN_THREAD_STACK_SIZE 2048
#define RT_MAIN_THREAD_PRIORITY 10
#define RT_USING_MSH
#define RT_USING_FINSH
#define FINSH_USING_MSH
#define FINSH_THREAD_NAME "tshell"
#define FINSH_THREAD_PRIORITY 20
#define FINSH_THREAD_STACK_SIZE 4096
#define FINSH_USING_HISTORY
#define FINSH_HISTORY_LINES 5
#define FINSH_USING_SYMTAB
#define FINSH_CMD_SIZE 80
#define MSH_USING_BUILT_IN_COMMANDS
#define FINSH_USING_DESCRIPTION
#define FINSH_ARG_MAX 10
#define RT_USING_DFS
#define DFS_USING_POSIX
#define DFS_USING_WORKDIR
#define DFS_FILESYSTEMS_MAX 16
#define DFS_FILESYSTEM_TYPES_MAX 16
#define DFS_FD_MAX 64
#define RT_USING_DFS_MNTTABLE
#define RT_USING_DFS_ELMFAT
/* elm-chan's FatFs, Generic FAT Filesystem Module */
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_WORD_ACCESS
#define RT_DFS_ELM_USE_LFN_3
#define RT_DFS_ELM_USE_LFN 3
#define RT_DFS_ELM_LFN_UNICODE_0
#define RT_DFS_ELM_LFN_UNICODE 0
#define RT_DFS_ELM_MAX_LFN 255
#define RT_DFS_ELM_DRIVES 8
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
#define RT_DFS_ELM_REENTRANT
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
#define RT_USING_DFS_DEVFS
#define RT_USING_FAL
#define FAL_DEBUG_CONFIG
#define FAL_DEBUG 1
#define FAL_PART_HAS_TABLE_CFG
#define FAL_USING_SFUD_PORT
#define FAL_USING_NOR_FLASH_DEV_NAME "norflash0"
/* Device Drivers */
#define RT_USING_DEVICE_IPC
#define RT_USING_SYSTEM_WORKQUEUE
#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
#define RT_USING_SERIAL
#define RT_USING_SERIAL_V1
#define RT_SERIAL_USING_DMA
#define RT_SERIAL_RB_BUFSZ 2048
#define RT_USING_CAN
#define RT_CAN_USING_HDR
#define RT_USING_HWTIMER
#define RT_USING_CPUTIME
#define RT_USING_I2C
#define RT_USING_I2C_BITOPS
#define RT_USING_PIN
#define RT_USING_ADC
#define RT_USING_RTC
#define RT_USING_SOFT_RTC
#define RT_USING_SPI
#define RT_USING_QSPI
#define RT_USING_SFUD
#define RT_SFUD_USING_SFDP
#define RT_SFUD_USING_FLASH_INFO_TABLE
#define RT_SFUD_USING_QSPI
#define RT_SFUD_SPI_MAX_HZ 50000000
#define RT_USING_WDT
#define RT_USING_HWCRYPTO
#define RT_HWCRYPTO_DEFAULT_NAME "hwcryto"
#define RT_HWCRYPTO_IV_MAX_SIZE 16
#define RT_HWCRYPTO_KEYBIT_MAX_SIZE 256
#define RT_HWCRYPTO_USING_AES
#define RT_HWCRYPTO_USING_AES_ECB
#define RT_HWCRYPTO_USING_AES_CBC
#define RT_HWCRYPTO_USING_AES_CFB
#define RT_HWCRYPTO_USING_AES_CTR
#define RT_HWCRYPTO_USING_AES_OFB
#define RT_HWCRYPTO_USING_SHA1
#define RT_HWCRYPTO_USING_SHA2
#define RT_HWCRYPTO_USING_SHA2_224
#define RT_HWCRYPTO_USING_SHA2_256
#define RT_HWCRYPTO_USING_SHA2_384
#define RT_HWCRYPTO_USING_SHA2_512
#define RT_HWCRYPTO_USING_RNG
/* Using USB */
#define RT_USING_USB
#define RT_USING_USB_HOST
#define RT_USBH_MSTORAGE
#define UDISK_MOUNTPOINT "/mnt/udisk"
#define RT_USING_USB_DEVICE
#define RT_USBD_THREAD_STACK_SZ 4096
#define USB_VENDOR_ID 0x0FFE
#define USB_PRODUCT_ID 0x0001
#define RT_USB_DEVICE_COMPOSITE
#define RT_USB_DEVICE_CDC
#define RT_USB_DEVICE_NONE
#define RT_USB_DEVICE_MSTORAGE
#define RT_VCOM_TASK_STK_SIZE 2048
#define RT_CDC_RX_BUFSIZE 128
#define RT_VCOM_SERNO "32021919830108"
#define RT_VCOM_SER_LEN 14
#define RT_VCOM_TX_TIMEOUT 1000
#define RT_USB_MSTORAGE_DISK_NAME "ramdisk1"
/* C/C++ and POSIX layer */
#define RT_LIBC_DEFAULT_TIMEZONE 8
/* POSIX (Portable Operating System Interface) layer */
#define RT_USING_POSIX_FS
#define RT_USING_POSIX_DEVIO
#define RT_USING_POSIX_POLL
#define RT_USING_POSIX_SELECT
#define RT_USING_POSIX_SOCKET
/* Interprocess Communication (IPC) */
/* Socket is in the 'Network' category */
/* Network */
#define RT_USING_SAL
/* Docking with protocol stacks */
#define SAL_USING_LWIP
#define SAL_USING_POSIX
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
#define RT_USING_LWIP
#define RT_USING_LWIP212
#define RT_USING_LWIP_VER_NUM 0x20102
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.31.55"
#define RT_LWIP_GWADDR "192.168.31.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 16
#define RT_LWIP_PBUF_NUM 256
#define RT_LWIP_RAW_PCB_NUM 16
#define RT_LWIP_UDP_PCB_NUM 16
#define RT_LWIP_TCP_PCB_NUM 16
#define RT_LWIP_TCP_SEG_NUM 64
#define RT_LWIP_TCP_SND_BUF 16384
#define RT_LWIP_TCP_WND 65535
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 256
#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 4096
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 256
#define RT_LWIP_REASSEMBLY_FRAG
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define RT_LWIP_NETIF_LOOPBACK
#define LWIP_NETIF_LOOPBACK 1
#define RT_LWIP_STATS
#define RT_LWIP_USING_PING
/* Utilities */
#define RT_USING_UTEST
#define UTEST_THR_STACK_SIZE 4096
#define UTEST_THR_PRIORITY 20
/* RT-Thread Utestcases */
/* RT-Thread online packages */
/* IoT - internet of things */
/* Wi-Fi */
/* Marvell WiFi */
/* Wiced WiFi */
#define PKG_USING_NETUTILS
#define PKG_NETUTILS_TFTP
#define PKG_NETUTILS_IPERF
#define PKG_NETUTILS_NTP
#define NTP_USING_AUTO_SYNC
#define NTP_AUTO_SYNC_FIRST_DELAY 30
#define NTP_AUTO_SYNC_PERIOD 3600
#define NETUTILS_NTP_HOSTNAME "0.tw.pool.ntp.org"
#define NETUTILS_NTP_HOSTNAME2 "1.tw.pool.ntp.org"
#define NETUTILS_NTP_HOSTNAME3 "2.tw.pool.ntp.org"
#define PKG_USING_NETUTILS_LATEST_VERSION
#define PKG_NETUTILS_VER_NUM 0x99999
/* IoT Cloud */
/* security packages */
/* language packages */
/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
/* XML: Extensible Markup Language */
/* multimedia packages */
/* LVGL: powerful and easy-to-use embedded GUI library */
/* u8g2: a monochrome graphic library */
/* PainterEngine: A cross-platform graphics application framework written in C language */
/* tools packages */
/* system packages */
/* enhanced kernel services */
/* acceleration: Assembly language or algorithmic acceleration packages */
/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
/* Micrium: Micrium software products porting for RT-Thread */
#define PKG_USING_RAMDISK
#define PKG_USING_RAMDISK_LATEST_VERSION
/* peripheral libraries and drivers */
/* Kendryte SDK */
/* AI packages */
/* miscellaneous packages */
/* project laboratory */
/* samples: kernel and components samples */
/* entertainment: terminal games and other interesting software packages */
#define PKG_USING_OPTPARSE
#define PKG_USING_OPTPARSE_LATEST_VERSION
/* Privated Packages of RealThread */
/* Network Utilities */
/* RT-Thread Smart */
/* Hardware Drivers Config */
/* On-chip Peripheral Drivers */
#define SOC_SERIES_NUC980
#define BSP_USE_STDDRIVER_SOURCE
#define BSP_USING_MMU
#define BSP_USING_PDMA
#define NU_PDMA_MEMFUN_ACTOR_MAX 2
#define BSP_USING_GPIO
#define BSP_USING_EMAC
#define BSP_USING_EMAC1
#define NU_EMAC_PDMA_MEMCOPY
#define NU_EMAC_PDMA_MEMCOPY_THRESHOLD 128
#define BSP_USING_ADC
#define BSP_USING_TMR
#define BSP_USING_TIMER
#define BSP_USING_TMR0
#define BSP_USING_TIMER0
#define BSP_USING_TMR1
#define BSP_USING_TIMER1
#define BSP_USING_TMR2
#define BSP_USING_TIMER2
#define BSP_USING_TMR3
#define BSP_USING_TIMER3
#define BSP_USING_TMR4
#define BSP_USING_TIMER4
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_USING_UART4
#define BSP_USING_UART4_TX_DMA
#define BSP_USING_UART4_RX_DMA
#define BSP_USING_UART8
#define BSP_USING_UART8_TX_DMA
#define BSP_USING_UART8_RX_DMA
#define BSP_USING_I2C
#define BSP_USING_I2C1
#define BSP_USING_CAN
#define BSP_USING_CAN3
#define BSP_USING_SPI
#define BSP_USING_SPI_PDMA
#define BSP_USING_SPI0
#define BSP_USING_SPI0_PDMA
#define BSP_USING_SPI1_NONE
#define BSP_USING_QSPI
#define BSP_USING_QSPI_PDMA
#define BSP_USING_QSPI0
#define BSP_USING_QSPI0_PDMA
#define BSP_USING_CRYPTO
#define BSP_USING_WDT
#define BSP_USING_USBD
#define BSP_USING_USBH
/* On-board Peripheral Drivers */
#define BSP_USING_CONSOLE
#define BOARD_USING_UART8_RS485
#define BOARD_USING_STORAGE_SPIFLASH
#define BOARD_USING_USB0_DEVICE_HOST
/* Board extended module drivers */
#define BOARD_USING_IP101GR
/* Nuvoton Packages Config */
#define NU_PKG_USING_UTILS
#define NU_PKG_USING_DEMO
#endif

2
bsp/nuvoton/nk-rtu980/rtconfig.py
View File

@ -16,7 +16,7 @@ if os.getenv('RTT_ROOT'):
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
EXEC_PATH = r'C:\Program Files (x86)\GNU Tools ARM Embedded\6 2017-q1-update\bin'
elif CROSS_TOOL == 'keil':
if CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = r'C:\Keil_v5'

381
bsp/nuvoton/numaker-hmi-ma35d1/.config
View File

@ -9,8 +9,8 @@ CONFIG_USE_MA35D1_AARCH32=y
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
CONFIG_RT_USING_SMP=y
CONFIG_RT_CPUS_NR=2
# CONFIG_RT_USING_SMART is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=32
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
@ -23,7 +23,6 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=4096
CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
@ -67,7 +66,7 @@ CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
CONFIG_RT_USING_MEMHEAP=y
CONFIG_RT_MEMHEAP_FAST_MODE=y
# CONFIG_RT_MEMHEAP_BSET_MODE is not set
# CONFIG_RT_MEMHEAP_BEST_MODE is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
@ -82,19 +81,26 @@ CONFIG_RT_USING_HEAP=y
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_DM is not set
CONFIG_RT_USING_INTERRUPT_INFO=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=4096
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x50000
CONFIG_ARCH_ARM=y
CONFIG_RT_USING_CACHE=y
# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
CONFIG_RT_USING_CPU_FFS=y
CONFIG_ARCH_MM_MMU=y
CONFIG_ARCH_ARM=y
CONFIG_ARCH_ARM_MMU=y
CONFIG_ARCH_ARM_CORTEX_A=y
CONFIG_RT_SMP_AUTO_BOOT=y
CONFIG_RT_USING_GIC_V2=y
# CONFIG_RT_USING_GIC_V3 is not set
CONFIG_ARCH_ARM_SECURE_MODE=y
# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set
CONFIG_ARCH_ARMV8=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
@ -151,15 +157,17 @@ CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_CROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_TMPFS is not set
# CONFIG_RT_USING_DFS_NFS is not set
# CONFIG_RT_USING_FAL is not set
# CONFIG_RT_USING_LWP is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
@ -179,11 +187,15 @@ CONFIG_RT_USING_I2C_BITOPS=y
CONFIG_RT_USING_PIN=y
CONFIG_RT_USING_ADC=y
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_NULL is not set
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
CONFIG_RT_USING_PWM=y
# CONFIG_RT_USING_MTD_NOR is not set
CONFIG_RT_USING_MTD_NAND=y
CONFIG_RT_MTD_NAND_DEBUG=y
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_FDT is not set
CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_ALARM is not set
# CONFIG_RT_USING_SOFT_RTC is not set
@ -209,10 +221,13 @@ CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=2048
# CONFIG_RT_USING_SENSOR is not set
CONFIG_RT_USING_TOUCH=y
# CONFIG_RT_TOUCH_PIN_IRQ is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
#
# Using USB
@ -507,6 +522,7 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_RYANMQTT is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@ -514,6 +530,7 @@ CONFIG_UTEST_SMALL_MEM_TC=y
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
# CONFIG_PKG_USING_ZFTP is not set
# CONFIG_PKG_USING_WOL is not set
#
# security packages
@ -563,14 +580,20 @@ CONFIG_PKG_USING_LVGL=y
CONFIG_PKG_LVGL_PATH="/packages/multimedia/LVGL/LVGL"
CONFIG_PKG_LVGL_THREAD_PRIO=20
CONFIG_PKG_LVGL_THREAD_STACK_SIZE=4096
CONFIG_PKG_LVGL_DISP_REFR_PERIOD=5
CONFIG_PKG_LVGL_DISP_REFR_PERIOD=16
# CONFIG_PKG_USING_LVGL_SQUARELINE is not set
# CONFIG_PKG_LVGL_USING_EXAMPLES is not set
CONFIG_PKG_LVGL_USING_DEMOS=y
# CONFIG_PKG_LVGL_USING_V08020 is not set
# CONFIG_PKG_LVGL_USING_V08034 is not set
# CONFIG_PKG_LVGL_USING_V08033 is not set
# CONFIG_PKG_LVGL_USING_V08032 is not set
# CONFIG_PKG_LVGL_USING_V08031 is not set
# CONFIG_PKG_LVGL_USING_V08030 is not set
CONFIG_PKG_LVGL_USING_LATEST_VERSION=y
CONFIG_PKG_LVGL_VER_NUM=0x99999
CONFIG_PKG_LVGL_VER="latest"
# CONFIG_PKG_LVGL_USING_V08020 is not set
CONFIG_PKG_LVGL_USING_V8_3_LATEST_VERSION=y
# CONFIG_PKG_LVGL_USING_LATEST_VERSION is not set
CONFIG_PKG_LVGL_VER_NUM=0x0803F
CONFIG_PKG_LVGL_VER="v8.3-latest"
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
@ -595,14 +618,10 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_HELIX_V100 is not set
# CONFIG_PKG_USING_HELIX_LATEST_VERSION is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_MP3PLAYER_V100 is not set
# CONFIG_PKG_USING_MP3PLAYER_LATEST_VERSION is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
@ -628,7 +647,6 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
@ -662,8 +680,8 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_CBOX is not set
# CONFIG_PKG_USING_SNOWFLAKE is not set
# CONFIG_PKG_USING_HASH_MATCH is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
# CONFIG_PKG_USING_VOFA_PLUS is not set
#
# system packages
@ -699,7 +717,6 @@ CONFIG_PKG_WAVPLAYER_VER="latest"
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_RTDUINO is not set
# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
@ -738,19 +755,93 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_KMULTI_RTIMER is not set
# CONFIG_PKG_USING_TFDB is not set
# CONFIG_PKG_USING_QPC is not set
# CONFIG_PKG_USING_AGILE_UPGRADE is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
#
# sensors drivers
#
# CONFIG_PKG_USING_LSM6DSM is not set
# CONFIG_PKG_USING_LSM6DSL is not set
# CONFIG_PKG_USING_LPS22HB is not set
# CONFIG_PKG_USING_HTS221 is not set
# CONFIG_PKG_USING_LSM303AGR is not set
# CONFIG_PKG_USING_BME280 is not set
# CONFIG_PKG_USING_BME680 is not set
# CONFIG_PKG_USING_BMA400 is not set
# CONFIG_PKG_USING_BMI160_BMX160 is not set
# CONFIG_PKG_USING_SPL0601 is not set
# CONFIG_PKG_USING_MS5805 is not set
# CONFIG_PKG_USING_DA270 is not set
# CONFIG_PKG_USING_DF220 is not set
# CONFIG_PKG_USING_HSHCAL001 is not set
# CONFIG_PKG_USING_BH1750 is not set
# CONFIG_PKG_USING_MPU6XXX is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_TSL4531 is not set
# CONFIG_PKG_USING_DS18B20 is not set
# CONFIG_PKG_USING_DHT11 is not set
# CONFIG_PKG_USING_DHTXX is not set
# CONFIG_PKG_USING_GY271 is not set
# CONFIG_PKG_USING_GP2Y10 is not set
# CONFIG_PKG_USING_SGP30 is not set
# CONFIG_PKG_USING_HDC1000 is not set
# CONFIG_PKG_USING_BMP180 is not set
# CONFIG_PKG_USING_BMP280 is not set
# CONFIG_PKG_USING_SHTC1 is not set
# CONFIG_PKG_USING_BMI088 is not set
# CONFIG_PKG_USING_HMC5883 is not set
# CONFIG_PKG_USING_MAX6675 is not set
# CONFIG_PKG_USING_TMP1075 is not set
# CONFIG_PKG_USING_SR04 is not set
# CONFIG_PKG_USING_CCS811 is not set
# CONFIG_PKG_USING_PMSXX is not set
# CONFIG_PKG_USING_RT3020 is not set
# CONFIG_PKG_USING_MLX90632 is not set
# CONFIG_PKG_USING_MLX90393 is not set
# CONFIG_PKG_USING_MLX90392 is not set
# CONFIG_PKG_USING_MLX90397 is not set
# CONFIG_PKG_USING_MS5611 is not set
# CONFIG_PKG_USING_MAX31865 is not set
# CONFIG_PKG_USING_VL53L0X is not set
# CONFIG_PKG_USING_INA260 is not set
# CONFIG_PKG_USING_MAX30102 is not set
# CONFIG_PKG_USING_INA226 is not set
# CONFIG_PKG_USING_LIS2DH12 is not set
# CONFIG_PKG_USING_HS300X is not set
# CONFIG_PKG_USING_ZMOD4410 is not set
# CONFIG_PKG_USING_ISL29035 is not set
# CONFIG_PKG_USING_MMC3680KJ is not set
# CONFIG_PKG_USING_QMP6989 is not set
# CONFIG_PKG_USING_BALANCE is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_ADT74XX is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# touch drivers
#
# CONFIG_PKG_USING_GT9147 is not set
# CONFIG_PKG_USING_GT1151 is not set
# CONFIG_PKG_USING_GT917S is not set
# CONFIG_PKG_USING_GT911 is not set
# CONFIG_PKG_USING_FT6206 is not set
# CONFIG_PKG_USING_FT5426 is not set
# CONFIG_PKG_USING_FT6236 is not set
# CONFIG_PKG_USING_XPT2046_TOUCH is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ESP_IDF is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
@ -773,12 +864,9 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
@ -793,7 +881,6 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
@ -824,10 +911,11 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_RFM300 is not set
# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
# CONFIG_PKG_USING_FINGERPRINT is not set
#
# AI packages
@ -842,6 +930,12 @@ CONFIG_PKG_RAMDISK_VER="latest"
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_UKAL is not set
#
# miscellaneous packages
#
@ -897,7 +991,6 @@ CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
@ -907,8 +1000,213 @@ CONFIG_PKG_OPTPARSE_VER="latest"
# CONFIG_PKG_USING_MFBD is not set
# CONFIG_PKG_USING_SLCAN2RTT is not set
# CONFIG_PKG_USING_SOEM is not set
CONFIG_UTEST_CMD_PREFIX="bsp.nuvoton.utest."
CONFIG_BOARD_USE_UTEST=y
# CONFIG_PKG_USING_QPARAM is not set
# CONFIG_PKG_USING_CorevMCU_CLI is not set
#
# Arduino libraries
#
# CONFIG_PKG_USING_RTDUINO is not set
#
# Projects
#
# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
#
# Sensors
#
# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
# CONFIG_PKG_USING_SEEED_ITG3200 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
# CONFIG_PKG_USING_SEEED_MP503 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
#
# Display
#
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set
#
# Timing
#
# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
#
# Data Processing
#
# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
#
# Data Storage
#
#
# Communication
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
#
# Device Control
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
#
# Other
#
#
# Signal IO
#
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
#
# Uncategorized
#
#
# Hardware Drivers Config
@ -918,6 +1216,11 @@ CONFIG_BOARD_USE_UTEST=y
# On-chip Peripheral Drivers
#
CONFIG_SOC_SERIES_MA35D1=y
CONFIG_BSP_USING_SSPCC=y
CONFIG_BSP_USING_SSMCC=y
CONFIG_BSP_USING_UMCTL2=y
CONFIG_BSP_USING_RTP=y
CONFIG_RTP_USING_AT_STARTUP=y
CONFIG_RT_USING_FPU=y
# CONFIG_BSP_USE_STDDRIVER_SOURCE is not set
CONFIG_BSP_USING_PDMA=y
@ -1006,9 +1309,6 @@ CONFIG_BSP_USING_QSPI0=y
# CONFIG_BSP_USING_SCUART is not set
# CONFIG_BSP_USING_ECAP is not set
# CONFIG_BSP_USING_QEI is not set
# CONFIG_BSP_USING_CRYPTO is not set
# CONFIG_BSP_USING_TRNG is not set
# CONFIG_BSP_USING_CRC is not set
# CONFIG_BSP_USING_SOFT_I2C is not set
CONFIG_BSP_USING_DISP=y
CONFIG_LCM_USING_FW070TFT_WSVGA=y
@ -1020,8 +1320,13 @@ CONFIG_BSP_LCD_WIDTH=1024
CONFIG_BSP_LCD_HEIGHT=600
CONFIG_DISP_USING_OVERLAY=y
# CONFIG_BSP_USING_WDT is not set
CONFIG_BSP_USING_HWSEM=y
CONFIG_BSP_USING_HWSEM0=y
CONFIG_BSP_USING_WHC=y
CONFIG_BSP_USING_WHC0=y
# CONFIG_BSP_USING_WHC1 is not set
CONFIG_BSP_USING_NFI=y
# CONFIG_BSP_USING_EBI is not set
# CONFIG_BSP_USING_USBD is not set
CONFIG_BSP_USING_USBH=y
CONFIG_BSP_USING_HSUSBH0=y
CONFIG_BSP_USING_HSUSBH1=y
@ -1033,9 +1338,11 @@ CONFIG_BSP_USING_CONSOLE=y
CONFIG_BOARD_USING_NAU8822=y
CONFIG_BOARD_USING_STORAGE_SDCARD=y
CONFIG_BOARD_USING_STORAGE_EMMC=y
CONFIG_BOARD_USING_STORAGE_RAWNAND=y
# CONFIG_BOARD_USING_STORAGE_SPIFLASH is not set
CONFIG_BOARD_USING_STORAGE_SPINAND=y
# CONFIG_BOARD_USING_BUZZER is not set
# CONFIG_BOARD_USING_MPU6500 is not set
CONFIG_BOARD_USING_USBHOST=y
#
@ -1046,16 +1353,14 @@ CONFIG_BOARD_USING_LCM=y
CONFIG_BOARD_USING_LCM_FW070TFT_WSVGA=y
# CONFIG_BOARD_USING_GT911 is not set
CONFIG_BOARD_USING_ADCTOUCH=y
CONFIG_BOARD_USING_SENSOR0=y
CONFIG_BOARD_USING_SENSON0_ID=0
# CONFIG_BOARD_USING_SENSOR0 is not set
# CONFIG_BOARD_USING_SENSOR1 is not set
#
# Nuvoton Packages Config
#
CONFIG_NU_PKG_USING_UTILS=y
# CONFIG_NU_PKG_USING_DEMO is not set
CONFIG_NU_PKG_USING_LVGL=y
CONFIG_NU_PKG_USING_DEMO=y
# CONFIG_NU_PKG_USING_BMX055 is not set
# CONFIG_NU_PKG_USING_MAX31875 is not set
# CONFIG_NU_PKG_USING_NCT7717U is not set

16
bsp/nuvoton/numaker-hmi-ma35d1/README.md
View File

@ -88,10 +88,10 @@ Support GCC compiler. More information of these compiler version as following:
| Compiler | Tested version |
| -- | -- |
| GCC | 6-2017-q1-update|
| GCC | Arm Embedded Toolchain 10.3-2021.10 (Env 1.3.5 embedded version)|
## **Build RT-Thread**
You can build rt-thread.bin for NuMaker-HMI-MA35D1 board. Steps as following. Notice, the building will include **ma35-rtp/rtthread.bin** file into **NuMaker-HMI-MA35D1/rtthread.bin** for heterogeneous multi-core demonstration.
You can build rt-thread.bin for NuMaker-HMI-MA35D1 board. Steps as following. Notice, the building will include **ma35-rtp/rtthread.bin** file into **numaker-hmi-ma35d1/rtthread.bin** for heterogeneous multi-core demonstration.
```bash
# cd rt-thread/bsp/nuvoton/numaker-hmi-ma35d1
@ -194,8 +194,8 @@ You can run windows batch script to download rtthread.bin into Raw NAND flash, t
|Connector on board|Wiring|Usage|
|-|-|-|
|VCOM(CON21)|Use an USB line| rt-thread@RTP Console |
|RS232_16(CON14)|Using an USB to RS232 convert| rt-thread@CA35 Console |
|VCOM(CON21)|Use an USB line| rt-thread@CA35 Console |
|RS232_16(CON14)|Using an USB to RS232 convert| rt-thread@RTP Console |
You can use Tera Term terminate emulator (or other software) to type commands of RTT. All parameters of serial communication are shown in below image. Here, you can find out the corresponding port number of Nuvoton Virtual Com Port in window device manager.
@ -206,11 +206,11 @@ You can use Tera Term terminate emulator (or other software) to type commands of
## **Purchase**
* [Nuvoton Direct](https://ComingSoon)
* [Nuvoton Direct](https://direct.nuvoton.com/en/numaker-hmi-ma35d1-s1)
## **Resources**
* [Download Board Schematics](https://ComingSoon)
* [Download Quick Start Guide](https://ComingSoon)
* [Download TRM](https://ComingSoon)
* [Download Board Schematics](https://www.nuvoton.com/resource-download.jsp?tp_GUID=HL102022102107140870)
* [Download User Manual](https://www.nuvoton.com/resource-download.jsp?tp_GUID=UG132022101900252882)
* [Download Datasheet](https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA00-MA35D16)
* [Download NuWriter](https://github.com/OpenNuvoton/MA35D1_NuWriter)

Some files were not shown because too many files have changed in this diff Show More