Add taihu bsp (PPC405)
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2350 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
bernard.xiong
parent
8ab1059873
commit
0c13711396
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@ -0,0 +1,15 @@
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# RT-Thread building script for bridge
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import os
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@ -0,0 +1,33 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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from building import *
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TARGET = 'rtthread-taihu.' + rtconfig.TARGET_EXT
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cwd = GetCurrentDir()
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# add include path for asm
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rtconfig.AFLAGS = rtconfig.AFLAGS + ' -I' + RTT_ROOT + '/libcpu/ppc/ppc405/include '
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rtconfig.CFLAGS = rtconfig.CFLAGS + ' -I' + RTT_ROOT + '/libcpu/ppc/ppc405/include '
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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Export('RTT_ROOT')
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Export('rtconfig')
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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# build program
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DoBuilding(TARGET, objs)
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# RT-Thread building script for component
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd, Dir('#')]
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group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')
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@ -0,0 +1,100 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-04-16 first version
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*/
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#include <rtthread.h>
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#define THREAD_STACK_SIZE 1024
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#if 0
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struct rt_semaphore sem1, sem2;
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static struct rt_thread thread1;
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ALIGN(4)
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static rt_uint8_t thread1_stack[THREAD_STACK_SIZE];
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static struct rt_thread thread2;
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ALIGN(4)
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static rt_uint8_t thread2_stack[THREAD_STACK_SIZE];
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static void thread1_entry(void* parameter)
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{
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while (1)
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{
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rt_sem_release(&sem2);
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rt_kprintf("thread1..: %s\n", rt_thread_self()->name);
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rt_sem_take(&sem1, RT_WAITING_FOREVER);
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rt_kprintf("get semaphore: %s!\n", rt_thread_self()->name);
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}
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}
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static void thread2_entry(void* parameter)
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{
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while (1)
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{
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rt_sem_take(&sem2, RT_WAITING_FOREVER);
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rt_kprintf("thread2--->: %s\n", rt_thread_self()->name);
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rt_sem_release(&sem1);
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}
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}
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/* user application */
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int rt_application_init()
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{
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rt_err_t result;
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rt_sem_init(&sem1, "s1", 0, RT_IPC_FLAG_FIFO);
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rt_sem_init(&sem2, "s2", 0, RT_IPC_FLAG_FIFO);
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result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL,
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&thread1_stack[0], sizeof(thread1_stack), 10, 10);
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if (result == RT_EOK)
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rt_thread_startup(&thread1);
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result = rt_thread_init(&thread2, "t2", thread2_entry, RT_NULL,
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&thread2_stack[0], sizeof(thread2_stack), 18, 10);
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if (result == RT_EOK)
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rt_thread_startup(&thread2);
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return 0;
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}
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#else
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static struct rt_thread thread1;
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ALIGN(4)
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static rt_uint8_t thread1_stack[THREAD_STACK_SIZE];
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rt_timer_t ttimer;
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static void thread1_entry(void* parameter)
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{
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rt_uint32_t count = 0;
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while (1)
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{
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rt_kprintf("%s: count = %d\n", rt_thread_self()->name, count ++);
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rt_thread_delay(10);
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}
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}
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/* user application */
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int rt_application_init()
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{
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rt_err_t result;
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result = rt_thread_init(&thread1, "t1", thread1_entry, RT_NULL,
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&thread1_stack[0], sizeof(thread1_stack), 10, 10);
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ttimer = &(thread1.thread_timer);
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if (result == RT_EOK)
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rt_thread_startup(&thread1);
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return 0;
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}
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#endif
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/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-04-16 first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "board.h"
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void rt_hw_board_init()
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{
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rt_hw_serial_init();
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rt_console_set_device("uart1");
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}
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/*
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* File : board.h
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-04-16 first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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void rt_hw_board_init(void);
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#endif
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/*
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* File : startup.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2011-04-16 nsj first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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extern void finsh_system_init(void);
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#endif
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extern int rt_application_init(void);
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#ifdef RT_USING_DEVICE
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extern rt_err_t rt_hw_serial_init(void);
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#endif
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extern int __heap_start;
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extern int __heap_end;
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/**
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* This function will startup RT-Thread RTOS.
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*/
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void rtthread_startup(void)
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{
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/* init hardware interrupt */
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rt_hw_interrupt_init();
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/* init board */
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rt_hw_board_init();
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rt_show_version();
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/* init tick */
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rt_system_tick_init();
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/* init timer system */
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rt_system_timer_init();
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/* init memory system */
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void*)&__heap_start, (void*)&__heap_end);
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#endif
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/* init scheduler system */
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rt_system_scheduler_init();
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/* init application */
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rt_application_init();
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#ifdef RT_USING_FINSH
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/* init finsh */
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finsh_system_init();
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finsh_set_device("uart1");
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#endif
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/* init soft timer thread */
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rt_system_timer_thread_init();
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/* init idle thread */
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rt_thread_idle_init();
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/* start scheduler */
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rt_system_scheduler_start();
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/* never reach here */
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return ;
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}
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/* RT-Thread config file */
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#ifndef __RTTHREAD_CFG_H__
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#define __RTTHREAD_CFG_H__
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/* RT_NAME_MAX*/
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#define RT_NAME_MAX 8
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/* RT_ALIGN_SIZE*/
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#define RT_ALIGN_SIZE 4
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/* PRIORITY_MAX*/
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#define RT_THREAD_PRIORITY_MAX 32
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#define IDLE_THREAD_STACK_SIZE 1024
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/* Tick per Second*/
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#define RT_TICK_PER_SECOND 100
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/* CPU Frequency 200MHz */
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#define RT_CPU_FREQ 200
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/* SECTION: RT_DEBUG */
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/* open debug for system assert */
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// #define RT_DEBUG
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/* Thread Debug*/
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/* #define RT_THREAD_DEBUG */
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/* #define RT_SCHEDULER_DEBUG */
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/* Using Hook*/
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#define RT_USING_HOOK
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/* SECTION: IPC */
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/* Using Semaphore*/
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#define RT_USING_SEMAPHORE
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/* Using Mutex*/
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#define RT_USING_MUTEX
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/* Using Event*/
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#define RT_USING_EVENT
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/* Using MailBox*/
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#define RT_USING_MAILBOX
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/* Using Message Queue*/
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#define RT_USING_MESSAGEQUEUE
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/* SECTION: Memory Management */
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/* Using Memory Pool Management*/
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#define RT_USING_MEMPOOL
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/* Using Dynamic Heap Management*/
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#define RT_USING_HEAP
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/* Using Small MM*/
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#define RT_USING_SMALL_MEM
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// #define RT_USING_NOLIBC
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#define RT_TINY_SIZE
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/* SECTION: Device System */
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/* Using Device System*/
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#define RT_USING_DEVICE
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#define RT_USING_UART1
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#define RT_UART_RX_BUFFER_SIZE 64
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/* SECTION: Console options */
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#define RT_USING_CONSOLE
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/* the buffer size of console*/
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#define RT_CONSOLEBUF_SIZE 128
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/* SECTION: FinSH shell options */
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/* Using FinSH as Shell*/
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#define RT_USING_FINSH
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/* Using symbol table */
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#define FINSH_USING_SYMTAB
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#define FINSH_USING_DESCRIPTION
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/* SECTION: lwip, a lighwight TCP/IP protocol stack */
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/* #define RT_USING_LWIP */
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/* LwIP uses RT-Thread Memory Management */
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#define RT_LWIP_USING_RT_MEM
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/* Enable ICMP protocol*/
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#define RT_LWIP_ICMP
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/* Enable UDP protocol*/
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#define RT_LWIP_UDP
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/* Enable TCP protocol*/
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#define RT_LWIP_TCP
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/* Enable DNS */
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#define RT_LWIP_DNS
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/* the number of simulatenously active TCP connections*/
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#define RT_LWIP_TCP_PCB_NUM 5
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/* ip address of target*/
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#define RT_LWIP_IPADDR0 192
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#define RT_LWIP_IPADDR1 168
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#define RT_LWIP_IPADDR2 1
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#define RT_LWIP_IPADDR3 30
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/* gateway address of target*/
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#define RT_LWIP_GWADDR0 192
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#define RT_LWIP_GWADDR1 168
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#define RT_LWIP_GWADDR2 1
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#define RT_LWIP_GWADDR3 1
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/* mask address of target*/
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#define RT_LWIP_MSKADDR0 255
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#define RT_LWIP_MSKADDR1 255
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#define RT_LWIP_MSKADDR2 255
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#define RT_LWIP_MSKADDR3 0
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/* tcp thread options */
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#define RT_LWIP_TCPTHREAD_PRIORITY 12
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#define RT_LWIP_TCPTHREAD_MBOX_SIZE 4
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#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
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/* ethernet if thread options */
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#define RT_LWIP_ETHTHREAD_PRIORITY 15
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#define RT_LWIP_ETHTHREAD_MBOX_SIZE 4
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#define RT_LWIP_ETHTHREAD_STACKSIZE 512
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#endif
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# toolchains options
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ARCH='ppc'
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CPU='ppc405'
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CROSS_TOOL='gcc'
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TextBase = '0x00000000'
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PLATFORM = 'gcc'
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EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
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BUILD = 'debug'
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if PLATFORM == 'gcc':
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# toolchains
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PREFIX = 'powerpc-eabi-'
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CC = PREFIX + 'gcc'
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CXX = PREFIX + 'g++'
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AS = PREFIX + 'gcc'
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AR = PREFIX + 'ar'
|
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LINK = PREFIX + 'gcc'
|
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TARGET_EXT = 'elf'
|
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SIZE = PREFIX + 'size'
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OBJDUMP = PREFIX + 'objdump'
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OBJCPY = PREFIX + 'objcopy'
|
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|
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DEVICE = ' -mcpu=405 -mno-multiple -mno-string -mno-update -fno-exceptions -fno-builtin -msoft-float'
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CFLAGS = DEVICE + ' -D__KERNEL__'
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AFLAGS = '-D__ASSEMBLY__ -fno-exceptions -fno-builtin -mregnames -c -Wall -Xassembler -m405 -msoft-float -ffunction-sections'
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LFLAGS = DEVICE + ' -Wl,--gc-sections,--cref,-Map=rtthread.map -T taihu.lds' + ' -Ttext=' + TextBase
|
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|
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CPATH = ''
|
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LPATH = ''
|
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|
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if BUILD == 'debug':
|
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CFLAGS += ' -O0 -gdwarf-2'
|
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AFLAGS += ' -gdwarf-2'
|
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else:
|
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CFLAGS += ' -O2'
|
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|
||||
DASM_ACTION = OBJDUMP + ' -d rtthread-taihu.elf > rtt.asm\n'
|
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POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' # + DASM_ACTION
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OUTPUT_ARCH(powerpc)
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||||
|
||||
/* Do we need any of these for elf?
|
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__DYNAMIC = 0; */
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SECTIONS
|
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{
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||||
.resetvec 0xFFFFFFFC :
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||||
{
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*(.resetvec)
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} = 0xffff
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|
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/* Read-only sections, merged into text segment: */
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. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
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.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
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.rel.data : { *(.rel.data) }
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||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
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.rel.got : { *(.rel.got) }
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||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
/* .init : { *(.init) } */
|
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.plt : { *(.plt) }
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|
||||
.text :
|
||||
{
|
||||
KEEP(build\libcpu\ppc\ppc405\start_gcc.o (.text))
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.eh_frame)
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
|
||||
PROVIDE(__stack_bottom = .);
|
||||
. += 0x100000; /* 1MB */
|
||||
PROVIDE(__stack_top = .);
|
||||
|
||||
. = ALIGN(256);
|
||||
PROVIDE (__heap_start = .);
|
||||
. += 0x500000; /* 5MB */
|
||||
PROVIDE(__heap_end = .);
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
#ifndef _PPC_PTRACE_H
|
||||
#define _PPC_PTRACE_H
|
||||
|
||||
/*
|
||||
* This struct defines the way the registers are stored on the
|
||||
* kernel stack during a system call or other kernel entry.
|
||||
*
|
||||
* this should only contain volatile regs
|
||||
* since we can keep non-volatile in the thread_struct
|
||||
* should set this up when only volatiles are saved
|
||||
* by intr code.
|
||||
*
|
||||
* Since this is going on the stack, *CARE MUST BE TAKEN* to insure
|
||||
* that the overall structure is a multiple of 16 bytes in length.
|
||||
*
|
||||
* Note that the offsets of the fields in this struct correspond with
|
||||
* the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define PPC_REG unsigned long
|
||||
|
||||
struct pt_regs {
|
||||
PPC_REG gpr[32];
|
||||
PPC_REG nip;
|
||||
PPC_REG msr;
|
||||
PPC_REG orig_gpr3; /* Used for restarting system calls */
|
||||
PPC_REG ctr;
|
||||
PPC_REG link;
|
||||
PPC_REG xer;
|
||||
PPC_REG ccr;
|
||||
PPC_REG mq; /* 601 only (not used at present) */
|
||||
/* Used on APUS to hold IPL value. */
|
||||
PPC_REG trap; /* Reason for being here */
|
||||
PPC_REG dar; /* Fault registers */
|
||||
PPC_REG dsisr;
|
||||
PPC_REG result; /* Result of a system call */
|
||||
}__attribute__((packed)) CELL_STACK_FRAME_t;
|
||||
#endif
|
||||
|
||||
#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
|
||||
|
||||
/* Size of stack frame allocated when calling signal handler. */
|
||||
#define __SIGNAL_FRAMESIZE 64
|
||||
|
||||
#define instruction_pointer(regs) ((regs)->nip)
|
||||
#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
|
||||
|
||||
/*
|
||||
* Offsets used by 'ptrace' system call interface.
|
||||
* These can't be changed without breaking binary compatibility
|
||||
* with MkLinux, etc.
|
||||
*/
|
||||
#define PT_R0 0
|
||||
#define PT_R1 1
|
||||
#define PT_R2 2
|
||||
#define PT_R3 3
|
||||
#define PT_R4 4
|
||||
#define PT_R5 5
|
||||
#define PT_R6 6
|
||||
#define PT_R7 7
|
||||
#define PT_R8 8
|
||||
#define PT_R9 9
|
||||
#define PT_R10 10
|
||||
#define PT_R11 11
|
||||
#define PT_R12 12
|
||||
#define PT_R13 13
|
||||
#define PT_R14 14
|
||||
#define PT_R15 15
|
||||
#define PT_R16 16
|
||||
#define PT_R17 17
|
||||
#define PT_R18 18
|
||||
#define PT_R19 19
|
||||
#define PT_R20 20
|
||||
#define PT_R21 21
|
||||
#define PT_R22 22
|
||||
#define PT_R23 23
|
||||
#define PT_R24 24
|
||||
#define PT_R25 25
|
||||
#define PT_R26 26
|
||||
#define PT_R27 27
|
||||
#define PT_R28 28
|
||||
#define PT_R29 29
|
||||
#define PT_R30 30
|
||||
#define PT_R31 31
|
||||
|
||||
#define PT_NIP 32
|
||||
#define PT_MSR 33
|
||||
#define PT_ORIG_R3 34
|
||||
#define PT_CTR 35
|
||||
#define PT_LNK 36
|
||||
#define PT_XER 37
|
||||
#define PT_CCR 38
|
||||
#define PT_MQ 39
|
||||
|
||||
#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
|
||||
#define PT_FPR31 (PT_FPR0 + 2*31)
|
||||
#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006-2011, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-02-14 Fred first implementation for
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
/**
|
||||
* @addtogroup PowerPC
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
unsigned long *stk;
|
||||
rt_uint32_t msr;
|
||||
|
||||
__asm__ __volatile__("mfmsr %0\n" : "=r" (msr));
|
||||
msr |= 0x00028000;
|
||||
|
||||
stk = (unsigned long *)stack_addr;
|
||||
--stk;
|
||||
*(--stk) = msr; /* srr0: machine status register */
|
||||
*(--stk) = (rt_uint32_t)tentry; /* srr1: entry point */
|
||||
*(--stk) = (rt_uint32_t)texit; /* lr: link register */
|
||||
*(--stk) = 0x0F0F0F0F; /* ctr: counter register */
|
||||
*(--stk) = 0x0F0F0F0F; /* xer: fixed-point exception register */
|
||||
*(--stk) = 0x0F0F0F0F; /* cr : condition register */
|
||||
*(--stk) = 0x00; /* usprg0 */
|
||||
|
||||
*(--stk) = 0x31; /* r31 */
|
||||
*(--stk) = 0x30; /* r30 */
|
||||
*(--stk) = 0x29; /* r29 */
|
||||
*(--stk) = 0x28; /* r28 */
|
||||
*(--stk) = 0x27; /* r27 */
|
||||
*(--stk) = 0x26; /* r26 */
|
||||
*(--stk) = 0x25; /* r25 */
|
||||
*(--stk) = 0x24; /* r24 */
|
||||
*(--stk) = 0x23; /* r23 */
|
||||
*(--stk) = 0x22; /* r22 */
|
||||
*(--stk) = 0x21; /* r21 */
|
||||
*(--stk) = 0x20; /* r20 */
|
||||
*(--stk) = 0x19; /* r19 */
|
||||
*(--stk) = 0x18; /* r18 */
|
||||
*(--stk) = 0x17; /* r17 */
|
||||
*(--stk) = 0x16; /* r16 */
|
||||
*(--stk) = 0x15; /* r15 */
|
||||
*(--stk) = 0x14; /* r14 */
|
||||
*(--stk) = 0x13; /* r13: thread id */
|
||||
*(--stk) = 0x12; /* r12 */
|
||||
*(--stk) = 0x11; /* r11 */
|
||||
*(--stk) = 0x10; /* r10 */
|
||||
*(--stk) = 0x09; /* r09 */
|
||||
*(--stk) = 0x08; /* r08 */
|
||||
*(--stk) = 0x07; /* r07 */
|
||||
*(--stk) = 0x06; /* r06 */
|
||||
*(--stk) = 0x05; /* r05 */
|
||||
*(--stk) = 0x04; /* r04 */
|
||||
*(--stk) = (rt_uint32_t)parameter; /* r03: parameter and return */
|
||||
*(--stk) = 0x02; /* r02: toc */
|
||||
/* r01: sp */
|
||||
*(--stk) = 0x0; /* r00 */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#ifndef __CACHE_H__
|
||||
#define __CACHE_H__
|
||||
|
||||
#include <asm/processor.h>
|
||||
|
||||
#if !defined(__ASSEMBLY__)
|
||||
void flush_dcache_range(unsigned long start, unsigned long stop);
|
||||
void clean_dcache_range(unsigned long start, unsigned long stop);
|
||||
void invalidate_dcache_range(unsigned long start, unsigned long stop);
|
||||
void flush_dcache(void);
|
||||
void invalidate_dcache(void);
|
||||
void invalidate_icache(void);
|
||||
|
||||
void icache_enable(void);
|
||||
void icache_disable(void);
|
||||
unsigned long icache_status(void);
|
||||
|
||||
void dcache_enable(void);
|
||||
void dcache_disable(void);
|
||||
unsigned long dcache_status(void);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
#define L1_CACHE_SHIFT 5
|
||||
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
|
||||
#define DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */
|
||||
|
||||
/*
|
||||
* Flush instruction cache.
|
||||
*/
|
||||
.globl invalidate_icache
|
||||
invalidate_icache:
|
||||
iccci r0,r0
|
||||
isync
|
||||
blr
|
||||
|
||||
/*
|
||||
* Write any modified data cache blocks out to memory
|
||||
* and invalidate the corresponding instruction cache blocks.
|
||||
*
|
||||
* flush_icache_range(unsigned long start, unsigned long stop)
|
||||
*/
|
||||
.globl flush_icache_range
|
||||
flush_icache_range:
|
||||
li r5,L1_CACHE_BYTES-1
|
||||
andc r3,r3,r5
|
||||
subf r4,r3,r4
|
||||
add r4,r4,r5
|
||||
srwi. r4,r4,L1_CACHE_SHIFT
|
||||
beqlr
|
||||
mtctr r4
|
||||
mr r6,r3
|
||||
1: dcbst 0,r3
|
||||
addi r3,r3,L1_CACHE_BYTES
|
||||
bdnz 1b
|
||||
sync /* wait for dcbst's to get to ram */
|
||||
mtctr r4
|
||||
2: icbi 0,r6
|
||||
addi r6,r6,L1_CACHE_BYTES
|
||||
bdnz 2b
|
||||
sync /* additional sync needed on g4 */
|
||||
isync
|
||||
blr
|
||||
|
||||
/*
|
||||
* Write any modified data cache blocks out to memory.
|
||||
* Does not invalidate the corresponding cache lines (especially for
|
||||
* any corresponding instruction cache).
|
||||
*
|
||||
* clean_dcache_range(unsigned long start, unsigned long stop)
|
||||
*/
|
||||
.globl clean_dcache_range
|
||||
clean_dcache_range:
|
||||
li r5,L1_CACHE_BYTES-1
|
||||
andc r3,r3,r5
|
||||
subf r4,r3,r4
|
||||
add r4,r4,r5
|
||||
srwi. r4,r4,L1_CACHE_SHIFT
|
||||
beqlr
|
||||
mtctr r4
|
||||
|
||||
1: dcbst 0,r3
|
||||
addi r3,r3,L1_CACHE_BYTES
|
||||
bdnz 1b
|
||||
sync /* wait for dcbst's to get to ram */
|
||||
blr
|
||||
|
||||
/*
|
||||
* Write any modified data cache blocks out to memory and invalidate them.
|
||||
* Does not invalidate the corresponding instruction cache blocks.
|
||||
*
|
||||
* flush_dcache_range(unsigned long start, unsigned long stop)
|
||||
*/
|
||||
.globl flush_dcache_range
|
||||
flush_dcache_range:
|
||||
li r5,L1_CACHE_BYTES-1
|
||||
andc r3,r3,r5
|
||||
subf r4,r3,r4
|
||||
add r4,r4,r5
|
||||
srwi. r4,r4,L1_CACHE_SHIFT
|
||||
beqlr
|
||||
mtctr r4
|
||||
|
||||
1: dcbf 0,r3
|
||||
addi r3,r3,L1_CACHE_BYTES
|
||||
bdnz 1b
|
||||
sync /* wait for dcbst's to get to ram */
|
||||
blr
|
||||
|
||||
/*
|
||||
* Like above, but invalidate the D-cache. This is used by the 8xx
|
||||
* to invalidate the cache so the PPC core doesn't get stale data
|
||||
* from the CPM (no cache snooping here :-).
|
||||
*
|
||||
* invalidate_dcache_range(unsigned long start, unsigned long stop)
|
||||
*/
|
||||
.globl invalidate_dcache_range
|
||||
invalidate_dcache_range:
|
||||
li r5,L1_CACHE_BYTES-1
|
||||
andc r3,r3,r5
|
||||
subf r4,r3,r4
|
||||
add r4,r4,r5
|
||||
srwi. r4,r4,L1_CACHE_SHIFT
|
||||
beqlr
|
||||
mtctr r4
|
||||
|
||||
1: dcbi 0,r3
|
||||
addi r3,r3,L1_CACHE_BYTES
|
||||
bdnz 1b
|
||||
sync /* wait for dcbi's to get to ram */
|
||||
blr
|
||||
|
||||
/*
|
||||
* 40x cores have 8K or 16K dcache and 32 byte line size.
|
||||
* 44x has a 32K dcache and 32 byte line size.
|
||||
* 8xx has 1, 2, 4, 8K variants.
|
||||
* For now, cover the worst case of the 44x.
|
||||
* Must be called with external interrupts disabled.
|
||||
*/
|
||||
#define CACHE_NWAYS 64
|
||||
#define CACHE_NLINES 32
|
||||
|
||||
.globl flush_dcache
|
||||
flush_dcache:
|
||||
li r4,(2 * CACHE_NWAYS * CACHE_NLINES)
|
||||
mtctr r4
|
||||
lis r5,0
|
||||
1: lwz r3,0(r5) /* Load one word from every line */
|
||||
addi r5,r5,L1_CACHE_BYTES
|
||||
bdnz 1b
|
||||
sync
|
||||
blr
|
||||
|
||||
.globl invalidate_dcache
|
||||
invalidate_dcache:
|
||||
addi r6,0,0x0000 /* clear GPR 6 */
|
||||
/* Do loop for # of dcache congruence classes. */
|
||||
lis r7,(DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */
|
||||
ori r7,r7,(DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
|
||||
/* NOTE: dccci invalidates both */
|
||||
mtctr r7 /* ways in the D cache */
|
||||
dcloop:
|
||||
dccci 0,r6 /* invalidate line */
|
||||
addi r6,r6,L1_CACHE_BYTES /* bump to next line */
|
||||
bdnz dcloop
|
||||
sync
|
||||
blr
|
||||
|
||||
/*
|
||||
* Cache functions.
|
||||
*
|
||||
* Icache-related functions are used in POST framework.
|
||||
*/
|
||||
.globl icache_enable
|
||||
icache_enable:
|
||||
mflr r8
|
||||
bl invalidate_icache
|
||||
mtlr r8
|
||||
isync
|
||||
addis r3,r0, 0xc000 /* set bit 0 */
|
||||
mticcr r3
|
||||
blr
|
||||
|
||||
.globl icache_disable
|
||||
icache_disable:
|
||||
addis r3,r0, 0x0000 /* clear bit 0 */
|
||||
mticcr r3
|
||||
isync
|
||||
blr
|
||||
|
||||
.globl icache_status
|
||||
icache_status:
|
||||
mficcr r3
|
||||
srwi r3, r3, 31 /* >>31 => select bit 0 */
|
||||
blr
|
||||
|
||||
.globl dcache_enable
|
||||
dcache_enable:
|
||||
mflr r8
|
||||
bl invalidate_dcache
|
||||
mtlr r8
|
||||
isync
|
||||
addis r3,r0, 0x8000 /* set bit 0 */
|
||||
mtdccr r3
|
||||
blr
|
||||
|
||||
.globl dcache_disable
|
||||
dcache_disable:
|
||||
mflr r8
|
||||
bl flush_dcache
|
||||
mtlr r8
|
||||
addis r3,r0, 0x0000 /* clear bit 0 */
|
||||
mtdccr r3
|
||||
blr
|
||||
|
||||
.globl dcache_status
|
||||
dcache_status:
|
||||
mfdccr r3
|
||||
srwi r3, r3, 31 /* >>31 => select bit 0 */
|
||||
blr
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#ifndef __CONTEXT_H__
|
||||
#define __CONTEXT_H__
|
||||
|
||||
#define MSR_ME (1<<12) /* Machine Check Enable */
|
||||
#define MSR_EE (1<<15) /* External Interrupt Enable */
|
||||
#define MSR_CE (1<<17) /* Critical Interrupt Enable */
|
||||
|
||||
#define GPR0 0
|
||||
#define GPR2 4
|
||||
#define GPR3 8
|
||||
#define GPR4 12
|
||||
#define GPR5 16
|
||||
#define GPR6 20
|
||||
#define GPR7 24
|
||||
#define GPR8 28
|
||||
#define GPR9 32
|
||||
#define GPR10 36
|
||||
#define GPR11 40
|
||||
#define GPR12 44
|
||||
#define GPR13 48
|
||||
#define GPR14 52
|
||||
#define GPR15 56
|
||||
#define GPR16 60
|
||||
#define GPR17 64
|
||||
#define GPR18 68
|
||||
#define GPR19 72
|
||||
#define GPR20 76
|
||||
#define GPR21 80
|
||||
#define GPR22 84
|
||||
#define GPR23 88
|
||||
#define GPR24 92
|
||||
#define GPR25 96
|
||||
#define GPR26 100
|
||||
#define GPR27 104
|
||||
#define GPR28 108
|
||||
#define GPR29 112
|
||||
#define GPR30 116
|
||||
#define GPR31 120
|
||||
#define USPRG0 (GPR31 + 4)
|
||||
#define CR (USPRG0 + 4)
|
||||
#define XER (CR + 4)
|
||||
#define CTR (XER + 4)
|
||||
#define LR (CTR + 4)
|
||||
#define SRR0 (LR + 4)
|
||||
#define SRR1 (SRR0 + 4)
|
||||
#define STACK_FRAME_SIZE (SRR1 + 4)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
#include "context.h"
|
||||
#define SPRG0 0x110 /* Special Purpose Register General 0 */
|
||||
#define SPRG1 0x111 /* Special Purpose Register General 1 */
|
||||
|
||||
.globl rt_hw_interrupt_disable
|
||||
.globl rt_hw_interrupt_enable
|
||||
.globl rt_hw_context_switch
|
||||
.globl rt_hw_context_switch_to
|
||||
.globl rt_hw_context_switch_interrupt
|
||||
.globl rt_hw_systemcall_entry
|
||||
|
||||
/*
|
||||
* rt_base_t rt_hw_interrupt_disable();
|
||||
* return the interrupt status and disable interrupt
|
||||
*/
|
||||
#if 0
|
||||
rt_hw_interrupt_disable:
|
||||
mfmsr r3 /* Disable interrupts */
|
||||
li r4,0
|
||||
ori r4,r4,MSR_EE
|
||||
andc r4,r4,r3
|
||||
SYNC /* Some chip revs need this... */
|
||||
mtmsr r4
|
||||
SYNC
|
||||
blr
|
||||
#else
|
||||
rt_hw_interrupt_disable:
|
||||
addis r4, r0, 0xFFFD
|
||||
ori r4, r4, 0x7FFF
|
||||
mfmsr r3
|
||||
and r4, r4, 3 /* Clear bits 14 and 16, corresponding to... */
|
||||
mtmsr r4 /* ...critical and non-critical interrupts */
|
||||
blr
|
||||
#endif
|
||||
|
||||
/*
|
||||
* void rt_hw_interrupt_enable(rt_base_t level);
|
||||
* restore interrupt
|
||||
*/
|
||||
rt_hw_interrupt_enable:
|
||||
mtmsr r3
|
||||
SYNC
|
||||
blr
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||
* r3 --> from
|
||||
* r4 --> to
|
||||
*
|
||||
* r1: stack pointer
|
||||
*/
|
||||
rt_hw_systemcall_entry:
|
||||
mtspr SPRG0,r3 /* save r3 to SPRG0 */
|
||||
mtspr SPRG1,r4 /* save r4 to SPRG1 */
|
||||
|
||||
lis r3,rt_thread_switch_interrput_flag@h
|
||||
ori r3,r3,rt_thread_switch_interrput_flag@l
|
||||
lwz r4,0(r3)
|
||||
cmpi cr0,0,r4,0x0 /* whether is 0 */
|
||||
beq _no_switch /* no switch, exit */
|
||||
li r4,0x0 /* set rt_thread_switch_interrput_flag to 0 */
|
||||
stw r4,0(r3)
|
||||
|
||||
/* load from thread to r3 */
|
||||
lis r3,rt_interrupt_from_thread@h /* set rt_interrupt_from_thread */
|
||||
ori r3,r3,rt_interrupt_from_thread@l
|
||||
lwz r3,0(r3)
|
||||
|
||||
cmpi cr0,0,r3,0x0 /* whether is 0 */
|
||||
beq _restore /* it's first switch, goto _restore */
|
||||
|
||||
/* save r1:sp to thread[from] stack pointer */
|
||||
subi r1, r1, STACK_FRAME_SIZE
|
||||
stw r1, 0(r3)
|
||||
|
||||
/* restore r3, r4 from SPRG */
|
||||
mfspr r3,SPRG0
|
||||
mfspr r4,SPRG0
|
||||
|
||||
/* save registers */
|
||||
stw r0,GPR0(r1) /* save general purpose registers 0 */
|
||||
stmw r2,GPR2(r1) /* save general purpose registers 2-31 */
|
||||
|
||||
mfusprg0 r0 /* save usprg0 */
|
||||
stw r0,USPRG0(r1)
|
||||
mfcr r0, /* save cr */
|
||||
stw r0,CR(r1)
|
||||
mfxer r0 /* save xer */
|
||||
stw r0,XER(r1)
|
||||
mfctr r0 /* save ctr */
|
||||
stw r0,CTR(r1)
|
||||
mflr r0 /* save lr */
|
||||
stw r0, LR(r1)
|
||||
|
||||
mfsrr0 r0 /* save SRR0 and SRR1 */
|
||||
stw r0,SRR0(r1)
|
||||
mfsrr1 r0
|
||||
stw r0,SRR1(r1)
|
||||
|
||||
_restore:
|
||||
/* get thread[to] stack pointer */
|
||||
lis r4,rt_interrupt_to_thread@h
|
||||
ori r4,r4,rt_interrupt_to_thread@l
|
||||
lwz r1,0(r4)
|
||||
lwz r1,0(r1)
|
||||
|
||||
lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */
|
||||
mtsrr1 r0
|
||||
lwz r0,SRR0(r1)
|
||||
mtsrr0 r0
|
||||
|
||||
lwz r0,LR(r1) /* restore lr */
|
||||
mtlr r0
|
||||
lwz r0,CTR(r1) /* restore ctr */
|
||||
mtctr r0
|
||||
lwz r0,XER(r1) /* restore xer */
|
||||
mtxer r0
|
||||
lwz r0,CR(r1) /* restore cr */
|
||||
mtcr r0
|
||||
lwz r0,USPRG0(r1) /* restore usprg0 */
|
||||
// mtusprg0 r0
|
||||
|
||||
lmw r2, GPR2(r1) /* restore general register */
|
||||
lwz r0,GPR0(r1)
|
||||
addi r1, r1, STACK_FRAME_SIZE
|
||||
/* RFI will restore status register and thus the correct priority*/
|
||||
rfi
|
||||
|
||||
_no_switch:
|
||||
/* restore r3, r4 from SPRG */
|
||||
mfspr r3,SPRG0
|
||||
mfspr r4,SPRG0
|
||||
rfi
|
||||
|
||||
/* void rt_hw_context_switch_to(to); */
|
||||
.globl rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
/* set rt_thread_switch_interrput_flag = 1 */
|
||||
lis r5,rt_thread_switch_interrput_flag@h
|
||||
ori r5,r5,rt_thread_switch_interrput_flag@l
|
||||
li r6, 0x01
|
||||
stw r6,0(r5)
|
||||
|
||||
/* set rt_interrupt_from_thread = 0 */
|
||||
lis r5,rt_interrupt_from_thread@h
|
||||
ori r5,r5,rt_interrupt_from_thread@l
|
||||
li r6, 0x00
|
||||
stw r6,0(r5)
|
||||
|
||||
/* set rt_interrupt_from_thread = to */
|
||||
lis r5,rt_interrupt_to_thread@h
|
||||
ori r5,r5,rt_interrupt_to_thread@l
|
||||
stw r3,0(r5)
|
||||
|
||||
/* trigger a system call */
|
||||
sc
|
||||
|
||||
blr
|
||||
|
||||
/* void rt_hw_context_switch(from, to); */
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
/* compare rt_thread_switch_interrupt_flag and set it */
|
||||
lis r5,rt_thread_switch_interrput_flag@h
|
||||
ori r5,r5,rt_thread_switch_interrput_flag@l
|
||||
lwz r6,0(r5)
|
||||
cmpi cr0,0,r6,0x1 /* whether is 1 */
|
||||
beq _reswitch /* set already, goto _reswitch */
|
||||
li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/
|
||||
stw r6,0(r5)
|
||||
|
||||
/* set rt_interrupt_from_thread to 'from' */
|
||||
lis r5,rt_interrupt_from_thread@h
|
||||
ori r5,r5,rt_interrupt_from_thread@l
|
||||
stw r3,0(r5)
|
||||
|
||||
_reswitch:
|
||||
/* set rt_interrupt_to_thread to 'to' */
|
||||
lis r6,rt_interrupt_to_thread@h
|
||||
ori r6,r6,rt_interrupt_to_thread@l
|
||||
stw r4,0(r6)
|
||||
|
||||
/* trigger a system call */
|
||||
sc
|
||||
|
||||
blr
|
||||
|
||||
.globl rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch_interrupt:
|
||||
/* compare rt_thread_switch_interrupt_flag and set it */
|
||||
lis r5,rt_thread_switch_interrput_flag@h
|
||||
ori r5,r5,rt_thread_switch_interrput_flag@l
|
||||
lwz r6,0(r5)
|
||||
cmpi cr0,0,r6,0x1 /* whether is 1 */
|
||||
beq _int_reswitch /* set already, goto _reswitch */
|
||||
li r6,0x1 /* set rt_thread_switch_interrput_flag to 1*/
|
||||
stw r6,0(r5)
|
||||
|
||||
/* set rt_interrupt_from_thread to 'from' */
|
||||
lis r5,rt_interrupt_from_thread@h
|
||||
ori r5,r5,rt_interrupt_from_thread@l
|
||||
stw r3,0(r5)
|
||||
|
||||
_int_reswitch:
|
||||
/* set rt_interrupt_to_thread to 'to' */
|
||||
lis r6,rt_interrupt_to_thread@h
|
||||
ori r6,r6,rt_interrupt_to_thread@l
|
||||
stw r4,0(r6)
|
||||
|
||||
blr
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* XXX - DANGER
|
||||
* These routines make use of self modifying code. DO NOT CALL THEM
|
||||
* UNTIL THEY ARE RELOCATED TO RAM. Additionally, I do not
|
||||
* recommend them for use in anything other than an interactive
|
||||
* debugging environment. This is mainly due to performance reasons.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/*
|
||||
* static void _create_MFDCR(unsigned short dcrn)
|
||||
*
|
||||
* Builds a 'mfdcr' instruction for get_dcr
|
||||
* function.
|
||||
*/
|
||||
.section ".text"
|
||||
.align 2
|
||||
.type _create_MFDCR,@function
|
||||
_create_MFDCR:
|
||||
/*
|
||||
* Build up a 'mfdcr' instruction formatted as follows:
|
||||
*
|
||||
* OPCD | RT | DCRF | XO | CR |
|
||||
* ---------------|--------------|--------------|----|
|
||||
* 0 5 | 6 10 | 11 20 | 21 30 | 31 |
|
||||
* | | DCRN | | |
|
||||
* 31 | %r3 | (5..9|0..4) | 323 | 0 |
|
||||
*
|
||||
* Where:
|
||||
* OPCD = opcode - 31
|
||||
* RT = destination register - %r3 return register
|
||||
* DCRF = DCRN # with upper and lower halves swapped
|
||||
* XO = extended opcode - 323
|
||||
* CR = CR[CR0] NOT undefined - 0
|
||||
*/
|
||||
rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */
|
||||
rlwinm r3, r3, 5, 22, 26
|
||||
or r3, r3, r0
|
||||
slwi r3, r3, 10
|
||||
oris r3, r3, 0x3e30 /* RT = %r3 */
|
||||
ori r3, r3, 323 /* XO = 323 */
|
||||
slwi r3, r3, 1 /* CR = 0 */
|
||||
|
||||
mflr r4
|
||||
stw r3, 0(r4) /* Store instr in get_dcr() */
|
||||
dcbst r0, r4 /* Make sure val is written out */
|
||||
sync /* Wait for write to complete */
|
||||
icbi r0, r4 /* Make sure old instr is dumped */
|
||||
isync /* Wait for icbi to complete */
|
||||
|
||||
blr
|
||||
.Lfe1: .size _create_MFDCR,.Lfe1-_create_MFDCR
|
||||
/* end _create_MFDCR() */
|
||||
|
||||
/*
|
||||
* static void _create_MTDCR(unsigned short dcrn, unsigned long value)
|
||||
*
|
||||
* Builds a 'mtdcr' instruction for set_dcr
|
||||
* function.
|
||||
*/
|
||||
.section ".text"
|
||||
.align 2
|
||||
.type _create_MTDCR,@function
|
||||
_create_MTDCR:
|
||||
/*
|
||||
* Build up a 'mtdcr' instruction formatted as follows:
|
||||
*
|
||||
* OPCD | RS | DCRF | XO | CR |
|
||||
* ---------------|--------------|--------------|----|
|
||||
* 0 5 | 6 10 | 11 20 | 21 30 | 31 |
|
||||
* | | DCRN | | |
|
||||
* 31 | %r3 | (5..9|0..4) | 451 | 0 |
|
||||
*
|
||||
* Where:
|
||||
* OPCD = opcode - 31
|
||||
* RS = source register - %r4
|
||||
* DCRF = dest. DCRN # with upper and lower halves swapped
|
||||
* XO = extended opcode - 451
|
||||
* CR = CR[CR0] NOT undefined - 0
|
||||
*/
|
||||
rlwinm r0, r3, 27, 27, 31 /* OPCD = 31 */
|
||||
rlwinm r3, r3, 5, 22, 26
|
||||
or r3, r3, r0
|
||||
slwi r3, r3, 10
|
||||
oris r3, r3, 0x3e40 /* RS = %r4 */
|
||||
ori r3, r3, 451 /* XO = 451 */
|
||||
slwi r3, r3, 1 /* CR = 0 */
|
||||
|
||||
mflr r5
|
||||
stw r3, 0(r5) /* Store instr in set_dcr() */
|
||||
dcbst r0, r5 /* Make sure val is written out */
|
||||
sync /* Wait for write to complete */
|
||||
icbi r0, r5 /* Make sure old instr is dumped */
|
||||
isync /* Wait for icbi to complete */
|
||||
|
||||
blr
|
||||
.Lfe2: .size _create_MTDCR,.Lfe2-_create_MTDCR
|
||||
/* end _create_MTDCR() */
|
||||
|
||||
|
||||
/*
|
||||
* unsigned long get_dcr(unsigned short dcrn)
|
||||
*
|
||||
* Return a given DCR's value.
|
||||
*/
|
||||
/* */
|
||||
/* XXX - This is self modifying code, hence */
|
||||
/* it is in the data section. */
|
||||
/* */
|
||||
.section ".text"
|
||||
.align 2
|
||||
.globl get_dcr
|
||||
.type get_dcr,@function
|
||||
get_dcr:
|
||||
mflr r0 /* Get link register */
|
||||
stwu r1, -32(r1) /* Save back chain and move SP */
|
||||
stw r0, +36(r1) /* Save link register */
|
||||
|
||||
bl _create_MFDCR /* Build following instruction */
|
||||
/* XXX - we build this instuction up on the fly. */
|
||||
.long 0 /* Get DCR's value */
|
||||
|
||||
lwz r0, +36(r1) /* Get saved link register */
|
||||
mtlr r0 /* Restore link register */
|
||||
addi r1, r1, +32 /* Remove frame from stack */
|
||||
blr /* Return to calling function */
|
||||
.Lfe3: .size get_dcr,.Lfe3-get_dcr
|
||||
/* end get_dcr() */
|
||||
|
||||
|
||||
/*
|
||||
* unsigned void set_dcr(unsigned short dcrn, unsigned long value)
|
||||
*
|
||||
* Return a given DCR's value.
|
||||
*/
|
||||
/*
|
||||
* XXX - This is self modifying code, hence
|
||||
* it is in the data section.
|
||||
*/
|
||||
.section ".text"
|
||||
.align 2
|
||||
.globl set_dcr
|
||||
.type set_dcr,@function
|
||||
set_dcr:
|
||||
mflr r0 /* Get link register */
|
||||
stwu r1, -32(r1) /* Save back chain and move SP */
|
||||
stw r0, +36(r1) /* Save link register */
|
||||
|
||||
bl _create_MTDCR /* Build following instruction */
|
||||
/* XXX - we build this instuction up on the fly. */
|
||||
.long 0 /* Set DCR's value */
|
||||
|
||||
lwz r0, +36(r1) /* Get saved link register */
|
||||
mtlr r0 /* Restore link register */
|
||||
addi r1, r1, +32 /* Remove frame from stack */
|
||||
blr /* Return to calling function */
|
||||
.Lfe4: .size set_dcr,.Lfe4-set_dcr
|
||||
/* end set_dcr() */
|
||||
|
||||
|
|
@ -0,0 +1,980 @@
|
|||
/*----------------------------------------------------------------------------+
|
||||
|
|
||||
| This source code has been made available to you by IBM on an AS-IS
|
||||
| basis. Anyone receiving this source is licensed under IBM
|
||||
| copyrights to use it in any way he or she deems fit, including
|
||||
| copying it, modifying it, compiling it, and redistributing it either
|
||||
| with or without modifications. No license under IBM patents or
|
||||
| patent applications is to be implied by the copyright license.
|
||||
|
|
||||
| Any user of this software should understand that IBM cannot provide
|
||||
| technical support for this software and will not be responsible for
|
||||
| any consequences resulting from the use of this software.
|
||||
|
|
||||
| Any person who transfers this source code or any derivative work
|
||||
| must include the IBM copyright notice, this paragraph, and the
|
||||
| preceding two paragraphs in the transferred software.
|
||||
|
|
||||
| COPYRIGHT I B M CORPORATION 1999
|
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||
+----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef __PPC405_H__
|
||||
#define __PPC405_H__
|
||||
|
||||
/* Define bits and masks for real-mode storage attribute control registers */
|
||||
#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
|
||||
#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
|
||||
|
||||
/******************************************************************************
|
||||
* Special for PPC405GP
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* DMA
|
||||
******************************************************************************/
|
||||
#define DMA_DCR_BASE 0x100
|
||||
#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
|
||||
#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
|
||||
#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
|
||||
#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
|
||||
#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
|
||||
#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
|
||||
#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
|
||||
#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
|
||||
#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
|
||||
#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
|
||||
#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
|
||||
#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
|
||||
#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
|
||||
#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
|
||||
#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
|
||||
#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
|
||||
#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
|
||||
#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
|
||||
#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
|
||||
#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
|
||||
#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
|
||||
#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
|
||||
#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
|
||||
|
||||
#ifndef CONFIG_405EP
|
||||
/******************************************************************************
|
||||
* Decompression Controller
|
||||
******************************************************************************/
|
||||
#define DECOMP_DCR_BASE 0x14
|
||||
#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
|
||||
#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
|
||||
/* values for kiar register - indirect addressing of these regs */
|
||||
#define kitor0 0x00 /* index table origin register 0 */
|
||||
#define kitor1 0x01 /* index table origin register 1 */
|
||||
#define kitor2 0x02 /* index table origin register 2 */
|
||||
#define kitor3 0x03 /* index table origin register 3 */
|
||||
#define kaddr0 0x04 /* address decode definition regsiter 0 */
|
||||
#define kaddr1 0x05 /* address decode definition regsiter 1 */
|
||||
#define kconf 0x40 /* decompression core config register */
|
||||
#define kid 0x41 /* decompression core ID register */
|
||||
#define kver 0x42 /* decompression core version # reg */
|
||||
#define kpear 0x50 /* bus error addr reg (PLB addr) */
|
||||
#define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
|
||||
#define kesr0 0x52 /* bus error status reg 0 (R/clear) */
|
||||
#define kesr0s 0x53 /* bus error status reg 0 (set) */
|
||||
/* There are 0x400 of the following registers, from krom0 to krom3ff*/
|
||||
/* Only the first one is given here. */
|
||||
#define krom0 0x400 /* SRAM/ROM read/write */
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
* Power Management
|
||||
******************************************************************************/
|
||||
#ifdef CONFIG_405EX
|
||||
#define POWERMAN_DCR_BASE 0xb0
|
||||
#else
|
||||
#define POWERMAN_DCR_BASE 0xb8
|
||||
#endif
|
||||
#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
|
||||
#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
|
||||
#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
|
||||
|
||||
/******************************************************************************
|
||||
* Extrnal Bus Controller
|
||||
******************************************************************************/
|
||||
/* values for ebccfga register - indirect addressing of these regs */
|
||||
#define pb0cr 0x00 /* periph bank 0 config reg */
|
||||
#define pb1cr 0x01 /* periph bank 1 config reg */
|
||||
#define pb2cr 0x02 /* periph bank 2 config reg */
|
||||
#define pb3cr 0x03 /* periph bank 3 config reg */
|
||||
#define pb4cr 0x04 /* periph bank 4 config reg */
|
||||
#ifndef CONFIG_405EP
|
||||
#define pb5cr 0x05 /* periph bank 5 config reg */
|
||||
#define pb6cr 0x06 /* periph bank 6 config reg */
|
||||
#define pb7cr 0x07 /* periph bank 7 config reg */
|
||||
#endif
|
||||
#define pb0ap 0x10 /* periph bank 0 access parameters */
|
||||
#define pb1ap 0x11 /* periph bank 1 access parameters */
|
||||
#define pb2ap 0x12 /* periph bank 2 access parameters */
|
||||
#define pb3ap 0x13 /* periph bank 3 access parameters */
|
||||
#define pb4ap 0x14 /* periph bank 4 access parameters */
|
||||
#ifndef CONFIG_405EP
|
||||
#define pb5ap 0x15 /* periph bank 5 access parameters */
|
||||
#define pb6ap 0x16 /* periph bank 6 access parameters */
|
||||
#define pb7ap 0x17 /* periph bank 7 access parameters */
|
||||
#endif
|
||||
#define pbear 0x20 /* periph bus error addr reg */
|
||||
#define pbesr0 0x21 /* periph bus error status reg 0 */
|
||||
#define pbesr1 0x22 /* periph bus error status reg 1 */
|
||||
#define epcr 0x23 /* external periph control reg */
|
||||
#define EBC0_CFG 0x23 /* external bus configuration reg */
|
||||
|
||||
#ifdef CONFIG_405EP
|
||||
/******************************************************************************
|
||||
* Control
|
||||
******************************************************************************/
|
||||
#define CNTRL_DCR_BASE 0x0f0
|
||||
#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
|
||||
#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
|
||||
#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
|
||||
#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
|
||||
#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
|
||||
#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
|
||||
|
||||
#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
|
||||
#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
|
||||
#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
|
||||
#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
|
||||
#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
|
||||
#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
|
||||
#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
|
||||
#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
|
||||
#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
|
||||
#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
|
||||
|
||||
/* Bit definitions */
|
||||
#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
|
||||
#define PLLMR0_CPU_DIV_BYPASS 0x00000000
|
||||
#define PLLMR0_CPU_DIV_2 0x00100000
|
||||
#define PLLMR0_CPU_DIV_3 0x00200000
|
||||
#define PLLMR0_CPU_DIV_4 0x00300000
|
||||
|
||||
#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
|
||||
#define PLLMR0_CPU_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_CPU_PLB_DIV_2 0x00010000
|
||||
#define PLLMR0_CPU_PLB_DIV_3 0x00020000
|
||||
#define PLLMR0_CPU_PLB_DIV_4 0x00030000
|
||||
|
||||
#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
|
||||
#define PLLMR0_OPB_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_OPB_PLB_DIV_2 0x00001000
|
||||
#define PLLMR0_OPB_PLB_DIV_3 0x00002000
|
||||
#define PLLMR0_OPB_PLB_DIV_4 0x00003000
|
||||
|
||||
#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
|
||||
#define PLLMR0_EXB_PLB_DIV_2 0x00000000
|
||||
#define PLLMR0_EXB_PLB_DIV_3 0x00000100
|
||||
#define PLLMR0_EXB_PLB_DIV_4 0x00000200
|
||||
#define PLLMR0_EXB_PLB_DIV_5 0x00000300
|
||||
|
||||
#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
|
||||
#define PLLMR0_MAL_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_MAL_PLB_DIV_2 0x00000010
|
||||
#define PLLMR0_MAL_PLB_DIV_3 0x00000020
|
||||
#define PLLMR0_MAL_PLB_DIV_4 0x00000030
|
||||
|
||||
#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
|
||||
#define PLLMR0_PCI_PLB_DIV_1 0x00000000
|
||||
#define PLLMR0_PCI_PLB_DIV_2 0x00000001
|
||||
#define PLLMR0_PCI_PLB_DIV_3 0x00000002
|
||||
#define PLLMR0_PCI_PLB_DIV_4 0x00000003
|
||||
|
||||
#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
|
||||
#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
|
||||
#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
|
||||
#define PLLMR1_FBMUL_DIV_16 0x00000000
|
||||
#define PLLMR1_FBMUL_DIV_1 0x00100000
|
||||
#define PLLMR1_FBMUL_DIV_2 0x00200000
|
||||
#define PLLMR1_FBMUL_DIV_3 0x00300000
|
||||
#define PLLMR1_FBMUL_DIV_4 0x00400000
|
||||
#define PLLMR1_FBMUL_DIV_5 0x00500000
|
||||
#define PLLMR1_FBMUL_DIV_6 0x00600000
|
||||
#define PLLMR1_FBMUL_DIV_7 0x00700000
|
||||
#define PLLMR1_FBMUL_DIV_8 0x00800000
|
||||
#define PLLMR1_FBMUL_DIV_9 0x00900000
|
||||
#define PLLMR1_FBMUL_DIV_10 0x00A00000
|
||||
#define PLLMR1_FBMUL_DIV_11 0x00B00000
|
||||
#define PLLMR1_FBMUL_DIV_12 0x00C00000
|
||||
#define PLLMR1_FBMUL_DIV_13 0x00D00000
|
||||
#define PLLMR1_FBMUL_DIV_14 0x00E00000
|
||||
#define PLLMR1_FBMUL_DIV_15 0x00F00000
|
||||
|
||||
#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
|
||||
#define PLLMR1_FWDVA_DIV_8 0x00000000
|
||||
#define PLLMR1_FWDVA_DIV_7 0x00010000
|
||||
#define PLLMR1_FWDVA_DIV_6 0x00020000
|
||||
#define PLLMR1_FWDVA_DIV_5 0x00030000
|
||||
#define PLLMR1_FWDVA_DIV_4 0x00040000
|
||||
#define PLLMR1_FWDVA_DIV_3 0x00050000
|
||||
#define PLLMR1_FWDVA_DIV_2 0x00060000
|
||||
#define PLLMR1_FWDVA_DIV_1 0x00070000
|
||||
#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
|
||||
#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
|
||||
|
||||
/* Defines for CPC0_EPRCSR register */
|
||||
#define CPC0_EPRCSR_E0NFE 0x80000000
|
||||
#define CPC0_EPRCSR_E1NFE 0x40000000
|
||||
#define CPC0_EPRCSR_E1RPP 0x00000080
|
||||
#define CPC0_EPRCSR_E0RPP 0x00000040
|
||||
#define CPC0_EPRCSR_E1ERP 0x00000020
|
||||
#define CPC0_EPRCSR_E0ERP 0x00000010
|
||||
#define CPC0_EPRCSR_E1PCI 0x00000002
|
||||
#define CPC0_EPRCSR_E0PCI 0x00000001
|
||||
|
||||
/* Defines for CPC0_PCI Register */
|
||||
#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
|
||||
#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
|
||||
#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
|
||||
|
||||
/* Defines for CPC0_BOOR Register */
|
||||
#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
|
||||
|
||||
/* Defines for CPC0_PLLMR1 Register fields */
|
||||
#define PLL_ACTIVE 0x80000000
|
||||
#define CPC0_PLLMR1_SSCS 0x80000000
|
||||
#define PLL_RESET 0x40000000
|
||||
#define CPC0_PLLMR1_PLLR 0x40000000
|
||||
/* Feedback multiplier */
|
||||
#define PLL_FBKDIV 0x00F00000
|
||||
#define CPC0_PLLMR1_FBDV 0x00F00000
|
||||
#define PLL_FBKDIV_16 0x00000000
|
||||
#define PLL_FBKDIV_1 0x00100000
|
||||
#define PLL_FBKDIV_2 0x00200000
|
||||
#define PLL_FBKDIV_3 0x00300000
|
||||
#define PLL_FBKDIV_4 0x00400000
|
||||
#define PLL_FBKDIV_5 0x00500000
|
||||
#define PLL_FBKDIV_6 0x00600000
|
||||
#define PLL_FBKDIV_7 0x00700000
|
||||
#define PLL_FBKDIV_8 0x00800000
|
||||
#define PLL_FBKDIV_9 0x00900000
|
||||
#define PLL_FBKDIV_10 0x00A00000
|
||||
#define PLL_FBKDIV_11 0x00B00000
|
||||
#define PLL_FBKDIV_12 0x00C00000
|
||||
#define PLL_FBKDIV_13 0x00D00000
|
||||
#define PLL_FBKDIV_14 0x00E00000
|
||||
#define PLL_FBKDIV_15 0x00F00000
|
||||
/* Forward A divisor */
|
||||
#define PLL_FWDDIVA 0x00070000
|
||||
#define CPC0_PLLMR1_FWDVA 0x00070000
|
||||
#define PLL_FWDDIVA_8 0x00000000
|
||||
#define PLL_FWDDIVA_7 0x00010000
|
||||
#define PLL_FWDDIVA_6 0x00020000
|
||||
#define PLL_FWDDIVA_5 0x00030000
|
||||
#define PLL_FWDDIVA_4 0x00040000
|
||||
#define PLL_FWDDIVA_3 0x00050000
|
||||
#define PLL_FWDDIVA_2 0x00060000
|
||||
#define PLL_FWDDIVA_1 0x00070000
|
||||
/* Forward B divisor */
|
||||
#define PLL_FWDDIVB 0x00007000
|
||||
#define CPC0_PLLMR1_FWDVB 0x00007000
|
||||
#define PLL_FWDDIVB_8 0x00000000
|
||||
#define PLL_FWDDIVB_7 0x00001000
|
||||
#define PLL_FWDDIVB_6 0x00002000
|
||||
#define PLL_FWDDIVB_5 0x00003000
|
||||
#define PLL_FWDDIVB_4 0x00004000
|
||||
#define PLL_FWDDIVB_3 0x00005000
|
||||
#define PLL_FWDDIVB_2 0x00006000
|
||||
#define PLL_FWDDIVB_1 0x00007000
|
||||
/* PLL tune bits */
|
||||
#define PLL_TUNE_MASK 0x000003FF
|
||||
#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
|
||||
#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
|
||||
#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
|
||||
#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
|
||||
#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
|
||||
#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
|
||||
#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
|
||||
|
||||
/* Defines for CPC0_PLLMR0 Register fields */
|
||||
/* CPU divisor */
|
||||
#define PLL_CPUDIV 0x00300000
|
||||
#define CPC0_PLLMR0_CCDV 0x00300000
|
||||
#define PLL_CPUDIV_1 0x00000000
|
||||
#define PLL_CPUDIV_2 0x00100000
|
||||
#define PLL_CPUDIV_3 0x00200000
|
||||
#define PLL_CPUDIV_4 0x00300000
|
||||
/* PLB divisor */
|
||||
#define PLL_PLBDIV 0x00030000
|
||||
#define CPC0_PLLMR0_CBDV 0x00030000
|
||||
#define PLL_PLBDIV_1 0x00000000
|
||||
#define PLL_PLBDIV_2 0x00010000
|
||||
#define PLL_PLBDIV_3 0x00020000
|
||||
#define PLL_PLBDIV_4 0x00030000
|
||||
/* OPB divisor */
|
||||
#define PLL_OPBDIV 0x00003000
|
||||
#define CPC0_PLLMR0_OPDV 0x00003000
|
||||
#define PLL_OPBDIV_1 0x00000000
|
||||
#define PLL_OPBDIV_2 0x00001000
|
||||
#define PLL_OPBDIV_3 0x00002000
|
||||
#define PLL_OPBDIV_4 0x00003000
|
||||
/* EBC divisor */
|
||||
#define PLL_EXTBUSDIV 0x00000300
|
||||
#define CPC0_PLLMR0_EPDV 0x00000300
|
||||
#define PLL_EXTBUSDIV_2 0x00000000
|
||||
#define PLL_EXTBUSDIV_3 0x00000100
|
||||
#define PLL_EXTBUSDIV_4 0x00000200
|
||||
#define PLL_EXTBUSDIV_5 0x00000300
|
||||
/* MAL divisor */
|
||||
#define PLL_MALDIV 0x00000030
|
||||
#define CPC0_PLLMR0_MPDV 0x00000030
|
||||
#define PLL_MALDIV_1 0x00000000
|
||||
#define PLL_MALDIV_2 0x00000010
|
||||
#define PLL_MALDIV_3 0x00000020
|
||||
#define PLL_MALDIV_4 0x00000030
|
||||
/* PCI divisor */
|
||||
#define PLL_PCIDIV 0x00000003
|
||||
#define CPC0_PLLMR0_PPFD 0x00000003
|
||||
#define PLL_PCIDIV_1 0x00000000
|
||||
#define PLL_PCIDIV_2 0x00000001
|
||||
#define PLL_PCIDIV_3 0x00000002
|
||||
#define PLL_PCIDIV_4 0x00000003
|
||||
|
||||
/*
|
||||
*-------------------------------------------------------------------------------
|
||||
* PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
|
||||
* assuming a 33.3MHz input clock to the 405EP.
|
||||
*-------------------------------------------------------------------------------
|
||||
*/
|
||||
#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
|
||||
#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
|
||||
PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
|
||||
PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_4)
|
||||
#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_2)
|
||||
#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
|
||||
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_3)
|
||||
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
|
||||
PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
|
||||
PLL_MALDIV_1 | PLL_PCIDIV_1)
|
||||
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
|
||||
PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
|
||||
PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
|
||||
|
||||
/*
|
||||
* PLL Voltage Controlled Oscillator (VCO) definitions
|
||||
* Maximum and minimum values (in MHz) for correct PLL operation.
|
||||
*/
|
||||
#define VCO_MIN 500
|
||||
#define VCO_MAX 1000
|
||||
#elif defined(CONFIG_405EZ)
|
||||
#define sdrnand0 0x4000
|
||||
#define sdrultra0 0x4040
|
||||
#define sdrultra1 0x4050
|
||||
#define sdricintstat 0x4510
|
||||
|
||||
#define SDR_NAND0_NDEN 0x80000000
|
||||
#define SDR_NAND0_NDBTEN 0x40000000
|
||||
#define SDR_NAND0_NDBADR_MASK 0x30000000
|
||||
#define SDR_NAND0_NDBPG_MASK 0x0f000000
|
||||
#define SDR_NAND0_NDAREN 0x00800000
|
||||
#define SDR_NAND0_NDRBEN 0x00400000
|
||||
|
||||
#define SDR_ULTRA0_NDGPIOBP 0x80000000
|
||||
#define SDR_ULTRA0_CSN_MASK 0x78000000
|
||||
#define SDR_ULTRA0_CSNSEL0 0x40000000
|
||||
#define SDR_ULTRA0_CSNSEL1 0x20000000
|
||||
#define SDR_ULTRA0_CSNSEL2 0x10000000
|
||||
#define SDR_ULTRA0_CSNSEL3 0x08000000
|
||||
#define SDR_ULTRA0_EBCRDYEN 0x04000000
|
||||
#define SDR_ULTRA0_SPISSINEN 0x02000000
|
||||
#define SDR_ULTRA0_NFSRSTEN 0x01000000
|
||||
|
||||
#define SDR_ULTRA1_LEDNENABLE 0x40000000
|
||||
|
||||
#define SDR_ICRX_STAT 0x80000000
|
||||
#define SDR_ICTX0_STAT 0x40000000
|
||||
#define SDR_ICTX1_STAT 0x20000000
|
||||
|
||||
#define SDR_PINSTP 0x40
|
||||
|
||||
/******************************************************************************
|
||||
* Control
|
||||
******************************************************************************/
|
||||
/* CPR Registers */
|
||||
#define cprclkupd 0x020 /* CPR_CLKUPD */
|
||||
#define cprpllc 0x040 /* CPR_PLLC */
|
||||
#define cprplld 0x060 /* CPR_PLLD */
|
||||
#define cprprimad 0x080 /* CPR_PRIMAD */
|
||||
#define cprperd0 0x0e0 /* CPR_PERD0 */
|
||||
#define cprperd1 0x0e1 /* CPR_PERD1 */
|
||||
#define cprperc0 0x180 /* CPR_PERC0 */
|
||||
#define cprmisc0 0x181 /* CPR_MISC0 */
|
||||
#define cprmisc1 0x182 /* CPR_MISC1 */
|
||||
|
||||
#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
|
||||
#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
|
||||
#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
|
||||
|
||||
#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
|
||||
|
||||
#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
|
||||
#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
|
||||
#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
|
||||
|
||||
#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
|
||||
#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
|
||||
#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
|
||||
#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
|
||||
|
||||
#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
|
||||
#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
|
||||
#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
|
||||
#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
|
||||
|
||||
#else /* #ifdef CONFIG_405EP */
|
||||
/******************************************************************************
|
||||
* Control
|
||||
******************************************************************************/
|
||||
#define CNTRL_DCR_BASE 0x0b0
|
||||
#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
|
||||
#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
|
||||
#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
|
||||
#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
|
||||
#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
|
||||
|
||||
#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
|
||||
#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
|
||||
#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
|
||||
|
||||
/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
|
||||
#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */
|
||||
#define CPC0_ECR (0xaa) /* edge conditioner register */
|
||||
|
||||
#define ecr (0xaa) /* edge conditioner register (405gpr) */
|
||||
|
||||
/* Bit definitions */
|
||||
#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
|
||||
#define PLLMR_FWD_DIV_BYPASS 0xE0000000
|
||||
#define PLLMR_FWD_DIV_3 0xA0000000
|
||||
#define PLLMR_FWD_DIV_4 0x80000000
|
||||
#define PLLMR_FWD_DIV_6 0x40000000
|
||||
|
||||
#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
|
||||
#define PLLMR_FB_DIV_1 0x02000000
|
||||
#define PLLMR_FB_DIV_2 0x04000000
|
||||
#define PLLMR_FB_DIV_3 0x06000000
|
||||
#define PLLMR_FB_DIV_4 0x08000000
|
||||
|
||||
#define PLLMR_TUNING_MASK 0x01F80000
|
||||
|
||||
#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
|
||||
#define PLLMR_CPU_PLB_DIV_1 0x00000000
|
||||
#define PLLMR_CPU_PLB_DIV_2 0x00020000
|
||||
#define PLLMR_CPU_PLB_DIV_3 0x00040000
|
||||
#define PLLMR_CPU_PLB_DIV_4 0x00060000
|
||||
|
||||
#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
|
||||
#define PLLMR_OPB_PLB_DIV_1 0x00000000
|
||||
#define PLLMR_OPB_PLB_DIV_2 0x00008000
|
||||
#define PLLMR_OPB_PLB_DIV_3 0x00010000
|
||||
#define PLLMR_OPB_PLB_DIV_4 0x00018000
|
||||
|
||||
#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
|
||||
#define PLLMR_PCI_PLB_DIV_1 0x00000000
|
||||
#define PLLMR_PCI_PLB_DIV_2 0x00002000
|
||||
#define PLLMR_PCI_PLB_DIV_3 0x00004000
|
||||
#define PLLMR_PCI_PLB_DIV_4 0x00006000
|
||||
|
||||
#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
|
||||
#define PLLMR_EXB_PLB_DIV_2 0x00000000
|
||||
#define PLLMR_EXB_PLB_DIV_3 0x00000800
|
||||
#define PLLMR_EXB_PLB_DIV_4 0x00001000
|
||||
#define PLLMR_EXB_PLB_DIV_5 0x00001800
|
||||
|
||||
/* definitions for PPC405GPr (new mode strapping) */
|
||||
#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
|
||||
|
||||
#define PSR_PLL_FWD_MASK 0xC0000000
|
||||
#define PSR_PLL_FDBACK_MASK 0x30000000
|
||||
#define PSR_PLL_TUNING_MASK 0x0E000000
|
||||
#define PSR_PLB_CPU_MASK 0x01800000
|
||||
#define PSR_OPB_PLB_MASK 0x00600000
|
||||
#define PSR_PCI_PLB_MASK 0x00180000
|
||||
#define PSR_EB_PLB_MASK 0x00060000
|
||||
#define PSR_ROM_WIDTH_MASK 0x00018000
|
||||
#define PSR_ROM_LOC 0x00004000
|
||||
#define PSR_PCI_ASYNC_EN 0x00001000
|
||||
#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
|
||||
#define PSR_PCI_ARBIT_EN 0x00000400
|
||||
#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
|
||||
|
||||
#ifndef CONFIG_IOP480
|
||||
/*
|
||||
* PLL Voltage Controlled Oscillator (VCO) definitions
|
||||
* Maximum and minimum values (in MHz) for correct PLL operation.
|
||||
*/
|
||||
#define VCO_MIN 400
|
||||
#define VCO_MAX 800
|
||||
#endif /* #ifndef CONFIG_IOP480 */
|
||||
#endif /* #ifdef CONFIG_405EP */
|
||||
|
||||
/******************************************************************************
|
||||
* Memory Access Layer
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define MAL_DCR_BASE 0x380
|
||||
#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
|
||||
#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
|
||||
#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
|
||||
#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
|
||||
#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
|
||||
#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
|
||||
#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
|
||||
#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
|
||||
/* 0x08-0x0F Reserved */
|
||||
#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
|
||||
#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
|
||||
#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
|
||||
#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
|
||||
/* 0x14-0x1F Reserved */
|
||||
#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
|
||||
#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
|
||||
#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
|
||||
#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
|
||||
#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
|
||||
#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
|
||||
#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
|
||||
#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
|
||||
#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
|
||||
#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
|
||||
#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
|
||||
#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
|
||||
#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
|
||||
#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
|
||||
#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
|
||||
#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
|
||||
#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
|
||||
#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
|
||||
#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
|
||||
#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
|
||||
#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
|
||||
#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
|
||||
#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
|
||||
#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
|
||||
#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
|
||||
#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
|
||||
#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
|
||||
#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
|
||||
#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
|
||||
#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
|
||||
#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
|
||||
#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
|
||||
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
|
||||
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
|
||||
#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
|
||||
#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
|
||||
#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
|
||||
#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
|
||||
#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
|
||||
#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
|
||||
#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
|
||||
#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
|
||||
#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
|
||||
#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
|
||||
#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
|
||||
#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
|
||||
#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
|
||||
#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
|
||||
#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
|
||||
#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
|
||||
#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
|
||||
#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
|
||||
#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
|
||||
#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
|
||||
#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
|
||||
#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
|
||||
#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
|
||||
#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
|
||||
#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
|
||||
#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
|
||||
#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
|
||||
#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
|
||||
#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
|
||||
#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
|
||||
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
|
||||
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
|
||||
#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
|
||||
#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
|
||||
#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
|
||||
#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
|
||||
#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
|
||||
#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
|
||||
#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
|
||||
#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
|
||||
#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
|
||||
#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
|
||||
#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
|
||||
#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
|
||||
#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
|
||||
#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
|
||||
#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
|
||||
#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
|
||||
#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
|
||||
#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
|
||||
#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
|
||||
#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
|
||||
#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
|
||||
#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
|
||||
#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
|
||||
#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
|
||||
#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
|
||||
#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
|
||||
#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
|
||||
#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
|
||||
#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
|
||||
#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
|
||||
|
||||
#else /* !defined(CONFIG_405EZ) */
|
||||
|
||||
#define MAL_DCR_BASE 0x180
|
||||
#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
|
||||
#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
|
||||
#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
|
||||
#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
|
||||
#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
|
||||
#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
|
||||
#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
|
||||
#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
|
||||
#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
|
||||
#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
|
||||
#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
|
||||
#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
|
||||
#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
|
||||
#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
|
||||
#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
|
||||
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
|
||||
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
|
||||
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
|
||||
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
|
||||
#endif /* defined(CONFIG_405EZ) */
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| IIC Register Offsets
|
||||
'----------------------------------------------------------------------------*/
|
||||
#define IICMDBUF 0x00
|
||||
#define IICSDBUF 0x02
|
||||
#define IICLMADR 0x04
|
||||
#define IICHMADR 0x05
|
||||
#define IICCNTL 0x06
|
||||
#define IICMDCNTL 0x07
|
||||
#define IICSTS 0x08
|
||||
#define IICEXTSTS 0x09
|
||||
#define IICLSADR 0x0A
|
||||
#define IICHSADR 0x0B
|
||||
#define IICCLKDIV 0x0C
|
||||
#define IICINTRMSK 0x0D
|
||||
#define IICXFRCNT 0x0E
|
||||
#define IICXTCNTLSS 0x0F
|
||||
#define IICDIRECTCNTL 0x10
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
| UART Register Offsets
|
||||
'----------------------------------------------------------------------------*/
|
||||
#define DATA_REG 0x00
|
||||
#define DL_LSB 0x00
|
||||
#define DL_MSB 0x01
|
||||
#define INT_ENABLE 0x01
|
||||
#define FIFO_CONTROL 0x02
|
||||
#define LINE_CONTROL 0x03
|
||||
#define MODEM_CONTROL 0x04
|
||||
#define LINE_STATUS 0x05
|
||||
#define MODEM_STATUS 0x06
|
||||
#define SCRATCH 0x07
|
||||
|
||||
/******************************************************************************
|
||||
* On Chip Memory
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
#define OCM_DCR_BASE 0x020
|
||||
#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
|
||||
#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
|
||||
#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
|
||||
#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
|
||||
#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
|
||||
#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
|
||||
#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
|
||||
#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
|
||||
#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
|
||||
#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
|
||||
#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
|
||||
#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
|
||||
#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
|
||||
#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
|
||||
#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
|
||||
#else
|
||||
#define OCM_DCR_BASE 0x018
|
||||
#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
|
||||
#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
|
||||
#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
|
||||
#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
|
||||
#endif /* CONFIG_405EZ */
|
||||
|
||||
/******************************************************************************
|
||||
* GPIO macro register defines
|
||||
******************************************************************************/
|
||||
#if defined(CONFIG_405EZ)
|
||||
/* Only the 405EZ has 2 GPIOs */
|
||||
#define GPIO_BASE 0xEF600700
|
||||
#define GPIO0_OR (GPIO_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||||
#define GPIO0_OSRL (GPIO_BASE+0x8)
|
||||
#define GPIO0_OSRH (GPIO_BASE+0xC)
|
||||
#define GPIO0_TSRL (GPIO_BASE+0x10)
|
||||
#define GPIO0_TSRH (GPIO_BASE+0x14)
|
||||
#define GPIO0_ODR (GPIO_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE+0x1C)
|
||||
#define GPIO0_RR1 (GPIO_BASE+0x20)
|
||||
#define GPIO0_RR2 (GPIO_BASE+0x24)
|
||||
#define GPIO0_RR3 (GPIO_BASE+0x28)
|
||||
#define GPIO0_ISR1L (GPIO_BASE+0x30)
|
||||
#define GPIO0_ISR1H (GPIO_BASE+0x34)
|
||||
#define GPIO0_ISR2L (GPIO_BASE+0x38)
|
||||
#define GPIO0_ISR2H (GPIO_BASE+0x3C)
|
||||
#define GPIO0_ISR3L (GPIO_BASE+0x40)
|
||||
#define GPIO0_ISR3H (GPIO_BASE+0x44)
|
||||
|
||||
#define GPIO1_BASE 0xEF600800
|
||||
#define GPIO1_OR (GPIO1_BASE+0x0)
|
||||
#define GPIO1_TCR (GPIO1_BASE+0x4)
|
||||
#define GPIO1_OSRL (GPIO1_BASE+0x8)
|
||||
#define GPIO1_OSRH (GPIO1_BASE+0xC)
|
||||
#define GPIO1_TSRL (GPIO1_BASE+0x10)
|
||||
#define GPIO1_TSRH (GPIO1_BASE+0x14)
|
||||
#define GPIO1_ODR (GPIO1_BASE+0x18)
|
||||
#define GPIO1_IR (GPIO1_BASE+0x1C)
|
||||
#define GPIO1_RR1 (GPIO1_BASE+0x20)
|
||||
#define GPIO1_RR2 (GPIO1_BASE+0x24)
|
||||
#define GPIO1_RR3 (GPIO1_BASE+0x28)
|
||||
#define GPIO1_ISR1L (GPIO1_BASE+0x30)
|
||||
#define GPIO1_ISR1H (GPIO1_BASE+0x34)
|
||||
#define GPIO1_ISR2L (GPIO1_BASE+0x38)
|
||||
#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
|
||||
#define GPIO1_ISR3L (GPIO1_BASE+0x40)
|
||||
#define GPIO1_ISR3H (GPIO1_BASE+0x44)
|
||||
|
||||
#elif defined(CONFIG_405EX)
|
||||
#define GPIO_BASE 0xEF600800
|
||||
#define GPIO0_OR (GPIO_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||||
#define GPIO0_OSRL (GPIO_BASE+0x8)
|
||||
#define GPIO0_OSRH (GPIO_BASE+0xC)
|
||||
#define GPIO0_TSRL (GPIO_BASE+0x10)
|
||||
#define GPIO0_TSRH (GPIO_BASE+0x14)
|
||||
#define GPIO0_ODR (GPIO_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE+0x1C)
|
||||
#define GPIO0_RR1 (GPIO_BASE+0x20)
|
||||
#define GPIO0_RR2 (GPIO_BASE+0x24)
|
||||
#define GPIO0_ISR1L (GPIO_BASE+0x30)
|
||||
#define GPIO0_ISR1H (GPIO_BASE+0x34)
|
||||
#define GPIO0_ISR2L (GPIO_BASE+0x38)
|
||||
#define GPIO0_ISR2H (GPIO_BASE+0x3C)
|
||||
#define GPIO0_ISR3L (GPIO_BASE+0x40)
|
||||
#define GPIO0_ISR3H (GPIO_BASE+0x44)
|
||||
|
||||
#else /* !405EZ */
|
||||
|
||||
#define GPIO_BASE 0xEF600700
|
||||
#define GPIO0_OR (GPIO_BASE+0x0)
|
||||
#define GPIO0_TCR (GPIO_BASE+0x4)
|
||||
#define GPIO0_OSRH (GPIO_BASE+0x8)
|
||||
#define GPIO0_OSRL (GPIO_BASE+0xC)
|
||||
#define GPIO0_TSRH (GPIO_BASE+0x10)
|
||||
#define GPIO0_TSRL (GPIO_BASE+0x14)
|
||||
#define GPIO0_ODR (GPIO_BASE+0x18)
|
||||
#define GPIO0_IR (GPIO_BASE+0x1C)
|
||||
#define GPIO0_RR1 (GPIO_BASE+0x20)
|
||||
#define GPIO0_RR2 (GPIO_BASE+0x24)
|
||||
#define GPIO0_ISR1H (GPIO_BASE+0x30)
|
||||
#define GPIO0_ISR1L (GPIO_BASE+0x34)
|
||||
#define GPIO0_ISR2H (GPIO_BASE+0x38)
|
||||
#define GPIO0_ISR2L (GPIO_BASE+0x3C)
|
||||
|
||||
#endif /* CONFIG_405EZ */
|
||||
|
||||
#define GPIO0_BASE GPIO_BASE
|
||||
|
||||
#if defined(CONFIG_405EX)
|
||||
#define SDR0_SRST 0x0200
|
||||
|
||||
/*
|
||||
* Software Reset Register
|
||||
*/
|
||||
#define SDR0_SRST_BGO PPC_REG_VAL(0, 1)
|
||||
#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1)
|
||||
#define SDR0_SRST_EBC PPC_REG_VAL(2, 1)
|
||||
#define SDR0_SRST_OPB PPC_REG_VAL(3, 1)
|
||||
#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1)
|
||||
#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1)
|
||||
#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1)
|
||||
#define SDR0_SRST_BGI PPC_REG_VAL(7, 1)
|
||||
#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1)
|
||||
#define SDR0_SRST_GPT PPC_REG_VAL(9, 1)
|
||||
#define SDR0_SRST_DMC PPC_REG_VAL(10, 1)
|
||||
#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1)
|
||||
#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1)
|
||||
#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1)
|
||||
#define SDR0_SRST_CPM PPC_REG_VAL(14, 1)
|
||||
#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1)
|
||||
#define SDR0_SRST_UIC PPC_REG_VAL(16, 1)
|
||||
#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1)
|
||||
#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1)
|
||||
#define SDR0_SRST_SCP PPC_REG_VAL(19, 1)
|
||||
#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1)
|
||||
#define SDR0_SRST_DMA PPC_REG_VAL(21, 1)
|
||||
#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1)
|
||||
#define SDR0_SRST_MAL PPC_REG_VAL(23, 1)
|
||||
#define SDR0_SRST_EBM PPC_REG_VAL(24, 1)
|
||||
#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1)
|
||||
#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1)
|
||||
#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1)
|
||||
#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1)
|
||||
#define SDR0_SRST_PKP PPC_REG_VAL(29, 1)
|
||||
#define SDR0_SRST_AHB PPC_REG_VAL(30, 1)
|
||||
#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1)
|
||||
|
||||
#define sdr_uart0 0x0120 /* UART0 Config */
|
||||
#define sdr_uart1 0x0121 /* UART1 Config */
|
||||
#define sdr_mfr 0x4300 /* SDR0_MFR reg */
|
||||
|
||||
/* Defines for CPC0_EPRCSR register */
|
||||
#define CPC0_EPRCSR_E0NFE 0x80000000
|
||||
#define CPC0_EPRCSR_E1NFE 0x40000000
|
||||
#define CPC0_EPRCSR_E1RPP 0x00000080
|
||||
#define CPC0_EPRCSR_E0RPP 0x00000040
|
||||
#define CPC0_EPRCSR_E1ERP 0x00000020
|
||||
#define CPC0_EPRCSR_E0ERP 0x00000010
|
||||
#define CPC0_EPRCSR_E1PCI 0x00000002
|
||||
#define CPC0_EPRCSR_E0PCI 0x00000001
|
||||
|
||||
#define cpr0_clkupd 0x020
|
||||
#define cpr0_pllc 0x040
|
||||
#define cpr0_plld 0x060
|
||||
#define cpr0_cpud 0x080
|
||||
#define cpr0_plbd 0x0a0
|
||||
#define cpr0_opbd 0x0c0
|
||||
#define cpr0_perd 0x0e0
|
||||
#define cpr0_ahbd 0x100
|
||||
#define cpr0_icfg 0x140
|
||||
|
||||
#define SDR_PINSTP 0x0040
|
||||
#define sdr_sdcs 0x0060
|
||||
|
||||
#define SDR0_SDCS_SDD (0x80000000 >> 31)
|
||||
|
||||
/* CUST0 Customer Configuration Register0 */
|
||||
#define SDR0_CUST0 0x4000
|
||||
#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
|
||||
#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
|
||||
#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
|
||||
#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
|
||||
|
||||
#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
|
||||
#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
|
||||
#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
|
||||
|
||||
#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
|
||||
#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
|
||||
#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
|
||||
|
||||
#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
|
||||
#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
|
||||
#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
|
||||
|
||||
#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
|
||||
#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
|
||||
#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
|
||||
|
||||
#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
|
||||
#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
|
||||
#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
|
||||
|
||||
#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
|
||||
#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
|
||||
#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
|
||||
|
||||
#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
|
||||
#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
|
||||
#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
|
||||
|
||||
#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
|
||||
#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
|
||||
#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
|
||||
|
||||
#define SDR0_PFC0 0x4100
|
||||
#define SDR0_PFC1 0x4101
|
||||
#define SDR0_PFC1_U1ME 0x02000000
|
||||
#define SDR0_PFC1_U0ME 0x00080000
|
||||
#define SDR0_PFC1_U0IM 0x00040000
|
||||
#define SDR0_PFC1_SIS 0x00020000
|
||||
#define SDR0_PFC1_DMAAEN 0x00010000
|
||||
#define SDR0_PFC1_DMADEN 0x00008000
|
||||
#define SDR0_PFC1_USBEN 0x00004000
|
||||
#define SDR0_PFC1_AHBSWAP 0x00000020
|
||||
#define SDR0_PFC1_USBBIGEN 0x00000010
|
||||
#define SDR0_PFC1_GPT_FREQ 0x0000000f
|
||||
#endif
|
||||
|
||||
/* General Purpose Timer (GPT) Register Offsets */
|
||||
#define GPT0_TBC 0x00000000
|
||||
#define GPT0_IM 0x00000018
|
||||
#define GPT0_ISS 0x0000001C
|
||||
#define GPT0_ISC 0x00000020
|
||||
#define GPT0_IE 0x00000024
|
||||
#define GPT0_COMP0 0x00000080
|
||||
#define GPT0_COMP1 0x00000084
|
||||
#define GPT0_COMP2 0x00000088
|
||||
#define GPT0_COMP3 0x0000008C
|
||||
#define GPT0_COMP4 0x00000090
|
||||
#define GPT0_COMP5 0x00000094
|
||||
#define GPT0_COMP6 0x00000098
|
||||
#define GPT0_MASK0 0x000000C0
|
||||
#define GPT0_MASK1 0x000000C4
|
||||
#define GPT0_MASK2 0x000000C8
|
||||
#define GPT0_MASK3 0x000000CC
|
||||
#define GPT0_MASK4 0x000000D0
|
||||
#define GPT0_MASK5 0x000000D4
|
||||
#define GPT0_MASK6 0x000000D8
|
||||
#define GPT0_DCT0 0x00000110
|
||||
#define GPT0_DCIS 0x0000011C
|
||||
|
||||
#endif /* __PPC405_H__ */
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
#ifndef _VECNUMS_H_
|
||||
#define _VECNUMS_H_
|
||||
|
||||
#define VECNUM_U0 0 /* UART0 */
|
||||
#define VECNUM_U1 1 /* UART1 */
|
||||
#define VECNUM_D0 5 /* DMA channel 0 */
|
||||
#define VECNUM_D1 6 /* DMA channel 1 */
|
||||
#define VECNUM_D2 7 /* DMA channel 2 */
|
||||
#define VECNUM_D3 8 /* DMA channel 3 */
|
||||
#define VECNUM_EWU0 9 /* Ethernet wakeup */
|
||||
#define VECNUM_MS 10 /* MAL SERR */
|
||||
#define VECNUM_MTE 11 /* MAL TXEOB */
|
||||
#define VECNUM_MRE 12 /* MAL RXEOB */
|
||||
#define VECNUM_TXDE 13 /* MAL TXDE */
|
||||
#define VECNUM_RXDE 14 /* MAL RXDE */
|
||||
#define VECNUM_ETH0 15 /* Ethernet interrupt status */
|
||||
#define VECNUM_EIR0 25 /* External interrupt 0 */
|
||||
#define VECNUM_EIR1 26 /* External interrupt 1 */
|
||||
#define VECNUM_EIR2 27 /* External interrupt 2 */
|
||||
#define VECNUM_EIR3 28 /* External interrupt 3 */
|
||||
#define VECNUM_EIR4 29 /* External interrupt 4 */
|
||||
#define VECNUM_EIR5 30 /* External interrupt 5 */
|
||||
#define VECNUM_EIR6 31 /* External interrupt 6 */
|
||||
|
||||
#endif /* _VECNUMS_H_ */
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
#ifndef _PPC4xx_UIC_H_
|
||||
#define _PPC4xx_UIC_H_
|
||||
|
||||
/*
|
||||
* Define the number of UIC's
|
||||
*/
|
||||
#define UIC_MAX 1
|
||||
#define IRQ_MAX UIC_MAX * 32
|
||||
|
||||
/* UIC0 dcr base address */
|
||||
#define UIC0_DCR_BASE 0xc0
|
||||
|
||||
/*
|
||||
* UIC register
|
||||
*/
|
||||
#define UIC_SR 0x0 /* UIC status */
|
||||
#define UIC_ER 0x2 /* UIC enable */
|
||||
#define UIC_CR 0x3 /* UIC critical */
|
||||
#define UIC_PR 0x4 /* UIC polarity */
|
||||
#define UIC_TR 0x5 /* UIC triggering */
|
||||
#define UIC_MSR 0x6 /* UIC masked status */
|
||||
#define UIC_VR 0x7 /* UIC vector */
|
||||
#define UIC_VCR 0x8 /* UIC vector configuration */
|
||||
|
||||
#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
|
||||
#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
|
||||
#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
|
||||
#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
|
||||
#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
|
||||
#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
|
||||
#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
|
||||
#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
|
||||
|
||||
/* The following is for compatibility with 405 code */
|
||||
#define uicsr uic0sr
|
||||
#define uicer uic0er
|
||||
#define uiccr uic0cr
|
||||
#define uicpr uic0pr
|
||||
#define uictr uic0tr
|
||||
#define uicmsr uic0msr
|
||||
#define uicvr uic0vr
|
||||
#define uicvcr uic0vcr
|
||||
|
||||
/* the interrupt vector definitions */
|
||||
#define VECNUM_MAL_SERR 10
|
||||
#define VECNUM_MAL_TXEOB 11
|
||||
#define VECNUM_MAL_RXEOB 12
|
||||
#define VECNUM_MAL_TXDE 13
|
||||
#define VECNUM_MAL_RXDE 14
|
||||
#define VECNUM_ETH0 15
|
||||
#define VECNUM_ETH1_OFFS 2
|
||||
#define VECNUM_EIRQ6 29
|
||||
|
||||
/*
|
||||
* Mask definitions (used for example in 4xx_enet.c)
|
||||
*/
|
||||
#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
|
||||
/* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */
|
||||
#define UIC_NR(vec) ((vec) >> 5)
|
||||
|
||||
#endif /* _PPC4xx_UIC_H_ */
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/*----------------------------------------------------------------------------+
|
||||
|
|
||||
| This source code has been made available to you by IBM on an AS-IS
|
||||
| basis. Anyone receiving this source is licensed under IBM
|
||||
| copyrights to use it in any way he or she deems fit, including
|
||||
| copying it, modifying it, compiling it, and redistributing it either
|
||||
| with or without modifications. No license under IBM patents or
|
||||
| patent applications is to be implied by the copyright license.
|
||||
|
|
||||
| Any user of this software should understand that IBM cannot provide
|
||||
| technical support for this software and will not be responsible for
|
||||
| any consequences resulting from the use of this software.
|
||||
|
|
||||
| Any person who transfers this source code or any derivative work
|
||||
| must include the IBM copyright notice, this paragraph, and the
|
||||
| preceding two paragraphs in the transferred software.
|
||||
|
|
||||
| COPYRIGHT I B M CORPORATION 1999
|
||||
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
|
||||
+----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef __PPC4XX_H__
|
||||
#define __PPC4XX_H__
|
||||
|
||||
/*
|
||||
* Configure which SDRAM/DDR/DDR2 controller is equipped
|
||||
*/
|
||||
#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
|
||||
|
||||
#include <asm/ppc405.h>
|
||||
#include <asm/ppc4xx-uic.h>
|
||||
|
||||
/*
|
||||
* Macro for generating register field mnemonics
|
||||
*/
|
||||
#define PPC_REG_BITS 32
|
||||
#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
|
||||
|
||||
/*
|
||||
* Elide casts when assembling register mnemonics
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#define static_cast(type, val) (type)(val)
|
||||
#else
|
||||
#define static_cast(type, val) (val)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Common stuff for 4xx (405 and 440)
|
||||
*/
|
||||
|
||||
#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
|
||||
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
|
||||
|
||||
#define RESET_VECTOR 0xfffffffc
|
||||
#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
|
||||
line aligned data. */
|
||||
|
||||
#define CPR0_DCR_BASE 0x0C
|
||||
#define cprcfga (CPR0_DCR_BASE+0x0)
|
||||
#define cprcfgd (CPR0_DCR_BASE+0x1)
|
||||
|
||||
#define SDR_DCR_BASE 0x0E
|
||||
#define sdrcfga (SDR_DCR_BASE+0x0)
|
||||
#define sdrcfgd (SDR_DCR_BASE+0x1)
|
||||
|
||||
#define SDRAM_DCR_BASE 0x10
|
||||
#define memcfga (SDRAM_DCR_BASE+0x0)
|
||||
#define memcfgd (SDRAM_DCR_BASE+0x1)
|
||||
|
||||
#define EBC_DCR_BASE 0x12
|
||||
#define ebccfga (EBC_DCR_BASE+0x0)
|
||||
#define ebccfgd (EBC_DCR_BASE+0x1)
|
||||
|
||||
/*
|
||||
* Macros for indirect DCR access
|
||||
*/
|
||||
#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0)
|
||||
#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0)
|
||||
|
||||
#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0)
|
||||
#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0)
|
||||
|
||||
#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0)
|
||||
#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0)
|
||||
|
||||
#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0)
|
||||
#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned long freqDDR;
|
||||
unsigned long freqEBC;
|
||||
unsigned long freqOPB;
|
||||
unsigned long freqPCI;
|
||||
unsigned long freqPLB;
|
||||
unsigned long freqTmrClk;
|
||||
unsigned long freqUART;
|
||||
unsigned long freqProcessor;
|
||||
unsigned long freqVCOHz;
|
||||
unsigned long freqVCOMhz; /* in MHz */
|
||||
unsigned long pciClkSync; /* PCI clock is synchronous */
|
||||
unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
|
||||
unsigned long pllExtBusDiv;
|
||||
unsigned long pllFbkDiv;
|
||||
unsigned long pllFwdDiv;
|
||||
unsigned long pllFwdDivA;
|
||||
unsigned long pllFwdDivB;
|
||||
unsigned long pllOpbDiv;
|
||||
unsigned long pllPciDiv;
|
||||
unsigned long pllPlbDiv;
|
||||
} PPC4xx_SYS_INFO;
|
||||
|
||||
static inline rt_uint32_t get_mcsr(void)
|
||||
{
|
||||
rt_uint32_t val;
|
||||
|
||||
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline void set_mcsr(rt_uint32_t val)
|
||||
{
|
||||
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* for multi-cpu support */
|
||||
#define NA_OR_UNKNOWN_CPU -1
|
||||
|
||||
#endif /* __PPC4XX_H__ */
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* WARNING! This file is automatically generated - DO NOT EDIT!
|
||||
*/
|
||||
#define STACK_FRAME_OVERHEAD 16
|
||||
#define INT_FRAME_SIZE 192
|
||||
#define GPR0 16
|
||||
#define GPR1 20
|
||||
#define GPR2 24
|
||||
#define GPR3 28
|
||||
#define GPR4 32
|
||||
#define GPR5 36
|
||||
#define GPR6 40
|
||||
#define GPR7 44
|
||||
#define GPR8 48
|
||||
#define GPR9 52
|
||||
#define GPR10 56
|
||||
#define GPR11 60
|
||||
#define GPR12 64
|
||||
#define GPR13 68
|
||||
#define GPR14 72
|
||||
#define GPR15 76
|
||||
#define GPR16 80
|
||||
#define GPR17 84
|
||||
#define GPR18 88
|
||||
#define GPR19 92
|
||||
#define GPR20 96
|
||||
#define GPR21 100
|
||||
#define GPR22 104
|
||||
#define GPR23 108
|
||||
#define GPR24 112
|
||||
#define GPR25 116
|
||||
#define GPR26 120
|
||||
#define GPR27 124
|
||||
#define GPR28 128
|
||||
#define GPR29 132
|
||||
#define GPR30 136
|
||||
#define GPR31 140
|
||||
#define _NIP 144
|
||||
#define _MSR 148
|
||||
#define ORIG_GPR3 152
|
||||
#define _CTR 156
|
||||
#define _LINK 160
|
||||
#define _XER 164
|
||||
#define _CCR 168
|
||||
#define _MQ 172
|
||||
#define TRAP 176
|
||||
#define _DAR 180
|
||||
#define _DSISR 184
|
||||
#define RESULT 188
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,107 @@
|
|||
#ifndef _PPC_PTRACE_H
|
||||
#define _PPC_PTRACE_H
|
||||
|
||||
/*
|
||||
* This struct defines the way the registers are stored on the
|
||||
* kernel stack during a system call or other kernel entry.
|
||||
*
|
||||
* this should only contain volatile regs
|
||||
* since we can keep non-volatile in the thread_struct
|
||||
* should set this up when only volatiles are saved
|
||||
* by intr code.
|
||||
*
|
||||
* Since this is going on the stack, *CARE MUST BE TAKEN* to insure
|
||||
* that the overall structure is a multiple of 16 bytes in length.
|
||||
*
|
||||
* Note that the offsets of the fields in this struct correspond with
|
||||
* the PT_* values below. This simplifies arch/ppc/kernel/ptrace.c.
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_PPC64BRIDGE
|
||||
#define PPC_REG unsigned long /*long*/
|
||||
#else
|
||||
#define PPC_REG unsigned long
|
||||
#endif
|
||||
struct pt_regs {
|
||||
PPC_REG gpr[32];
|
||||
PPC_REG nip;
|
||||
PPC_REG msr;
|
||||
PPC_REG orig_gpr3; /* Used for restarting system calls */
|
||||
PPC_REG ctr;
|
||||
PPC_REG link;
|
||||
PPC_REG xer;
|
||||
PPC_REG ccr;
|
||||
PPC_REG mq; /* 601 only (not used at present) */
|
||||
/* Used on APUS to hold IPL value. */
|
||||
PPC_REG trap; /* Reason for being here */
|
||||
PPC_REG dar; /* Fault registers */
|
||||
PPC_REG dsisr;
|
||||
PPC_REG result; /* Result of a system call */
|
||||
}__attribute__((packed)) CELL_STACK_FRAME_t;
|
||||
#endif
|
||||
|
||||
#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */
|
||||
|
||||
/* Size of stack frame allocated when calling signal handler. */
|
||||
#define __SIGNAL_FRAMESIZE 64
|
||||
|
||||
#define instruction_pointer(regs) ((regs)->nip)
|
||||
#define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
|
||||
|
||||
/*
|
||||
* Offsets used by 'ptrace' system call interface.
|
||||
* These can't be changed without breaking binary compatibility
|
||||
* with MkLinux, etc.
|
||||
*/
|
||||
#define PT_R0 0
|
||||
#define PT_R1 1
|
||||
#define PT_R2 2
|
||||
#define PT_R3 3
|
||||
#define PT_R4 4
|
||||
#define PT_R5 5
|
||||
#define PT_R6 6
|
||||
#define PT_R7 7
|
||||
#define PT_R8 8
|
||||
#define PT_R9 9
|
||||
#define PT_R10 10
|
||||
#define PT_R11 11
|
||||
#define PT_R12 12
|
||||
#define PT_R13 13
|
||||
#define PT_R14 14
|
||||
#define PT_R15 15
|
||||
#define PT_R16 16
|
||||
#define PT_R17 17
|
||||
#define PT_R18 18
|
||||
#define PT_R19 19
|
||||
#define PT_R20 20
|
||||
#define PT_R21 21
|
||||
#define PT_R22 22
|
||||
#define PT_R23 23
|
||||
#define PT_R24 24
|
||||
#define PT_R25 25
|
||||
#define PT_R26 26
|
||||
#define PT_R27 27
|
||||
#define PT_R28 28
|
||||
#define PT_R29 29
|
||||
#define PT_R30 30
|
||||
#define PT_R31 31
|
||||
|
||||
#define PT_NIP 32
|
||||
#define PT_MSR 33
|
||||
#ifdef __KERNEL__
|
||||
#define PT_ORIG_R3 34
|
||||
#endif
|
||||
#define PT_CTR 35
|
||||
#define PT_LNK 36
|
||||
#define PT_XER 37
|
||||
#define PT_CCR 38
|
||||
#define PT_MQ 39
|
||||
|
||||
#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
|
||||
#define PT_FPR31 (PT_FPR0 + 2*31)
|
||||
#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#ifndef _PPC_TYPES_H
|
||||
#define _PPC_TYPES_H
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef enum bool
|
||||
{
|
||||
FALSE = 0,
|
||||
TRUE = 1
|
||||
}BOOL;
|
||||
|
||||
typedef unsigned short umode_t;
|
||||
|
||||
typedef __signed__ char __s8;
|
||||
typedef unsigned char __u8;
|
||||
|
||||
typedef __signed__ short __s16;
|
||||
typedef unsigned short __u16;
|
||||
|
||||
typedef __signed__ int __s32;
|
||||
typedef unsigned int __u32;
|
||||
|
||||
#if defined(__GNUC__)
|
||||
__extension__ typedef __signed__ long long __s64;
|
||||
__extension__ typedef unsigned long long __u64;
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
__u32 u[4];
|
||||
} __attribute__((aligned(16))) vector128;
|
||||
|
||||
#ifdef __KERNEL__
|
||||
/*
|
||||
* These aren't exported outside the kernel to avoid name space clashes
|
||||
*/
|
||||
typedef signed char s8;
|
||||
typedef unsigned char u8;
|
||||
|
||||
typedef signed short s16;
|
||||
typedef unsigned short u16;
|
||||
|
||||
typedef signed int s32;
|
||||
typedef unsigned int u32;
|
||||
|
||||
typedef signed long long s64;
|
||||
typedef unsigned long long u64;
|
||||
|
||||
typedef char INT8;
|
||||
typedef short INT16;
|
||||
typedef int INT32;
|
||||
typedef long long INT64;
|
||||
typedef unsigned char UINT8;
|
||||
typedef unsigned short UINT16;
|
||||
typedef unsigned int UINT32;
|
||||
typedef unsigned long long UINT64;
|
||||
|
||||
#define BITS_PER_LONG 32
|
||||
|
||||
/* DMA addresses are 32-bits wide */
|
||||
typedef u32 dma_addr_t;
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
typedef unsigned long long phys_addr_t;
|
||||
typedef unsigned long long phys_size_t;
|
||||
#else
|
||||
typedef unsigned long phys_addr_t;
|
||||
typedef unsigned long phys_size_t;
|
||||
#endif
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_405EP 1 /* this is a PPC405 CPU */
|
||||
#define CONFIG_4xx 1 /* member of PPC4xx family */
|
||||
|
||||
#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
|
||||
#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */
|
||||
#define CONFIG_SYS_HZ 100
|
||||
#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ)
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
|
||||
|
||||
/*
|
||||
* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
|
||||
* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
|
||||
* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
|
||||
* The Linux BASE_BAUD define should match this configuration.
|
||||
* baseBaud = cpuClock/(uartDivisor*16)
|
||||
* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
|
||||
* set Linux BASE_BAUD to 403200.
|
||||
*/
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
#define CONFIG_UART1_CONSOLE 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFE00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x555
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2aa
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* File : interrupt.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2009, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2009-01-05 Bernard first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <asm/ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
/* interrupt nest */
|
||||
extern volatile rt_uint8_t rt_interrupt_nest;
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
#define MAX_HANDLERS 32
|
||||
rt_isr_handler_t isr_table[MAX_HANDLERS];
|
||||
|
||||
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrput_flag;
|
||||
|
||||
rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
|
||||
{
|
||||
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
|
||||
return RT_NULL;
|
||||
}
|
||||
|
||||
void uic_irq_ack(unsigned int vec)
|
||||
{
|
||||
mtdcr(uic0sr, UIC_MASK(vec));
|
||||
}
|
||||
|
||||
void uic_int_handler (unsigned int vec)
|
||||
{
|
||||
rt_interrupt_enter();
|
||||
|
||||
/* Allow external interrupts to the CPU. */
|
||||
if (isr_table [vec] != 0)
|
||||
{
|
||||
(*isr_table[vec])(vec);
|
||||
}
|
||||
uic_irq_ack(vec);
|
||||
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
/* handler for UIC interrupt */
|
||||
void uic_interrupt(rt_uint32_t uic_base, int vec_base)
|
||||
{
|
||||
int vec;
|
||||
rt_uint32_t uic_msr;
|
||||
rt_uint32_t msr_shift;
|
||||
|
||||
/*
|
||||
* Read masked interrupt status register to determine interrupt source
|
||||
*/
|
||||
uic_msr = get_dcr(uic_base + UIC_MSR);
|
||||
msr_shift = uic_msr;
|
||||
vec = vec_base;
|
||||
|
||||
while (msr_shift != 0)
|
||||
{
|
||||
if (msr_shift & 0x80000000)
|
||||
uic_int_handler(vec);
|
||||
|
||||
/*
|
||||
* Shift msr to next position and increment vector
|
||||
*/
|
||||
msr_shift <<= 1;
|
||||
vec++;
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
|
||||
{
|
||||
int intVal;
|
||||
|
||||
if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS))
|
||||
{
|
||||
return; /* out of range */
|
||||
}
|
||||
|
||||
/* install the handler in the system interrupt table */
|
||||
intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */
|
||||
|
||||
if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
|
||||
if (new_handler != RT_NULL) isr_table[vector] = new_handler;
|
||||
|
||||
rt_hw_interrupt_enable (intVal);
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector));
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_unmask(int vector)
|
||||
{
|
||||
mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector));
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_init()
|
||||
{
|
||||
int vector;
|
||||
rt_uint32_t pit_value;
|
||||
|
||||
pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ);
|
||||
|
||||
/* enable pit */
|
||||
mtspr(SPRN_PIT, pit_value);
|
||||
mtspr(SPRN_TCR, 0x4400000);
|
||||
|
||||
/* set default interrupt handler */
|
||||
for (vector = 0; vector < MAX_HANDLERS; vector++)
|
||||
{
|
||||
isr_table [vector] = (rt_isr_handler_t)rt_hw_interrupt_handle;
|
||||
}
|
||||
|
||||
/* initialize interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
rt_interrupt_from_thread = 0;
|
||||
rt_interrupt_to_thread = 0;
|
||||
rt_thread_switch_interrput_flag = 0;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
#ifndef __IO_H__
|
||||
#define __IO_H__
|
||||
|
||||
#define __iomem
|
||||
|
||||
/*
|
||||
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
|
||||
*
|
||||
* Read operations have additional twi & isync to make sure the read
|
||||
* is actually performed (i.e. the data has come back) before we start
|
||||
* executing any following instructions.
|
||||
*/
|
||||
static inline int in_8(const volatile unsigned char __iomem *addr)
|
||||
{
|
||||
int ret;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"sync; lbz%U1%X1 %0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void out_8(volatile unsigned char __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
|
||||
}
|
||||
|
||||
extern inline int in_le16(const volatile unsigned short __iomem *addr)
|
||||
{
|
||||
int ret;
|
||||
|
||||
__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) :
|
||||
"r" (addr), "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline int in_be16(const volatile unsigned short __iomem *addr)
|
||||
{
|
||||
int ret;
|
||||
|
||||
__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
|
||||
"r" (val), "r" (addr));
|
||||
}
|
||||
|
||||
extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
|
||||
}
|
||||
|
||||
extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
|
||||
{
|
||||
unsigned ret;
|
||||
|
||||
__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) :
|
||||
"r" (addr), "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
|
||||
{
|
||||
unsigned ret;
|
||||
|
||||
__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline void out_le32(volatile unsigned __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
|
||||
"r" (val), "r" (addr));
|
||||
}
|
||||
|
||||
extern inline void out_be32(volatile unsigned __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,319 @@
|
|||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "io.h"
|
||||
#include <asm/ppc4xx-intvec.h>
|
||||
|
||||
#define UART0_BASE 0xef600300
|
||||
#define UART1_BASE 0xef600400
|
||||
#define UCR0_MASK 0x0000007f
|
||||
#define UCR1_MASK 0x00007f00
|
||||
#define UCR0_UDIV_POS 0
|
||||
#define UCR1_UDIV_POS 8
|
||||
#define UDIV_MAX 127
|
||||
|
||||
#define UART_RBR 0x00
|
||||
#define UART_THR 0x00
|
||||
#define UART_IER 0x01
|
||||
#define UART_IIR 0x02
|
||||
#define UART_FCR 0x02
|
||||
#define UART_LCR 0x03
|
||||
#define UART_MCR 0x04
|
||||
#define UART_LSR 0x05
|
||||
#define UART_MSR 0x06
|
||||
#define UART_SCR 0x07
|
||||
#define UART_DLL 0x00
|
||||
#define UART_DLM 0x01
|
||||
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Line Status Register.
|
||||
+-----------------------------------------------------------------------------*/
|
||||
#define asyncLSRDataReady1 0x01
|
||||
#define asyncLSROverrunError1 0x02
|
||||
#define asyncLSRParityError1 0x04
|
||||
#define asyncLSRFramingError1 0x08
|
||||
#define asyncLSRBreakInterrupt1 0x10
|
||||
#define asyncLSRTxHoldEmpty1 0x20
|
||||
#define asyncLSRTxShiftEmpty1 0x40
|
||||
#define asyncLSRRxFifoError1 0x80
|
||||
|
||||
/* PPC405 serial device */
|
||||
struct rt_ppc405_serial
|
||||
{
|
||||
/* inherit from device */
|
||||
struct rt_device parent;
|
||||
|
||||
rt_uint32_t hw_base;
|
||||
rt_uint32_t irqno;
|
||||
rt_uint32_t baudrate;
|
||||
|
||||
/* reception field */
|
||||
rt_uint16_t save_index, read_index;
|
||||
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
||||
};
|
||||
struct rt_ppc405_serial ppc405_serial;
|
||||
|
||||
/* serial character device */
|
||||
static rt_err_t rt_serial_init (rt_device_t dev)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
|
||||
{
|
||||
struct rt_ppc405_serial* device;
|
||||
device = (struct rt_ppc405_serial*) dev;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* Enable "RX Data Available" Interrupt on UART */
|
||||
out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01);
|
||||
/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
|
||||
out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1);
|
||||
|
||||
/* init UART rx interrupt */
|
||||
rt_hw_interrupt_unmask(device->irqno);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_serial_close(rt_device_t dev)
|
||||
{
|
||||
struct rt_ppc405_serial* device;
|
||||
device = (struct rt_ppc405_serial*) dev;
|
||||
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
/* mask UART rx interrupt */
|
||||
rt_hw_interrupt_mask(device->irqno);
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_uint8_t* ptr;
|
||||
struct rt_ppc405_serial* device;
|
||||
|
||||
device = (struct rt_ppc405_serial*) dev;
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
/* point to buffer */
|
||||
ptr = (rt_uint8_t*) buffer;
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
/* interrupt receive */
|
||||
rt_base_t level;
|
||||
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
if (device->read_index != device->save_index)
|
||||
{
|
||||
*ptr = device->rx_buffer[device->read_index];
|
||||
|
||||
device->read_index ++;
|
||||
if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
device->read_index = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* no data in rx buffer */
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
break;
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
ptr ++; size --;
|
||||
}
|
||||
|
||||
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||
}
|
||||
else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
|
||||
{
|
||||
/* not support right now */
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
|
||||
/* polling mode */
|
||||
RT_ASSERT(0);
|
||||
|
||||
return (rt_size_t)ptr - (rt_size_t)buffer;
|
||||
}
|
||||
|
||||
static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
char *ptr;
|
||||
struct rt_ppc405_serial* device;
|
||||
|
||||
device = (struct rt_ppc405_serial*) dev;
|
||||
RT_ASSERT(device != RT_NULL);
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_INT_TX)
|
||||
{
|
||||
/* not support */
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
|
||||
{
|
||||
/* not support */
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
|
||||
/* polling write */
|
||||
ptr = (char *)buffer;
|
||||
|
||||
if (dev->flag & RT_DEVICE_FLAG_STREAM)
|
||||
{
|
||||
/* stream mode */
|
||||
while (size)
|
||||
{
|
||||
if (*ptr == '\n')
|
||||
{
|
||||
while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
|
||||
out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r');
|
||||
}
|
||||
|
||||
while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
|
||||
out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20);
|
||||
out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr);
|
||||
|
||||
ptr ++;
|
||||
size --;
|
||||
}
|
||||
}
|
||||
|
||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||
}
|
||||
|
||||
void rt_serial_set_baudrate(struct rt_ppc405_serial* device)
|
||||
{
|
||||
rt_uint32_t bdiv;
|
||||
|
||||
bdiv = 115200;
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
|
||||
}
|
||||
|
||||
void rt_serial_isr(int irqno)
|
||||
{
|
||||
unsigned char status;
|
||||
struct rt_ppc405_serial *device;
|
||||
|
||||
device = (struct rt_ppc405_serial*) &ppc405_serial;
|
||||
status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
|
||||
|
||||
if (status & 0x01)
|
||||
{
|
||||
rt_base_t level;
|
||||
|
||||
while (status & 0x01)
|
||||
{
|
||||
/* disable interrupt */
|
||||
level = rt_hw_interrupt_disable();
|
||||
|
||||
/* read character */
|
||||
device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base));
|
||||
device->save_index ++;
|
||||
if (device->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
device->save_index = 0;
|
||||
|
||||
/* if the next position is read index, discard this 'read char' */
|
||||
if (device->save_index == device->read_index)
|
||||
{
|
||||
device->read_index ++;
|
||||
if (device->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||
device->read_index = 0;
|
||||
}
|
||||
|
||||
/* enable interrupt */
|
||||
rt_hw_interrupt_enable(level);
|
||||
|
||||
/* check error */
|
||||
if ((status & ( asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1 )) != 0)
|
||||
{
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_LSR,
|
||||
asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1);
|
||||
}
|
||||
|
||||
status = in_8((rt_uint8_t *)device->hw_base + UART_LSR);
|
||||
}
|
||||
|
||||
/* invoke callback */
|
||||
if(device->parent.rx_indicate != RT_NULL)
|
||||
{
|
||||
device->parent.rx_indicate(&device->parent, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_serial_init(void)
|
||||
{
|
||||
volatile rt_uint8_t val;
|
||||
struct rt_ppc405_serial* device;
|
||||
|
||||
device = (struct rt_ppc405_serial*) &ppc405_serial;
|
||||
device->parent.type = RT_Device_Class_Char;
|
||||
|
||||
device->hw_base = UART0_BASE;
|
||||
device->baudrate = 115200;
|
||||
device->irqno = VECNUM_U0;
|
||||
rt_hw_interrupt_install(device->irqno, rt_serial_isr, RT_NULL); /* install isr */
|
||||
|
||||
rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer));
|
||||
device->read_index = device->save_index = 0;
|
||||
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */
|
||||
/* setup baudrate */
|
||||
rt_serial_set_baudrate(device);
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */
|
||||
val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */
|
||||
val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */
|
||||
out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
|
||||
device->parent.type = RT_Device_Class_Char;
|
||||
device->parent.init = rt_serial_init;
|
||||
device->parent.open = rt_serial_open;
|
||||
device->parent.close = rt_serial_close;
|
||||
device->parent.read = rt_serial_read;
|
||||
device->parent.write = rt_serial_write;
|
||||
device->parent.control = rt_serial_control;
|
||||
device->parent.user_data = RT_NULL;
|
||||
|
||||
rt_device_register(&device->parent,
|
||||
"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
|
||||
}
|
||||
|
|
@ -0,0 +1,564 @@
|
|||
#include <config.h>
|
||||
#include <asm/ppc_defs.h>
|
||||
|
||||
/* #include <asm/cache.h> */
|
||||
#include "cache.h"
|
||||
#include <asm/ppc4xx.h>
|
||||
|
||||
#include "context.h"
|
||||
|
||||
#define CONFIG_SYS_DCACHE_SACR_VALUE (0x00000000)
|
||||
#define CONFIG_SYS_ICACHE_SACR_VALUE \
|
||||
(PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
|
||||
PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
|
||||
PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
|
||||
|
||||
#define function_prolog(func_name) .text; \
|
||||
.align 2; \
|
||||
.globl func_name; \
|
||||
func_name:
|
||||
#define function_epilog(func_name) .type func_name,@function; \
|
||||
.size func_name,.-func_name
|
||||
|
||||
/* We don't want the MMU yet.
|
||||
*/
|
||||
#undef MSR_KERNEL
|
||||
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
|
||||
|
||||
#define SYNC \
|
||||
sync; \
|
||||
isync
|
||||
|
||||
/*
|
||||
* Macros for storing registers into and loading registers from
|
||||
* exception frames.
|
||||
*/
|
||||
#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
|
||||
#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
|
||||
#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
|
||||
#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
|
||||
#define SAVE_10GPRS(n,base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
|
||||
#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
|
||||
#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
|
||||
#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
|
||||
#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
|
||||
#define REST_10GPRS(n,base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
|
||||
|
||||
/*
|
||||
* GCC sometimes accesses words at negative offsets from the stack
|
||||
* pointer, although the SysV ABI says it shouldn't. To cope with
|
||||
* this, we leave this much untouched space on the stack on exception
|
||||
* entry.
|
||||
*/
|
||||
#define STACK_UNDERHEAD 64
|
||||
|
||||
/*
|
||||
* Exception entry code. This code runs with address translation
|
||||
* turned off, i.e. using physical addresses.
|
||||
* We assume sprg3 has the physical address of the current
|
||||
* task's thread_struct.
|
||||
*/
|
||||
/* Save:
|
||||
* CR, r0, r1 (sp), r2, r3, r4, r5, r6, r20, r21, r22, r23,
|
||||
* LR, CTR, XER, DAR, SRR0, SRR1
|
||||
*/
|
||||
#define EXCEPTION_PROLOG(reg1, reg2) \
|
||||
mtspr SPRG0,r20; \
|
||||
mtspr SPRG1,r21; \
|
||||
mfcr r20; \
|
||||
subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\
|
||||
stw r20,_CCR(r21); /* save registers */ \
|
||||
stw r22,GPR22(r21); \
|
||||
stw r23,GPR23(r21); \
|
||||
mfspr r20,SPRG0; \
|
||||
stw r20,GPR20(r21); \
|
||||
mfspr r22,SPRG1; \
|
||||
stw r22,GPR21(r21); \
|
||||
mflr r20; \
|
||||
stw r20,_LINK(r21); \
|
||||
mfctr r22; \
|
||||
stw r22,_CTR(r21); \
|
||||
mfspr r20,XER; \
|
||||
stw r20,_XER(r21); \
|
||||
mfspr r20, DAR_DEAR; \
|
||||
stw r20,_DAR(r21); \
|
||||
mfspr r22,reg1; \
|
||||
mfspr r23,reg2; \
|
||||
stw r0,GPR0(r21); \
|
||||
stw r1,GPR1(r21); \
|
||||
stw r2,GPR2(r21); \
|
||||
stw r1,0(r21);/* back chain */ \
|
||||
mr r1,r21;/* set new kernel sp */ \
|
||||
SAVE_4GPRS(3, r21);
|
||||
/*
|
||||
* Note: code which follows this uses cr0.eq (set if from kernel),
|
||||
* r21, r22 (SRR0), and r23 (SRR1).
|
||||
*/
|
||||
|
||||
/*
|
||||
* Exception vectors.
|
||||
*
|
||||
* The data words for `hdlr' and `int_return' are initialized with
|
||||
* OFFSET values only; they must be relocated first before they can
|
||||
* be used!
|
||||
*/
|
||||
#define STD_EXCEPTION(n, label, hdlr) \
|
||||
. = n; \
|
||||
label: \
|
||||
EXCEPTION_PROLOG(SRR0, SRR1); \
|
||||
lwz r3,GOT(transfer_to_handler); \
|
||||
mtlr r3; \
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
li r20,MSR_KERNEL; \
|
||||
rlwimi r20,r23,0,25,25; \
|
||||
blrl; \
|
||||
.L_ ## label : \
|
||||
.long hdlr - _start + _START_OFFSET; \
|
||||
.long int_return - _start + _START_OFFSET
|
||||
|
||||
#define CRIT_EXCEPTION(n, label, hdlr) \
|
||||
. = n; \
|
||||
label: \
|
||||
EXCEPTION_PROLOG(CSRR0, CSRR1); \
|
||||
lwz r3,GOT(transfer_to_handler); \
|
||||
mtlr r3; \
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
|
||||
rlwimi r20,r23,0,25,25; \
|
||||
blrl; \
|
||||
.L_ ## label : \
|
||||
.long hdlr - _start + _START_OFFSET; \
|
||||
.long crit_return - _start + _START_OFFSET
|
||||
|
||||
#define MCK_EXCEPTION(n, label, hdlr) \
|
||||
. = n; \
|
||||
label: \
|
||||
EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
|
||||
lwz r3,GOT(transfer_to_handler); \
|
||||
mtlr r3; \
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD; \
|
||||
li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
|
||||
rlwimi r20,r23,0,25,25; \
|
||||
blrl; \
|
||||
.L_ ## label : \
|
||||
.long hdlr - _start + _START_OFFSET; \
|
||||
.long mck_return - _start + _START_OFFSET
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
*
|
||||
* These definitions simplify the ugly declarations necessary for GOT
|
||||
* definitions.
|
||||
*
|
||||
* Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es
|
||||
*
|
||||
* Uses r14 to access the GOT
|
||||
*/
|
||||
|
||||
#define START_GOT \
|
||||
.section ".got2","aw"; \
|
||||
.LCTOC1 = .+32768
|
||||
|
||||
#define END_GOT \
|
||||
.text
|
||||
|
||||
#define GET_GOT \
|
||||
bl 1f ; \
|
||||
.text 2 ; \
|
||||
0: .long .LCTOC1-1f ; \
|
||||
.text ; \
|
||||
1: mflr r14 ; \
|
||||
lwz r0,0b-1b(r14) ; \
|
||||
add r14,r0,r14 ;
|
||||
|
||||
#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME
|
||||
|
||||
#define GOT(NAME) .L_ ## NAME (r14)
|
||||
|
||||
/*
|
||||
* Set up GOT: Global Offset Table
|
||||
*
|
||||
* Use r14 to access the GOT
|
||||
*/
|
||||
START_GOT
|
||||
GOT_ENTRY(_GOT2_TABLE_)
|
||||
GOT_ENTRY(_FIXUP_TABLE_)
|
||||
|
||||
GOT_ENTRY(_start)
|
||||
GOT_ENTRY(_start_of_vectors)
|
||||
GOT_ENTRY(_end_of_vectors)
|
||||
GOT_ENTRY(transfer_to_handler)
|
||||
|
||||
GOT_ENTRY(__init_end)
|
||||
GOT_ENTRY(_end)
|
||||
GOT_ENTRY(__bss_start)
|
||||
END_GOT
|
||||
|
||||
/*
|
||||
* r3 - 1st arg to board_init(): IMMP pointer
|
||||
* r4 - 2nd arg to board_init(): boot flag
|
||||
*/
|
||||
.text
|
||||
version_string:
|
||||
.ascii "RT-Thread 0.4.0"
|
||||
|
||||
. = EXC_OFF_SYS_RESET
|
||||
_start_of_vectors:
|
||||
|
||||
/* Critical input. */
|
||||
CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
|
||||
CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
|
||||
/* Data Storage exception. */
|
||||
STD_EXCEPTION(0x300, DataStorage, UnknownException)
|
||||
/* Instruction Storage exception. */
|
||||
STD_EXCEPTION(0x400, InstStorage, UnknownException)
|
||||
|
||||
. = 0x0500
|
||||
ExtInterrupt:
|
||||
/* save current thread stack */
|
||||
subi r1, r1, STACK_FRAME_SIZE
|
||||
|
||||
/* save registers */
|
||||
stw r0,GPR0(r1) /* save general purpose registers 0 */
|
||||
stmw r2,GPR2(r1) /* save general purpose registers 2-31 */
|
||||
|
||||
mfusprg0 r0 /* save usprg0 */
|
||||
stw r0,USPRG0(r1)
|
||||
mfcr r0, /* save cr */
|
||||
stw r0,CR(r1)
|
||||
mfxer r0 /* save xer */
|
||||
stw r0,XER(r1)
|
||||
mfctr r0 /* save ctr */
|
||||
stw r0,CTR(r1)
|
||||
mflr r0 /* save lr */
|
||||
stw r0, LR(r1)
|
||||
|
||||
mfsrr0 r0 /* save SRR0 and SRR1 */
|
||||
stw r0,SRR0(r1)
|
||||
mfsrr1 r0
|
||||
stw r0,SRR1(r1)
|
||||
|
||||
bl rt_interrupt_enter
|
||||
bl external_interrupt
|
||||
bl rt_interrupt_leave
|
||||
|
||||
/* restore thread context */
|
||||
lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */
|
||||
mtsrr1 r0
|
||||
lwz r0,SRR0(r1)
|
||||
mtsrr0 r0
|
||||
|
||||
lwz r0,LR(r1) /* restore lr */
|
||||
mtlr r0
|
||||
lwz r0,CTR(r1) /* restore ctr */
|
||||
mtctr r0
|
||||
lwz r0,XER(r1) /* restore xer */
|
||||
mtxer r0
|
||||
lwz r0,CR(r1) /* restore cr */
|
||||
mtcr r0
|
||||
lwz r0,USPRG0(r1) /* restore usprg0 */
|
||||
// mtusprg0 r0
|
||||
|
||||
lmw r2, GPR2(r1) /* restore general register */
|
||||
lwz r0,GPR0(r1)
|
||||
addi r1, r1, STACK_FRAME_SIZE
|
||||
b rt_hw_systemcall_entry
|
||||
|
||||
/* Alignment exception. */
|
||||
. = 0x600
|
||||
Alignment:
|
||||
EXCEPTION_PROLOG(SRR0, SRR1)
|
||||
mfspr r4,DAR
|
||||
stw r4,_DAR(r21)
|
||||
mfspr r5,DSISR
|
||||
stw r5,_DSISR(r21)
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
li r20,MSR_KERNEL
|
||||
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
|
||||
lwz r6,GOT(transfer_to_handler)
|
||||
mtlr r6
|
||||
blrl
|
||||
.L_Alignment:
|
||||
.long AlignmentException - _start + _START_OFFSET
|
||||
.long int_return - _start + _START_OFFSET
|
||||
|
||||
/* Program check exception */
|
||||
. = 0x700
|
||||
ProgramCheck:
|
||||
EXCEPTION_PROLOG(SRR0, SRR1)
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
li r20,MSR_KERNEL
|
||||
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
|
||||
lwz r6,GOT(transfer_to_handler)
|
||||
mtlr r6
|
||||
blrl
|
||||
.L_ProgramCheck:
|
||||
.long ProgramCheckException - _start + _START_OFFSET
|
||||
.long int_return - _start + _START_OFFSET
|
||||
|
||||
. = 0x0c00
|
||||
SystemCall:
|
||||
b rt_hw_systemcall_entry
|
||||
|
||||
. = 0x1000
|
||||
PIT:
|
||||
/* save current thread stack */
|
||||
subi r1, r1, STACK_FRAME_SIZE
|
||||
|
||||
/* save registers */
|
||||
stw r0,GPR0(r1) /* save general purpose registers 0 */
|
||||
stmw r2,GPR2(r1) /* save general purpose registers 2-31 */
|
||||
|
||||
mfusprg0 r0 /* save usprg0 */
|
||||
stw r0,USPRG0(r1)
|
||||
mfcr r0, /* save cr */
|
||||
stw r0,CR(r1)
|
||||
mfxer r0 /* save xer */
|
||||
stw r0,XER(r1)
|
||||
mfctr r0 /* save ctr */
|
||||
stw r0,CTR(r1)
|
||||
mflr r0 /* save lr */
|
||||
stw r0, LR(r1)
|
||||
|
||||
mfsrr0 r0 /* save SRR0 and SRR1 */
|
||||
stw r0,SRR0(r1)
|
||||
mfsrr1 r0
|
||||
stw r0,SRR1(r1)
|
||||
|
||||
bl rt_interrupt_enter
|
||||
bl DecrementerPITException
|
||||
bl rt_interrupt_leave
|
||||
|
||||
/* restore thread context */
|
||||
lwz r0,SRR1(r1) /* restore SRR1 and SRR0 */
|
||||
mtsrr1 r0
|
||||
lwz r0,SRR0(r1)
|
||||
mtsrr0 r0
|
||||
|
||||
lwz r0,LR(r1) /* restore lr */
|
||||
mtlr r0
|
||||
lwz r0,CTR(r1) /* restore ctr */
|
||||
mtctr r0
|
||||
lwz r0,XER(r1) /* restore xer */
|
||||
mtxer r0
|
||||
lwz r0,CR(r1) /* restore cr */
|
||||
mtcr r0
|
||||
lwz r0,USPRG0(r1) /* restore usprg0 */
|
||||
// mtusprg0 r0
|
||||
|
||||
lmw r2, GPR2(r1) /* restore general register */
|
||||
lwz r0,GPR0(r1)
|
||||
addi r1, r1, STACK_FRAME_SIZE
|
||||
b rt_hw_systemcall_entry
|
||||
|
||||
STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
|
||||
STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
|
||||
|
||||
CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
|
||||
|
||||
_end_of_vectors:
|
||||
. = _START_OFFSET
|
||||
|
||||
/*
|
||||
* start and end addresses of the BSS section
|
||||
* they are taken from the linker script
|
||||
*/
|
||||
|
||||
.set START_BSS, __bss_start
|
||||
.set END_BSS, __bss_end
|
||||
|
||||
/* stack top address exported from linker script */
|
||||
.set STACK_TOP, __stack_top
|
||||
|
||||
_start:
|
||||
/*----------------------------------------------------------------------- */
|
||||
/* Clear and set up some registers. */
|
||||
/*----------------------------------------------------------------------- */
|
||||
addi r4,r0,0x0000
|
||||
mtsgr r4 /* Configure guarded attribute for performance. */
|
||||
mtsler r4 /* Configure endinanness */
|
||||
mtsu0r r4 /* and compression. */
|
||||
|
||||
/*------------------------------------------------------------------------
|
||||
* Initialize vector tables and other registers
|
||||
* set them all to 0. The Interrupt Handler implementation
|
||||
* has to set these registers later on
|
||||
*-----------------------------------------------------------------------*/
|
||||
mtdcwr r4
|
||||
mtesr r4 /* clear Exception Syndrome Reg */
|
||||
mttcr r4 /* clear Timer Control Reg */
|
||||
mtxer r4 /* clear Fixed-Point Exception Reg */
|
||||
mtevpr r4 /* clear Exception Vector Prefix Reg */
|
||||
|
||||
addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
|
||||
/* dbsr is cleared by setting bits to 1) */
|
||||
mtdbsr r4 /* clear/reset the dbsr */
|
||||
|
||||
/* Invalidate the i- and d-caches. */
|
||||
bl invalidate_icache
|
||||
bl invalidate_dcache
|
||||
|
||||
/* Set-up icache cacheability. */
|
||||
lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
|
||||
ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
|
||||
mticcr r4
|
||||
isync
|
||||
|
||||
/* Set-up dcache cacheability. */
|
||||
lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
|
||||
ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
|
||||
mtdccr r4
|
||||
|
||||
/*----------------------------------------------------------------------- */
|
||||
/* DMA Status, clear to come up clean */
|
||||
/*----------------------------------------------------------------------- */
|
||||
addis r3,r0, 0xFFFF /* Clear all existing DMA status */
|
||||
ori r3,r3, 0xFFFF
|
||||
mtdcr dmasr, r3
|
||||
|
||||
/* clear the BSS section */
|
||||
lis r3,START_BSS@h // load start of BSS into r3
|
||||
ori r3,r3,START_BSS@l
|
||||
lis r4,END_BSS@h // load end of BSS into r4
|
||||
ori r4,r4,END_BSS@l
|
||||
sub r4,r4,r3 // calculate length of BSS
|
||||
srwi r4,r4,2 // convert byte-length to word-length
|
||||
li r5,0 // zero r5
|
||||
cmplw 0,r4,r5 // check to see whether length equals 0
|
||||
beql 0,2f // in case of length 0 we're already done
|
||||
subi r3,r3,4 // because of offset start 4 bytes lower
|
||||
mtctr r4 // use word-length of BSS section as counter
|
||||
1: /* bss clear start */
|
||||
stwu r5,4(r3) // zero one word of BSS section
|
||||
bdnz 1b // keep going until BSS is entirely clean
|
||||
2: /* bss clear done */
|
||||
|
||||
/* Set up stack in the linker script defined RAM area */
|
||||
lis r1, STACK_TOP@h
|
||||
ori r1, r1, STACK_TOP@l
|
||||
|
||||
/* Set up a zeroized stack frame so that backtrace works right */
|
||||
li r0, 0
|
||||
stwu r0, -4(r1)
|
||||
stwu r0, -4(r1)
|
||||
|
||||
/*
|
||||
* Set up a dummy frame to store reset vector as return address.
|
||||
* this causes stack underflow to reset board.
|
||||
*/
|
||||
stwu r1, -8(r1) /* Save back chain and move SP */
|
||||
lis r0, RESET_VECTOR@h /* Address of reset vector */
|
||||
ori r0, r0, RESET_VECTOR@l
|
||||
stwu r1, -8(r1) /* Save back chain and move SP */
|
||||
stw r0, +12(r1) /* Save return addr (underflow vect) */
|
||||
|
||||
GET_GOT /* initialize GOT access */
|
||||
|
||||
/* NEVER RETURNS! */
|
||||
bl rtthread_startup
|
||||
|
||||
/*
|
||||
* Note: code which follows this uses cr0.eq (set if from kernel),
|
||||
* r20(new MSR), r21(trap frame), r22 (SRR0), and r23 (SRR1).
|
||||
*/
|
||||
|
||||
/*
|
||||
* This code finishes saving the registers to the exception frame
|
||||
* and jumps to the appropriate handler for the exception.
|
||||
* Register r21 is pointer into trap frame, r1 has new stack pointer.
|
||||
*/
|
||||
transfer_to_handler:
|
||||
stw r22,_NIP(r21)
|
||||
lis r22,MSR_POW@h /* clear POW bit */
|
||||
andc r23,r23,r22 /* use normal power management */
|
||||
stw r23,_MSR(r21) /* MSC value when the exception returns */
|
||||
SAVE_GPR(7, r21)
|
||||
SAVE_4GPRS(8, r21)
|
||||
SAVE_8GPRS(12, r21)
|
||||
SAVE_8GPRS(24, r21)
|
||||
mflr r23 /* hdlr/int_return addr immediately follows */
|
||||
andi. r24,r23,0x3f00 /* get vector offset */
|
||||
stw r24,TRAP(r21) /* vector address, such as 0x1000 for PIT */
|
||||
li r22,0
|
||||
stw r22,RESULT(r21) /* clear the sc return value */
|
||||
mtspr SPRG2,r22 /* r1 is now kernel sp */
|
||||
lwz r24,0(r23) /* virtual address of hdlr */
|
||||
lwz r23,4(r23) /* where to go when done */
|
||||
mtspr SRR0,r24 /* hdlr */
|
||||
mtspr SRR1,r20 /* MSR_KERNEL with ME enabled */
|
||||
mtlr r23 /* call hdlr and then return to int_return */
|
||||
SYNC /* note r3 has address for pt_regs on stack */
|
||||
rfi /* jump to handler, enable ME */
|
||||
|
||||
int_return:
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
lwz r4,_MQ(r1)
|
||||
cmpwi r4, 0
|
||||
beq goon_return
|
||||
switch_stack:
|
||||
subi r1,r4,STACK_FRAME_OVERHEAD
|
||||
goon_return:
|
||||
mfmsr r28 /* Disable interrupts */
|
||||
li r4,0
|
||||
ori r4,r4,MSR_EE /* clear External Interrupt Enable */
|
||||
ori r4,r4,MSR_DE /* clear Debug Interrupts Enable - 4xx */
|
||||
andc r28,r28,r4
|
||||
SYNC /* Some chip revs need this... */
|
||||
mtmsr r28
|
||||
SYNC
|
||||
lwz r2,_CTR(r1)
|
||||
lwz r0,_LINK(r1)
|
||||
mtctr r2
|
||||
mtlr r0
|
||||
lwz r2,_XER(r1)
|
||||
lwz r0,_CCR(r1)
|
||||
mtspr XER,r2
|
||||
mtcrf 0xFF,r0
|
||||
REST_10GPRS(3, r1)
|
||||
REST_10GPRS(13, r1)
|
||||
REST_8GPRS(23, r1)
|
||||
REST_GPR(31, r1)
|
||||
lwz r2,_NIP(r1) /* Restore environment */
|
||||
lwz r0,_MSR(r1)
|
||||
mtspr SRR0,r2
|
||||
mtspr SRR1,r0
|
||||
lwz r0,GPR0(r1)
|
||||
lwz r2,GPR2(r1)
|
||||
lwz r1,GPR1(r1)
|
||||
SYNC
|
||||
rfi
|
||||
b . /* prevent prefetch past rfi */
|
||||
|
||||
crit_return:
|
||||
mfmsr r28 /* Disable interrupts */
|
||||
li r4,0
|
||||
ori r4,r4,MSR_EE
|
||||
andc r28,r28,r4
|
||||
SYNC /* Some chip revs need this... */
|
||||
mtmsr r28
|
||||
SYNC
|
||||
lwz r2,_CTR(r1)
|
||||
lwz r0,_LINK(r1)
|
||||
mtctr r2
|
||||
mtlr r0
|
||||
lwz r2,_XER(r1)
|
||||
lwz r0,_CCR(r1)
|
||||
mtspr XER,r2
|
||||
mtcrf 0xFF,r0
|
||||
REST_10GPRS(3, r1)
|
||||
REST_10GPRS(13, r1)
|
||||
REST_8GPRS(23, r1)
|
||||
REST_GPR(31, r1)
|
||||
lwz r2,_NIP(r1) /* Restore environment */
|
||||
lwz r0,_MSR(r1)
|
||||
mtspr SPRN_CSRR0,r2
|
||||
mtspr SPRN_CSRR1,r0
|
||||
lwz r0,GPR0(r1)
|
||||
lwz r2,GPR2(r1)
|
||||
lwz r1,GPR1(r1)
|
||||
SYNC
|
||||
rfci
|
||||
|
||||
get_pvr:
|
||||
mfspr r3, PVR
|
||||
blr
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
#include <rtthread.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/ppc4xx-uic.h>
|
||||
|
||||
/* Returns 0 if exception not found and fixup otherwise. */
|
||||
extern unsigned long search_exception_table(unsigned long);
|
||||
|
||||
/* THIS NEEDS CHANGING to use the board info structure.
|
||||
*/
|
||||
#define END_OF_MEM 0x800000
|
||||
#define UICB0_ALL 0
|
||||
|
||||
#define ESR_MCI 0x80000000
|
||||
#define ESR_PIL 0x08000000
|
||||
#define ESR_PPR 0x04000000
|
||||
#define ESR_PTR 0x02000000
|
||||
#define ESR_DST 0x00800000
|
||||
#define ESR_DIZ 0x00400000
|
||||
#define ESR_U0F 0x00008000
|
||||
|
||||
rt_inline void set_tsr(unsigned long val)
|
||||
{
|
||||
mtspr(SPRN_TSR, val);
|
||||
}
|
||||
|
||||
rt_inline rt_uint32_t get_esr(void)
|
||||
{
|
||||
rt_uint32_t val;
|
||||
|
||||
val = mfspr(SPRN_ESR);
|
||||
return val;
|
||||
}
|
||||
|
||||
/*
|
||||
* Trap & Exception support
|
||||
*/
|
||||
|
||||
void print_backtrace(unsigned long *sp)
|
||||
{
|
||||
int cnt = 0;
|
||||
unsigned long i;
|
||||
|
||||
rt_kprintf("Call backtrace: ");
|
||||
while (sp) {
|
||||
if ((rt_uint32_t)sp > END_OF_MEM)
|
||||
break;
|
||||
|
||||
i = sp[1];
|
||||
if (cnt++ % 7 == 0)
|
||||
rt_kprintf("\n");
|
||||
rt_kprintf("%08lX ", i);
|
||||
if (cnt > 32) break;
|
||||
sp = (unsigned long *)*sp;
|
||||
}
|
||||
rt_kprintf("\n");
|
||||
}
|
||||
|
||||
void show_regs(struct pt_regs * regs)
|
||||
{
|
||||
int i;
|
||||
|
||||
rt_kprintf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
|
||||
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
|
||||
rt_kprintf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
|
||||
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
|
||||
regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
|
||||
regs->msr&MSR_IR ? 1 : 0,
|
||||
regs->msr&MSR_DR ? 1 : 0);
|
||||
|
||||
rt_kprintf("\n");
|
||||
for (i = 0; i < 32; i++) {
|
||||
if ((i % 8) == 0) {
|
||||
rt_kprintf("GPR%02d: ", i);
|
||||
}
|
||||
|
||||
rt_kprintf("%08lX ", regs->gpr[i]);
|
||||
if ((i % 8) == 7) {
|
||||
rt_kprintf("\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void panic(const char *fmt, ...)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
void
|
||||
_exception(int signr, struct pt_regs *regs)
|
||||
{
|
||||
show_regs(regs);
|
||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
||||
panic("Exception");
|
||||
}
|
||||
|
||||
unsigned long
|
||||
search_exception_table(unsigned long addr)
|
||||
{
|
||||
unsigned long ret = 0;
|
||||
|
||||
/* There is only the kernel to search. */
|
||||
// ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr);
|
||||
/* if the serial port does not hang in exception, rt_kprintf can be used */
|
||||
if (ret) return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handle external interrupts
|
||||
*/
|
||||
void external_interrupt(struct pt_regs *regs)
|
||||
{
|
||||
u32 uic_msr;
|
||||
|
||||
/*
|
||||
* Read masked interrupt status register to determine interrupt source
|
||||
*/
|
||||
uic_msr = mfdcr(uic0msr);
|
||||
|
||||
mtdcr(uic0sr, (uic_msr & UICB0_ALL));
|
||||
|
||||
if (uic_msr & ~(UICB0_ALL))
|
||||
{
|
||||
uic_interrupt(UIC0_DCR_BASE, 0);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void MachineCheckException(struct pt_regs *regs)
|
||||
{
|
||||
unsigned long fixup, val;
|
||||
|
||||
if ((fixup = search_exception_table(regs->nip)) != 0) {
|
||||
regs->nip = fixup;
|
||||
val = mfspr(MCSR);
|
||||
/* Clear MCSR */
|
||||
mtspr(SPRN_MCSR, val);
|
||||
return;
|
||||
}
|
||||
|
||||
rt_kprintf("Machine Check Exception.\n");
|
||||
rt_kprintf("Caused by (from msr): ");
|
||||
rt_kprintf("regs %p ", regs);
|
||||
|
||||
val = get_esr();
|
||||
|
||||
if (val& ESR_IMCP) {
|
||||
rt_kprintf("Instruction");
|
||||
mtspr(ESR, val & ~ESR_IMCP);
|
||||
} else {
|
||||
rt_kprintf("Data");
|
||||
}
|
||||
rt_kprintf(" machine check.\n");
|
||||
|
||||
show_regs(regs);
|
||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
||||
panic("machine check");
|
||||
}
|
||||
|
||||
void AlignmentException(struct pt_regs *regs)
|
||||
{
|
||||
show_regs(regs);
|
||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
||||
panic("Alignment Exception");
|
||||
}
|
||||
|
||||
void ProgramCheckException(struct pt_regs *regs)
|
||||
{
|
||||
long esr_val;
|
||||
|
||||
show_regs(regs);
|
||||
|
||||
esr_val = get_esr();
|
||||
if( esr_val & ESR_PIL )
|
||||
rt_kprintf( "** Illegal Instruction **\n" );
|
||||
else if( esr_val & ESR_PPR )
|
||||
rt_kprintf( "** Privileged Instruction **\n" );
|
||||
else if( esr_val & ESR_PTR )
|
||||
rt_kprintf( "** Trap Instruction **\n" );
|
||||
|
||||
print_backtrace((unsigned long *)regs->gpr[1]);
|
||||
panic("Program Check Exception");
|
||||
}
|
||||
|
||||
void DecrementerPITException(struct pt_regs *regs)
|
||||
{
|
||||
/* reset PIT interrupt */
|
||||
set_tsr(0x08000000);
|
||||
|
||||
/* increase a OS Tick */
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
void UnknownException(struct pt_regs *regs)
|
||||
{
|
||||
|
||||
rt_kprintf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
|
||||
regs->nip, regs->msr, regs->trap);
|
||||
_exception(0, regs);
|
||||
}
|
||||
|
||||
void DebugException(struct pt_regs *regs)
|
||||
{
|
||||
rt_kprintf("Debugger trap at @ %lx @regs %lx\n", regs->nip, (rt_uint32_t)regs );
|
||||
show_regs(regs);
|
||||
}
|
||||
Loading…
Reference in New Issue