Merge pull request #921 from TanekLiang/imx_rt
[bsp] fix gcc build error and add missing file in i.MX RT.
This commit is contained in:
Bernard Xiong
GitHub
commit
0c04810a18
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@ -10,23 +10,16 @@ SrcRemove(src, 'drivers/dataqueue.c')
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src += Glob('common/chip/*.c')
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src += Glob('common/chip/*.c')
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src += [cwd + '/system_MIMXRT1052.c']
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src += [cwd + '/system_MIMXRT1052.c']
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CPPPATH = [ cwd, cwd + '/drivers', cwd + '/utilities', cwd + '/CMSIS/include']
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CPPPATH = [ cwd, cwd + '/drivers', cwd + '/utilities', cwd + '/CMSIS/Include']
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CPPDEFINES = ['CPU_MIMXRT1052DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1']
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CPPDEFINES = ['CPU_MIMXRT1052DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1']
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# CPPDEFINES = ['CPU_MIMXRT1052DVL6A', 'EVK_MCIMXRM']
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# add for startup script
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# add for startup script
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if rtconfig.CROSS_TOOL == 'gcc':
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if rtconfig.CROSS_TOOL == 'gcc':
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src += [cwd + '/gcc/startup_MIMXRT1052.s']
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src += [cwd + '/gcc/startup_MIMXRT1052.S']
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elif rtconfig.CROSS_TOOL == 'keil':
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elif rtconfig.CROSS_TOOL == 'keil':
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src += [cwd + '/arm/startup_MIMXRT1052.s']
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src += [cwd + '/arm/startup_MIMXRT1052.s']
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elif rtconfig.CROSS_TOOL == 'iar':
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elif rtconfig.CROSS_TOOL == 'iar':
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src += [cwd + '/iar/startup_MIMXRT1052.s']
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src += [cwd + '/iar/startup_MIMXRT1052.s']
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# if GetDepend('RT_USING_IMX_MID_SDMMC'):
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# src += Glob('middleware/sdmmc/src/*.c')
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# CPPPATH += [cwd + '/middleware/sdmmc/inc']
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# CPPPATH += [cwd + '/middleware/sdmmc/port']
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# CPPPATH += [cwd + '/middleware/sdmmc/port/usdhc/polling']
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group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
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group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
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@ -0,0 +1,846 @@
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/*
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* File : application.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2017-06-08 tanek first implementation
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*/
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#include <rtthread.h>
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#include "board.h"
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#include <rtdevice.h>
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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#endif
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#include "fsl_enet.h"
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#include "fsl_gpio.h"
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#include "fsl_iomuxc.h"
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#include "fsl_phy.h"
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#ifdef RT_USING_LWIP
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#include <netif/ethernetif.h>
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#include "lwipopts.h"
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#define ENET_RXBD_NUM (4)
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#define ENET_TXBD_NUM (4)
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#define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
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#define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
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#define PHY_ADDRESS 0x02u
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/* debug option */
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//#define DEBUG
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//#define ETH_RX_DUMP
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//#define ETH_TX_DUMP
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#ifdef DEBUG
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#define ETH_PRINTF rt_kprintf
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#else
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#define ETH_PRINTF(...)
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#endif
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#define MAX_ADDR_LEN 6
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struct rt_imxrt_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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enet_handle_t enet_handle;
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ENET_Type *enet_base;
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enet_data_error_stats_t error_statistic;
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rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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rt_bool_t tx_is_waiting;
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struct rt_semaphore tx_wait;
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};
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ALIGN(ENET_BUFF_ALIGNMENT) enet_tx_bd_struct_t g_txBuffDescrip[ENET_TXBD_NUM] SECTION("NonCacheable");
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ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_txDataBuff[ENET_TXBD_NUM][RT_ALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT)];
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ALIGN(ENET_BUFF_ALIGNMENT) enet_rx_bd_struct_t g_rxBuffDescrip[ENET_RXBD_NUM] SECTION("NonCacheable");
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ALIGN(ENET_BUFF_ALIGNMENT) rt_uint8_t g_rxDataBuff[ENET_RXBD_NUM][RT_ALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT)];
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static struct rt_imxrt_eth imxrt_eth_device;
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void _enet_rx_callback(struct rt_imxrt_eth * eth)
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{
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rt_err_t result;
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ENET_DisableInterrupts(eth->enet_base, kENET_RxFrameInterrupt);
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result = eth_device_ready(&(eth->parent));
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if( result != RT_EOK )
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rt_kprintf("RX err =%d\n", result );
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}
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void _enet_tx_callback(struct rt_imxrt_eth * eth)
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{
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if (eth->tx_is_waiting == RT_TRUE)
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{
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eth->tx_is_waiting = RT_FALSE;
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rt_sem_release(ð->tx_wait);
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}
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}
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void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event, void *userData)
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{
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switch(event)
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{
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case kENET_RxEvent:
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_enet_rx_callback((struct rt_imxrt_eth *)userData);
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break;
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case kENET_TxEvent:
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_enet_tx_callback((struct rt_imxrt_eth *)userData);
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break;
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case kENET_ErrEvent:
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//rt_kprintf("kENET_ErrEvent\n");
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break;
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case kENET_WakeUpEvent:
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//rt_kprintf("kENET_WakeUpEvent\n");
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break;
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case kENET_TimeStampEvent:
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//rt_kprintf("kENET_TimeStampEvent\n");
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break;
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case kENET_TimeStampAvailEvent:
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//rt_kprintf("kENET_TimeStampAvailEvent \n");
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break;
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default:
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//rt_kprintf("unknow error\n");
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break;
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}
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}
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static void _enet_io_init(void)
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{
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CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
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1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinMux(
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IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
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0U); /* Software Input On Field: Input Path is determined by functionality */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
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0xB0A9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
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0xB0A9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
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0x10B0u); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: R0/6
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Keeper
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
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0x10B0u); /* Slew Rate Field: Slow Slew Rate
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Drive Strength Field: R0/6
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Speed Field: medium(100MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Keeper
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
|
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
|
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
|
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Drive Strength Field: R0/5
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Speed Field: max(200MHz)
|
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|
Open Drain Enable Field: Open Drain Disabled
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Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||||
|
Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
|
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
|
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|
Drive Strength Field: R0/5
|
||||||
|
Speed Field: max(200MHz)
|
||||||
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Open Drain Enable Field: Open Drain Disabled
|
||||||
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Pull / Keep Enable Field: Pull/Keeper Enabled
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||||||
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Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
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0xB0E9u); /* Slew Rate Field: Fast Slew Rate
|
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Drive Strength Field: R0/5
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||||||
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Speed Field: max(200MHz)
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Open Drain Enable Field: Open Drain Disabled
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||||||
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Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||||
|
Pull / Keep Select Field: Pull
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Pull Up / Down Config. Field: 100K Ohm Pull Up
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Hyst. Enable Field: Hysteresis Disabled */
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IOMUXC_SetPinConfig(
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IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
|
||||||
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0x31u); /* Slew Rate Field: Fast Slew Rate
|
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Drive Strength Field: R0/6
|
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Speed Field: low(50MHz)
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Open Drain Enable Field: Open Drain Disabled
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||||||
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Pull / Keep Enable Field: Pull/Keeper Disabled
|
||||||
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Pull / Keep Select Field: Keeper
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||||||
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Pull Up / Down Config. Field: 100K Ohm Pull Down
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||||||
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Hyst. Enable Field: Hysteresis Disabled */
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||||||
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IOMUXC_SetPinConfig(
|
||||||
|
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
|
||||||
|
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
|
||||||
|
Drive Strength Field: R0/5
|
||||||
|
Speed Field: max(200MHz)
|
||||||
|
Open Drain Enable Field: Open Drain Disabled
|
||||||
|
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||||
|
Pull / Keep Select Field: Pull
|
||||||
|
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||||
|
Hyst. Enable Field: Hysteresis Disabled */
|
||||||
|
IOMUXC_SetPinConfig(
|
||||||
|
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
|
||||||
|
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
|
||||||
|
Drive Strength Field: R0/5
|
||||||
|
Speed Field: max(200MHz)
|
||||||
|
Open Drain Enable Field: Open Drain Disabled
|
||||||
|
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||||
|
Pull / Keep Select Field: Pull
|
||||||
|
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||||
|
Hyst. Enable Field: Hysteresis Disabled */
|
||||||
|
IOMUXC_SetPinConfig(
|
||||||
|
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
|
||||||
|
0xB829u); /* Slew Rate Field: Fast Slew Rate
|
||||||
|
Drive Strength Field: R0/5
|
||||||
|
Speed Field: low(50MHz)
|
||||||
|
Open Drain Enable Field: Open Drain Enabled
|
||||||
|
Pull / Keep Enable Field: Pull/Keeper Enabled
|
||||||
|
Pull / Keep Select Field: Pull
|
||||||
|
Pull Up / Down Config. Field: 100K Ohm Pull Up
|
||||||
|
Hyst. Enable Field: Hysteresis Disabled */
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _enet_clk_init(void)
|
||||||
|
{
|
||||||
|
const clock_enet_pll_config_t config = {true, false, false, 1, 1};
|
||||||
|
CLOCK_InitEnetPll(&config);
|
||||||
|
|
||||||
|
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _delay(void)
|
||||||
|
{
|
||||||
|
volatile int i = 1000000;
|
||||||
|
|
||||||
|
while (i--)
|
||||||
|
i = i;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _enet_phy_reset_by_gpio(void)
|
||||||
|
{
|
||||||
|
gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
|
||||||
|
|
||||||
|
GPIO_PinInit(GPIO1, 9, &gpio_config);
|
||||||
|
GPIO_PinInit(GPIO1, 10, &gpio_config);
|
||||||
|
/* pull up the ENET_INT before RESET. */
|
||||||
|
GPIO_WritePinOutput(GPIO1, 10, 1);
|
||||||
|
GPIO_WritePinOutput(GPIO1, 9, 0);
|
||||||
|
_delay();
|
||||||
|
GPIO_WritePinOutput(GPIO1, 9, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void _enet_config(void)
|
||||||
|
{
|
||||||
|
enet_config_t config;
|
||||||
|
uint32_t sysClock;
|
||||||
|
status_t status;
|
||||||
|
phy_speed_t speed;
|
||||||
|
phy_duplex_t duplex;
|
||||||
|
bool link = false;
|
||||||
|
|
||||||
|
/* prepare the buffer configuration. */
|
||||||
|
enet_buffer_config_t buffConfig = {
|
||||||
|
ENET_RXBD_NUM,
|
||||||
|
ENET_TXBD_NUM,
|
||||||
|
SDK_SIZEALIGN(ENET_RXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
|
||||||
|
SDK_SIZEALIGN(ENET_TXBUFF_SIZE, ENET_BUFF_ALIGNMENT),
|
||||||
|
&g_rxBuffDescrip[0],
|
||||||
|
&g_txBuffDescrip[0],
|
||||||
|
&g_rxDataBuff[0][0],
|
||||||
|
&g_txDataBuff[0][0],
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Get default configuration. */
|
||||||
|
/*
|
||||||
|
* config.miiMode = kENET_RmiiMode;
|
||||||
|
* config.miiSpeed = kENET_MiiSpeed100M;
|
||||||
|
* config.miiDuplex = kENET_MiiFullDuplex;
|
||||||
|
* config.rxMaxFrameLen = ENET_FRAME_MAX_FRAMELEN;
|
||||||
|
*/
|
||||||
|
ENET_GetDefaultConfig(&config);
|
||||||
|
config.interrupt = kENET_TxFrameInterrupt | kENET_RxFrameInterrupt;
|
||||||
|
//config.interrupt = 0xFFFFFFFF;
|
||||||
|
|
||||||
|
/* Set SMI to get PHY link status. */
|
||||||
|
sysClock = CLOCK_GetFreq(kCLOCK_AhbClk);
|
||||||
|
status = PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, sysClock);
|
||||||
|
while (status != kStatus_Success)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("\r\nPHY Auto-negotiation failed. Please check the cable connection and link partner setting.\r\n");
|
||||||
|
status = PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, sysClock);
|
||||||
|
}
|
||||||
|
|
||||||
|
PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &link);
|
||||||
|
if (link)
|
||||||
|
{
|
||||||
|
/* Get the actual PHY link speed. */
|
||||||
|
PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base, PHY_ADDRESS, &speed, &duplex);
|
||||||
|
/* Change the MII speed and duplex for actual link status. */
|
||||||
|
config.miiSpeed = (enet_mii_speed_t)speed;
|
||||||
|
config.miiDuplex = (enet_mii_duplex_t)duplex;
|
||||||
|
}
|
||||||
|
|
||||||
|
ENET_Init(imxrt_eth_device.enet_base, &imxrt_eth_device.enet_handle, &config, &buffConfig, &imxrt_eth_device.dev_addr[0], sysClock);
|
||||||
|
ENET_SetCallback(&imxrt_eth_device.enet_handle, _enet_callback, &imxrt_eth_device);
|
||||||
|
ENET_ActiveRead(imxrt_eth_device.enet_base);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* initialize the interface */
|
||||||
|
static rt_err_t rt_imxrt_eth_init(rt_device_t dev)
|
||||||
|
{
|
||||||
|
_enet_io_init();
|
||||||
|
_enet_clk_init();
|
||||||
|
_enet_phy_reset_by_gpio();
|
||||||
|
|
||||||
|
_enet_config();
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_imxrt_eth_open(rt_device_t dev, rt_uint16_t oflag)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("rt_imxrt_eth_open...\n");
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_imxrt_eth_close(rt_device_t dev)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("rt_imxrt_eth_close...\n");
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_size_t rt_imxrt_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("rt_imxrt_eth_read...\n");
|
||||||
|
rt_set_errno(-RT_ENOSYS);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_size_t rt_imxrt_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("rt_imxrt_eth_write...\n");
|
||||||
|
rt_set_errno(-RT_ENOSYS);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static rt_err_t rt_imxrt_eth_control(rt_device_t dev, int cmd, void *args)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("rt_imxrt_eth_control...\n");
|
||||||
|
switch(cmd)
|
||||||
|
{
|
||||||
|
case NIOCTL_GADDR:
|
||||||
|
/* get mac address */
|
||||||
|
if(args) rt_memcpy(args, imxrt_eth_device.dev_addr, 6);
|
||||||
|
else return -RT_ERROR;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default :
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* ethernet device interface */
|
||||||
|
/* transmit packet. */
|
||||||
|
rt_err_t rt_imxrt_eth_tx( rt_device_t dev, struct pbuf* p)
|
||||||
|
{
|
||||||
|
rt_err_t result = RT_EOK;
|
||||||
|
enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
|
||||||
|
|
||||||
|
RT_ASSERT(p != NULL);
|
||||||
|
RT_ASSERT(enet_handle != RT_NULL);
|
||||||
|
|
||||||
|
ETH_PRINTF("rt_imxrt_eth_tx: %d\n", p->len);
|
||||||
|
|
||||||
|
#ifdef ETH_TX_DUMP
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
uint8_t * buf;
|
||||||
|
buf = (uint8_t *)p->payload;
|
||||||
|
for (i = 0; i < p->len; i++)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("%02X ", buf[i]);
|
||||||
|
if (i % 16 == 15)
|
||||||
|
ETH_PRINTF("\n");
|
||||||
|
}
|
||||||
|
ETH_PRINTF("\n");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
result = ENET_SendFrame(imxrt_eth_device.enet_base, enet_handle, p->payload, p->len);
|
||||||
|
|
||||||
|
if (result == kStatus_ENET_TxFrameBusy)
|
||||||
|
{
|
||||||
|
rt_sem_take(&imxrt_eth_device.tx_wait, RT_WAITING_FOREVER);
|
||||||
|
}
|
||||||
|
|
||||||
|
} while (result == kStatus_ENET_TxFrameBusy);
|
||||||
|
|
||||||
|
return RT_EOK;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* reception packet. */
|
||||||
|
struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
|
||||||
|
{
|
||||||
|
uint32_t length = 0;
|
||||||
|
status_t status;
|
||||||
|
|
||||||
|
struct pbuf* p = RT_NULL;
|
||||||
|
enet_handle_t * enet_handle = &imxrt_eth_device.enet_handle;
|
||||||
|
ENET_Type *enet_base = imxrt_eth_device.enet_base;
|
||||||
|
enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic;
|
||||||
|
|
||||||
|
/* Get the Frame size */
|
||||||
|
status = ENET_GetRxFrameSize(enet_handle, &length);
|
||||||
|
|
||||||
|
/* Call ENET_ReadFrame when there is a received frame. */
|
||||||
|
if (length != 0)
|
||||||
|
{
|
||||||
|
/* Received valid frame. Deliver the rx buffer with the size equal to length. */
|
||||||
|
p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
|
||||||
|
|
||||||
|
if (p != NULL)
|
||||||
|
{
|
||||||
|
status = ENET_ReadFrame(enet_base, enet_handle, p->payload, length);
|
||||||
|
if (status == kStatus_Success)
|
||||||
|
{
|
||||||
|
#ifdef ETH_RX_DUMP
|
||||||
|
uint8_t *buf;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
ETH_PRINTF("A frame received. the length:%d\n", p->len);
|
||||||
|
buf = (uint8_t *)p->payload;
|
||||||
|
for (i = 0; i < p->len; i++)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("%02X ", buf[i]);
|
||||||
|
if (i % 16 == 15)
|
||||||
|
ETH_PRINTF("\n");
|
||||||
|
}
|
||||||
|
ETH_PRINTF("\n");
|
||||||
|
#endif
|
||||||
|
return p;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ETH_PRINTF(" A frame read failed\n");
|
||||||
|
pbuf_free(p);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ETH_PRINTF(" pbuf_alloc faild\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if (status == kStatus_ENET_RxFrameError)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("ENET_GetRxFrameSize: kStatus_ENET_RxFrameError\n");
|
||||||
|
/* Update the received buffer when error happened. */
|
||||||
|
/* Get the error information of the received g_frame. */
|
||||||
|
ENET_GetRxErrBeforeReadFrame(enet_handle, error_statistic);
|
||||||
|
/* update the receive buffer. */
|
||||||
|
ENET_ReadFrame(enet_base, enet_handle, NULL, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
ENET_EnableInterrupts(enet_base, kENET_RxFrameInterrupt);
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int rt_hw_imxrt_eth_init(void)
|
||||||
|
{
|
||||||
|
rt_err_t state;
|
||||||
|
|
||||||
|
/* OUI 00-80-E1 STMICROELECTRONICS. */
|
||||||
|
imxrt_eth_device.dev_addr[0] = 0x00;
|
||||||
|
imxrt_eth_device.dev_addr[1] = 0x80;
|
||||||
|
imxrt_eth_device.dev_addr[2] = 0xE1;
|
||||||
|
/* generate MAC addr from 96bit unique ID (only for test). */
|
||||||
|
imxrt_eth_device.dev_addr[3] = 0x12;
|
||||||
|
imxrt_eth_device.dev_addr[4] = 0x34;
|
||||||
|
imxrt_eth_device.dev_addr[5] = 0x56;
|
||||||
|
|
||||||
|
imxrt_eth_device.enet_base = ENET;
|
||||||
|
|
||||||
|
imxrt_eth_device.parent.parent.init = rt_imxrt_eth_init;
|
||||||
|
imxrt_eth_device.parent.parent.open = rt_imxrt_eth_open;
|
||||||
|
imxrt_eth_device.parent.parent.close = rt_imxrt_eth_close;
|
||||||
|
imxrt_eth_device.parent.parent.read = rt_imxrt_eth_read;
|
||||||
|
imxrt_eth_device.parent.parent.write = rt_imxrt_eth_write;
|
||||||
|
imxrt_eth_device.parent.parent.control = rt_imxrt_eth_control;
|
||||||
|
imxrt_eth_device.parent.parent.user_data = RT_NULL;
|
||||||
|
|
||||||
|
imxrt_eth_device.parent.eth_rx = rt_imxrt_eth_rx;
|
||||||
|
imxrt_eth_device.parent.eth_tx = rt_imxrt_eth_tx;
|
||||||
|
|
||||||
|
ETH_PRINTF("sem init: tx_wait\r\n");
|
||||||
|
/* init tx semaphore */
|
||||||
|
rt_sem_init(&imxrt_eth_device.tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO);
|
||||||
|
|
||||||
|
/* register eth device */
|
||||||
|
ETH_PRINTF("eth_device_init start\r\n");
|
||||||
|
state = eth_device_init(&(imxrt_eth_device.parent), "e0");
|
||||||
|
if (RT_EOK == state)
|
||||||
|
{
|
||||||
|
ETH_PRINTF("eth_device_init success\r\n");
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ETH_PRINTF("eth_device_init faild: %d\r\n", state);
|
||||||
|
}
|
||||||
|
return state;
|
||||||
|
}
|
||||||
|
INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef RT_USING_FINSH
|
||||||
|
#include <finsh.h>
|
||||||
|
|
||||||
|
void phy_read(uint32_t phyReg)
|
||||||
|
{
|
||||||
|
uint32_t data;
|
||||||
|
status_t status;
|
||||||
|
|
||||||
|
status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data);
|
||||||
|
if (kStatus_Success == status)
|
||||||
|
{
|
||||||
|
rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rt_kprintf("PHY_Read: %02X --> faild", phyReg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void phy_write(uint32_t phyReg, uint32_t data)
|
||||||
|
{
|
||||||
|
status_t status;
|
||||||
|
|
||||||
|
status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data);
|
||||||
|
if (kStatus_Success == status)
|
||||||
|
{
|
||||||
|
rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rt_kprintf("PHY_Write: %02X --> faild\n", phyReg);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void phy_dump(void)
|
||||||
|
{
|
||||||
|
uint32_t data;
|
||||||
|
status_t status;
|
||||||
|
|
||||||
|
int i;
|
||||||
|
for (i = 0; i < 32; i++)
|
||||||
|
{
|
||||||
|
status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data);
|
||||||
|
if (kStatus_Success != status)
|
||||||
|
{
|
||||||
|
rt_kprintf("phy_dump: %02X --> faild", i);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (i % 8 == 7)
|
||||||
|
{
|
||||||
|
rt_kprintf("%02X --> %08X ", i, data);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
rt_kprintf("%02X --> %08X\n", i, data);
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void enet_reg_dump(void)
|
||||||
|
{
|
||||||
|
ENET_Type *enet_base = imxrt_eth_device.enet_base;
|
||||||
|
|
||||||
|
#define DUMP_REG(__REG) \
|
||||||
|
rt_kprintf("%s(%08X): %08X\n", #__REG, (uint32_t)&enet_base->__REG, enet_base->__REG)
|
||||||
|
|
||||||
|
DUMP_REG(EIR);
|
||||||
|
DUMP_REG(EIMR);
|
||||||
|
DUMP_REG(RDAR);
|
||||||
|
DUMP_REG(TDAR);
|
||||||
|
DUMP_REG(ECR);
|
||||||
|
DUMP_REG(MMFR);
|
||||||
|
DUMP_REG(MSCR);
|
||||||
|
DUMP_REG(MIBC);
|
||||||
|
DUMP_REG(RCR);
|
||||||
|
DUMP_REG(TCR);
|
||||||
|
DUMP_REG(PALR);
|
||||||
|
DUMP_REG(PAUR);
|
||||||
|
DUMP_REG(OPD);
|
||||||
|
DUMP_REG(TXIC);
|
||||||
|
DUMP_REG(RXIC);
|
||||||
|
DUMP_REG(IAUR);
|
||||||
|
DUMP_REG(IALR);
|
||||||
|
DUMP_REG(GAUR);
|
||||||
|
DUMP_REG(GALR);
|
||||||
|
DUMP_REG(TFWR);
|
||||||
|
DUMP_REG(RDSR);
|
||||||
|
DUMP_REG(TDSR);
|
||||||
|
DUMP_REG(MRBR);
|
||||||
|
DUMP_REG(RSFL);
|
||||||
|
DUMP_REG(RSEM);
|
||||||
|
DUMP_REG(RAEM);
|
||||||
|
DUMP_REG(RAFL);
|
||||||
|
DUMP_REG(TSEM);
|
||||||
|
DUMP_REG(TAEM);
|
||||||
|
DUMP_REG(TAFL);
|
||||||
|
DUMP_REG(TIPG);
|
||||||
|
DUMP_REG(FTRL);
|
||||||
|
DUMP_REG(TACC);
|
||||||
|
DUMP_REG(RACC);
|
||||||
|
DUMP_REG(RMON_T_DROP);
|
||||||
|
DUMP_REG(RMON_T_PACKETS);
|
||||||
|
DUMP_REG(RMON_T_BC_PKT);
|
||||||
|
DUMP_REG(RMON_T_MC_PKT);
|
||||||
|
DUMP_REG(RMON_T_CRC_ALIGN);
|
||||||
|
DUMP_REG(RMON_T_UNDERSIZE);
|
||||||
|
DUMP_REG(RMON_T_OVERSIZE);
|
||||||
|
DUMP_REG(RMON_T_FRAG);
|
||||||
|
DUMP_REG(RMON_T_JAB);
|
||||||
|
DUMP_REG(RMON_T_COL);
|
||||||
|
DUMP_REG(RMON_T_P64);
|
||||||
|
DUMP_REG(RMON_T_P65TO127);
|
||||||
|
DUMP_REG(RMON_T_P128TO255);
|
||||||
|
DUMP_REG(RMON_T_P256TO511);
|
||||||
|
DUMP_REG(RMON_T_P512TO1023);
|
||||||
|
DUMP_REG(RMON_T_P1024TO2047);
|
||||||
|
DUMP_REG(RMON_T_P_GTE2048);
|
||||||
|
DUMP_REG(RMON_T_OCTETS);
|
||||||
|
DUMP_REG(IEEE_T_DROP);
|
||||||
|
DUMP_REG(IEEE_T_FRAME_OK);
|
||||||
|
DUMP_REG(IEEE_T_1COL);
|
||||||
|
DUMP_REG(IEEE_T_MCOL);
|
||||||
|
DUMP_REG(IEEE_T_DEF);
|
||||||
|
DUMP_REG(IEEE_T_LCOL);
|
||||||
|
DUMP_REG(IEEE_T_EXCOL);
|
||||||
|
DUMP_REG(IEEE_T_MACERR);
|
||||||
|
DUMP_REG(IEEE_T_CSERR);
|
||||||
|
DUMP_REG(IEEE_T_SQE);
|
||||||
|
DUMP_REG(IEEE_T_FDXFC);
|
||||||
|
DUMP_REG(IEEE_T_OCTETS_OK);
|
||||||
|
DUMP_REG(RMON_R_PACKETS);
|
||||||
|
DUMP_REG(RMON_R_BC_PKT);
|
||||||
|
DUMP_REG(RMON_R_MC_PKT);
|
||||||
|
DUMP_REG(RMON_R_CRC_ALIGN);
|
||||||
|
DUMP_REG(RMON_R_UNDERSIZE);
|
||||||
|
DUMP_REG(RMON_R_OVERSIZE);
|
||||||
|
DUMP_REG(RMON_R_FRAG);
|
||||||
|
DUMP_REG(RMON_R_JAB);
|
||||||
|
DUMP_REG(RMON_R_RESVD_0);
|
||||||
|
DUMP_REG(RMON_R_P64);
|
||||||
|
DUMP_REG(RMON_R_P65TO127);
|
||||||
|
DUMP_REG(RMON_R_P128TO255);
|
||||||
|
DUMP_REG(RMON_R_P256TO511);
|
||||||
|
DUMP_REG(RMON_R_P512TO1023);
|
||||||
|
DUMP_REG(RMON_R_P1024TO2047);
|
||||||
|
DUMP_REG(RMON_R_P_GTE2048);
|
||||||
|
DUMP_REG(RMON_R_OCTETS);
|
||||||
|
DUMP_REG(IEEE_R_DROP);
|
||||||
|
DUMP_REG(IEEE_R_FRAME_OK);
|
||||||
|
DUMP_REG(IEEE_R_CRC);
|
||||||
|
DUMP_REG(IEEE_R_ALIGN);
|
||||||
|
DUMP_REG(IEEE_R_MACERR);
|
||||||
|
DUMP_REG(IEEE_R_FDXFC);
|
||||||
|
DUMP_REG(IEEE_R_OCTETS_OK);
|
||||||
|
DUMP_REG(ATCR);
|
||||||
|
DUMP_REG(ATVR);
|
||||||
|
DUMP_REG(ATOFF);
|
||||||
|
DUMP_REG(ATPER);
|
||||||
|
DUMP_REG(ATCOR);
|
||||||
|
DUMP_REG(ATINC);
|
||||||
|
DUMP_REG(ATSTMP);
|
||||||
|
DUMP_REG(TGSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enet_nvic_tog(void)
|
||||||
|
{
|
||||||
|
NVIC_SetPendingIRQ(ENET_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
void enet_rx_stat(void)
|
||||||
|
{
|
||||||
|
enet_data_error_stats_t *error_statistic = &imxrt_eth_device.error_statistic;
|
||||||
|
|
||||||
|
#define DUMP_STAT(__VAR) \
|
||||||
|
rt_kprintf("%-25s: %08X\n", #__VAR, error_statistic->__VAR);
|
||||||
|
|
||||||
|
DUMP_STAT(statsRxLenGreaterErr);
|
||||||
|
DUMP_STAT(statsRxAlignErr);
|
||||||
|
DUMP_STAT(statsRxFcsErr);
|
||||||
|
DUMP_STAT(statsRxOverRunErr);
|
||||||
|
DUMP_STAT(statsRxTruncateErr);
|
||||||
|
|
||||||
|
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
|
||||||
|
DUMP_STAT(statsRxProtocolChecksumErr);
|
||||||
|
DUMP_STAT(statsRxIpHeadChecksumErr);
|
||||||
|
DUMP_STAT(statsRxMacErr);
|
||||||
|
DUMP_STAT(statsRxPhyErr);
|
||||||
|
DUMP_STAT(statsRxCollisionErr);
|
||||||
|
DUMP_STAT(statsTxErr);
|
||||||
|
DUMP_STAT(statsTxFrameErr);
|
||||||
|
DUMP_STAT(statsTxOverFlowErr);
|
||||||
|
DUMP_STAT(statsTxLateCollisionErr);
|
||||||
|
DUMP_STAT(statsTxExcessCollisionErr);
|
||||||
|
DUMP_STAT(statsTxUnderFlowErr);
|
||||||
|
DUMP_STAT(statsTxTsErr);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void enet_buf_info(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
int i = 0;
|
||||||
|
for (i = 0; i < ENET_RXBD_NUM; i++)
|
||||||
|
{
|
||||||
|
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
|
||||||
|
i,
|
||||||
|
g_rxBuffDescrip[i].length,
|
||||||
|
g_rxBuffDescrip[i].control,
|
||||||
|
g_rxBuffDescrip[i].buffer);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < ENET_TXBD_NUM; i++)
|
||||||
|
{
|
||||||
|
rt_kprintf("%d: length: %-8d, control: %04X, buffer:%p\n",
|
||||||
|
i,
|
||||||
|
g_txBuffDescrip[i].length,
|
||||||
|
g_txBuffDescrip[i].control,
|
||||||
|
g_txBuffDescrip[i].buffer);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
FINSH_FUNCTION_EXPORT(phy_read, read phy register);
|
||||||
|
FINSH_FUNCTION_EXPORT(phy_write, write phy register);
|
||||||
|
FINSH_FUNCTION_EXPORT(phy_dump, dump phy registers);
|
||||||
|
FINSH_FUNCTION_EXPORT(enet_reg_dump, dump enet registers);
|
||||||
|
FINSH_FUNCTION_EXPORT(enet_nvic_tog, toggle enet nvic pendding bit);
|
||||||
|
FINSH_FUNCTION_EXPORT(enet_rx_stat, dump enet rx statistic);
|
||||||
|
FINSH_FUNCTION_EXPORT(enet_buf_info, dump enet tx and tx buffer descripter);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,336 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2017 NXP
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* o Redistributions of source code must retain the above copyright notice, this list
|
||||||
|
* of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
* list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
* other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* o Neither the name of the copyright holder nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||||
|
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||||
|
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "fsl_phy.h"
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*! @brief Defines the timeout macro. */
|
||||||
|
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Prototypes
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Get the ENET instance from peripheral base address.
|
||||||
|
*
|
||||||
|
* @param base ENET peripheral base address.
|
||||||
|
* @return ENET instance.
|
||||||
|
*/
|
||||||
|
extern uint32_t ENET_GetInstance(ENET_Type *base);
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Variables
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||||
|
/*! @brief Pointers to enet clocks for each instance. */
|
||||||
|
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
|
||||||
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Code
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
|
||||||
|
{
|
||||||
|
uint32_t bssReg;
|
||||||
|
uint32_t counter = PHY_TIMEOUT_COUNT;
|
||||||
|
uint32_t idReg = 0;
|
||||||
|
status_t result = kStatus_Success;
|
||||||
|
uint32_t instance = ENET_GetInstance(base);
|
||||||
|
uint32_t timeDelay;
|
||||||
|
uint32_t ctlReg = 0;
|
||||||
|
|
||||||
|
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||||
|
/* Set SMI first. */
|
||||||
|
CLOCK_EnableClock(s_enetClock[instance]);
|
||||||
|
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||||
|
ENET_SetSMI(base, srcClock_Hz, false);
|
||||||
|
|
||||||
|
/* Initialization after PHY stars to work. */
|
||||||
|
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
|
||||||
|
{
|
||||||
|
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
|
||||||
|
counter --;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!counter)
|
||||||
|
{
|
||||||
|
return kStatus_Fail;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Reset PHY. */
|
||||||
|
counter = PHY_TIMEOUT_COUNT;
|
||||||
|
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
|
||||||
|
if (result == kStatus_Success)
|
||||||
|
{
|
||||||
|
|
||||||
|
#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
|
||||||
|
uint32_t data = 0;
|
||||||
|
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
|
||||||
|
if ( result != kStatus_Success)
|
||||||
|
{
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
|
||||||
|
if (result != kStatus_Success)
|
||||||
|
{
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
|
||||||
|
|
||||||
|
/* Set the negotiation. */
|
||||||
|
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
|
||||||
|
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
|
||||||
|
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
|
||||||
|
if (result == kStatus_Success)
|
||||||
|
{
|
||||||
|
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
|
||||||
|
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
|
||||||
|
if (result == kStatus_Success)
|
||||||
|
{
|
||||||
|
/* Check auto negotiation complete. */
|
||||||
|
while (counter --)
|
||||||
|
{
|
||||||
|
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
|
||||||
|
if ( result == kStatus_Success)
|
||||||
|
{
|
||||||
|
PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
|
||||||
|
if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK))
|
||||||
|
{
|
||||||
|
/* Wait a moment for Phy status stable. */
|
||||||
|
for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
|
||||||
|
{
|
||||||
|
__ASM("nop");
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!counter)
|
||||||
|
{
|
||||||
|
return kStatus_PHY_AutoNegotiateFail;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
|
||||||
|
{
|
||||||
|
uint32_t counter;
|
||||||
|
|
||||||
|
/* Clear the SMI interrupt event. */
|
||||||
|
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||||
|
|
||||||
|
/* Starts a SMI write command. */
|
||||||
|
ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
|
||||||
|
|
||||||
|
/* Wait for SMI complete. */
|
||||||
|
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
|
||||||
|
{
|
||||||
|
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check for timeout. */
|
||||||
|
if (!counter)
|
||||||
|
{
|
||||||
|
return kStatus_PHY_SMIVisitTimeout;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear MII interrupt event. */
|
||||||
|
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||||
|
|
||||||
|
return kStatus_Success;
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
|
||||||
|
{
|
||||||
|
assert(dataPtr);
|
||||||
|
|
||||||
|
uint32_t counter;
|
||||||
|
|
||||||
|
/* Clear the MII interrupt event. */
|
||||||
|
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||||
|
|
||||||
|
/* Starts a SMI read command operation. */
|
||||||
|
ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
|
||||||
|
|
||||||
|
/* Wait for MII complete. */
|
||||||
|
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
|
||||||
|
{
|
||||||
|
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check for timeout. */
|
||||||
|
if (!counter)
|
||||||
|
{
|
||||||
|
return kStatus_PHY_SMIVisitTimeout;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get data from MII register. */
|
||||||
|
*dataPtr = ENET_ReadSMIData(base);
|
||||||
|
|
||||||
|
/* Clear MII interrupt event. */
|
||||||
|
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
|
||||||
|
|
||||||
|
return kStatus_Success;
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable)
|
||||||
|
{
|
||||||
|
status_t result;
|
||||||
|
uint32_t data = 0;
|
||||||
|
|
||||||
|
/* Set the loop mode. */
|
||||||
|
if (enable)
|
||||||
|
{
|
||||||
|
if (mode == kPHY_LocalLoop)
|
||||||
|
{
|
||||||
|
if (speed == kPHY_Speed100M)
|
||||||
|
{
|
||||||
|
data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
|
||||||
|
}
|
||||||
|
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* First read the current status in control register. */
|
||||||
|
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
|
||||||
|
if (result == kStatus_Success)
|
||||||
|
{
|
||||||
|
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable the loop mode. */
|
||||||
|
if (mode == kPHY_LocalLoop)
|
||||||
|
{
|
||||||
|
/* First read the current status in control register. */
|
||||||
|
result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
|
||||||
|
if (result == kStatus_Success)
|
||||||
|
{
|
||||||
|
data &= ~PHY_BCTL_LOOP_MASK;
|
||||||
|
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* First read the current status in control one register. */
|
||||||
|
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
|
||||||
|
if (result == kStatus_Success)
|
||||||
|
{
|
||||||
|
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
|
||||||
|
{
|
||||||
|
assert(status);
|
||||||
|
|
||||||
|
status_t result = kStatus_Success;
|
||||||
|
uint32_t data;
|
||||||
|
|
||||||
|
/* Read the basic status register. */
|
||||||
|
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
|
||||||
|
if (result == kStatus_Success)
|
||||||
|
{
|
||||||
|
if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
|
||||||
|
{
|
||||||
|
/* link down. */
|
||||||
|
*status = false;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* link up. */
|
||||||
|
*status = true;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
|
||||||
|
{
|
||||||
|
assert(duplex);
|
||||||
|
|
||||||
|
status_t result = kStatus_Success;
|
||||||
|
uint32_t data, ctlReg;
|
||||||
|
|
||||||
|
/* Read the control two register. */
|
||||||
|
result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
|
||||||
|
if (result == kStatus_Success)
|
||||||
|
{
|
||||||
|
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
|
||||||
|
if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
|
||||||
|
{
|
||||||
|
/* Full duplex. */
|
||||||
|
*duplex = kPHY_FullDuplex;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Half duplex. */
|
||||||
|
*duplex = kPHY_HalfDuplex;
|
||||||
|
}
|
||||||
|
|
||||||
|
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
|
||||||
|
if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
|
||||||
|
{
|
||||||
|
/* 100M speed. */
|
||||||
|
*speed = kPHY_Speed100M;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{ /* 10M speed. */
|
||||||
|
*speed = kPHY_Speed10M;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,222 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||||
|
* Copyright 2016-2017 NXP
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
* are permitted provided that the following conditions are met:
|
||||||
|
*
|
||||||
|
* o Redistributions of source code must retain the above copyright notice, this list
|
||||||
|
* of conditions and the following disclaimer.
|
||||||
|
*
|
||||||
|
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||||
|
* list of conditions and the following disclaimer in the documentation and/or
|
||||||
|
* other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* o Neither the name of the copyright holder nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from this
|
||||||
|
* software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||||
|
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||||
|
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
#ifndef _FSL_PHY_H_
|
||||||
|
#define _FSL_PHY_H_
|
||||||
|
|
||||||
|
#include "fsl_enet.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @addtogroup phy_driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Definitions
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
/*! @brief PHY driver version */
|
||||||
|
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||||
|
|
||||||
|
/*! @brief Defines the PHY registers. */
|
||||||
|
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
|
||||||
|
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
|
||||||
|
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
|
||||||
|
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
|
||||||
|
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
|
||||||
|
#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
|
||||||
|
#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
|
||||||
|
|
||||||
|
#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
|
||||||
|
|
||||||
|
/*! @brief Defines the mask flag in basic control register. */
|
||||||
|
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
|
||||||
|
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
|
||||||
|
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
|
||||||
|
#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
|
||||||
|
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
|
||||||
|
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
|
||||||
|
#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
|
||||||
|
|
||||||
|
/*!@brief Defines the mask flag of operation mode in control two register*/
|
||||||
|
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
|
||||||
|
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
|
||||||
|
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
|
||||||
|
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
|
||||||
|
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
|
||||||
|
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
|
||||||
|
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
|
||||||
|
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
|
||||||
|
#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
|
||||||
|
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
|
||||||
|
|
||||||
|
/*! @brief Defines the mask flag in basic status register. */
|
||||||
|
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
|
||||||
|
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
|
||||||
|
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
|
||||||
|
|
||||||
|
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
|
||||||
|
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
|
||||||
|
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
|
||||||
|
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
|
||||||
|
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
|
||||||
|
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
|
||||||
|
|
||||||
|
/*! @brief Defines the PHY status. */
|
||||||
|
enum _phy_status
|
||||||
|
{
|
||||||
|
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
|
||||||
|
kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
|
||||||
|
};
|
||||||
|
|
||||||
|
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
|
||||||
|
typedef enum _phy_speed
|
||||||
|
{
|
||||||
|
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
|
||||||
|
kPHY_Speed100M /*!< ENET PHY 100M speed. */
|
||||||
|
} phy_speed_t;
|
||||||
|
|
||||||
|
/*! @brief Defines the PHY link duplex. */
|
||||||
|
typedef enum _phy_duplex
|
||||||
|
{
|
||||||
|
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
|
||||||
|
kPHY_FullDuplex /*!< ENET PHY full duplex. */
|
||||||
|
} phy_duplex_t;
|
||||||
|
|
||||||
|
/*! @brief Defines the PHY loopback mode. */
|
||||||
|
typedef enum _phy_loop
|
||||||
|
{
|
||||||
|
kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
|
||||||
|
kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
|
||||||
|
} phy_loop_t;
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* API
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @name PHY Driver
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Initializes PHY.
|
||||||
|
*
|
||||||
|
* This function initialize the SMI interface and initialize PHY.
|
||||||
|
* The SMI is the MII management interface between PHY and MAC, which should be
|
||||||
|
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
|
||||||
|
*
|
||||||
|
* @param base ENET peripheral base address.
|
||||||
|
* @param phyAddr The PHY address.
|
||||||
|
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
|
||||||
|
* @retval kStatus_Success PHY initialize success
|
||||||
|
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||||
|
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
|
||||||
|
*/
|
||||||
|
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief PHY Write function. This function write data over the SMI to
|
||||||
|
* the specified PHY register. This function is called by all PHY interfaces.
|
||||||
|
*
|
||||||
|
* @param base ENET peripheral base address.
|
||||||
|
* @param phyAddr The PHY address.
|
||||||
|
* @param phyReg The PHY register.
|
||||||
|
* @param data The data written to the PHY register.
|
||||||
|
* @retval kStatus_Success PHY write success
|
||||||
|
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||||
|
*/
|
||||||
|
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief PHY Read function. This interface read data over the SMI from the
|
||||||
|
* specified PHY register. This function is called by all PHY interfaces.
|
||||||
|
*
|
||||||
|
* @param base ENET peripheral base address.
|
||||||
|
* @param phyAddr The PHY address.
|
||||||
|
* @param phyReg The PHY register.
|
||||||
|
* @param dataPtr The address to store the data read from the PHY register.
|
||||||
|
* @retval kStatus_Success PHY read success
|
||||||
|
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||||
|
*/
|
||||||
|
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Enables/disables PHY loopback.
|
||||||
|
*
|
||||||
|
* @param base ENET peripheral base address.
|
||||||
|
* @param phyAddr The PHY address.
|
||||||
|
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
|
||||||
|
* the two loopback mode should not be both set. when one loopback mode is set
|
||||||
|
* the other one should be disabled.
|
||||||
|
* @param speed PHY speed for loopback mode.
|
||||||
|
* @param enable True to enable, false to disable.
|
||||||
|
* @retval kStatus_Success PHY loopback success
|
||||||
|
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||||
|
*/
|
||||||
|
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the PHY link status.
|
||||||
|
*
|
||||||
|
* @param base ENET peripheral base address.
|
||||||
|
* @param phyAddr The PHY address.
|
||||||
|
* @param status The link up or down status of the PHY.
|
||||||
|
* - true the link is up.
|
||||||
|
* - false the link is down.
|
||||||
|
* @retval kStatus_Success PHY get link status success
|
||||||
|
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||||
|
*/
|
||||||
|
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
* @brief Gets the PHY link speed and duplex.
|
||||||
|
*
|
||||||
|
* @param base ENET peripheral base address.
|
||||||
|
* @param phyAddr The PHY address.
|
||||||
|
* @param speed The address of PHY link speed.
|
||||||
|
* @param duplex The link duplex of PHY.
|
||||||
|
* @retval kStatus_Success PHY get link speed and duplex success
|
||||||
|
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
|
||||||
|
*/
|
||||||
|
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
|
||||||
|
|
||||||
|
/* @} */
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*! @}*/
|
||||||
|
|
||||||
|
#endif /* _FSL_PHY_H_ */
|
||||||
|
|
@ -53,9 +53,9 @@ STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||||
/* Specify the memory areas */
|
/* Specify the memory areas */
|
||||||
MEMORY
|
MEMORY
|
||||||
{
|
{
|
||||||
m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
|
m_interrupts (RX) : ORIGIN = 0x80000000, LENGTH = 0x80000400
|
||||||
m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0001FC00
|
m_text (RX) : ORIGIN = 0x80000400, LENGTH = 0x8007FC00
|
||||||
m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01E00000
|
m_data (RW) : ORIGIN = 0x80000000, LENGTH = 0x01600000
|
||||||
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
|
m_ncache (RW) : ORIGIN = 0x81E00000, LENGTH = 0x00200000
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -40,7 +40,7 @@ if PLATFORM == 'gcc':
|
||||||
OBJCPY = PREFIX + 'objcopy'
|
OBJCPY = PREFIX + 'objcopy'
|
||||||
STRIP = PREFIX + 'strip'
|
STRIP = PREFIX + 'strip'
|
||||||
|
|
||||||
DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
|
DEVICE = ' -std=c99 -mcpu=cortex-m7 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -ffunction-sections -fdata-sections'
|
||||||
CFLAGS = DEVICE + ' -g -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_USED -eentry'
|
CFLAGS = DEVICE + ' -g -Wall -DUSE_HAL_DRIVER -D__ASSEMBLY__ -D__FPU_USED -eentry'
|
||||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||||
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T imxrt1052_sdram.ld'
|
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=imxrt1052_sdram.map,-cref,-u,Reset_Handler -T imxrt1052_sdram.ld'
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue