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https://github.com/RT-Thread/rt-thread.git
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[update] stm32mp1 heap address.
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@ -26,15 +26,19 @@ extern "C" {
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#define STM32_FLASH_SIZE (192 * 1024)
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#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
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#if defined(BSP_USING_OPENAMP)
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#define STM32_SRAM_BEGIN (uint32_t)0x10030000
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#else
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#define STM32_SRAM_BEGIN (uint32_t)0x2FFF0000
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#endif
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#define STM32_SRAM_SIZE (64)
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#define STM32_SRAM_END (STM32_SRAM_BEGIN + (STM32_SRAM_SIZE * 1024))
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#define STM32_SRAM_SIZE (64)
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#define STM32_SRAM_END (0x10030000 + 64 * 1024)
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#define HEAP_BEGIN STM32_SRAM_BEGIN
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#if defined(__CC_ARM) || defined(__CLANG_ARM)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN (&__bss_end)
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#endif
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#define HEAP_END STM32_SRAM_END
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void SystemClock_Config(void);
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@ -46,4 +50,3 @@ extern void _Error_Handler(char *s, int num);
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#endif
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#endif
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@ -84,7 +84,6 @@ void HAL_MspInit(void)
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if (IS_ENGINEERING_BOOT_MODE())
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{
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__HAL_RCC_SYSRAM_CLK_ENABLE();
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__HAL_RCC_RETRAM_CLK_ENABLE();
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}
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HAL_NVIC_SetPriority(RCC_WAKEUP_IRQn, 0, 0);
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@ -12,6 +12,7 @@
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#include "board.h"
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void PeriphCommonClock_Config(void);
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/**
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* @brief System Clock Configuration
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* @retval None
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@ -124,6 +125,12 @@ void SystemClock_Config(void)
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/**Set the HSE division factor for RTC clock
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*/
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__HAL_RCC_RTC_HSEDIV(24);
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/* Configure the peripherals common clocks */
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if(IS_ENGINEERING_BOOT_MODE())
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{
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PeriphCommonClock_Config();
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}
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}
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@ -23,18 +23,23 @@ extern "C" {
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#endif
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#define STM32_FLASH_START_ADRESS ((uint32_t)0x10000000)
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#define STM32_FLASH_SIZE (191 * 1024)
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#define STM32_FLASH_SIZE (192 * 1024)
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#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
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#if defined(BSP_USING_OPENAMP)
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#define STM32_SRAM_BEGIN (uint32_t)0x10030000
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#else
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#define STM32_SRAM_BEGIN (uint32_t)0x2FFF0000
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#endif
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#define STM32_SRAM_SIZE (64)
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#define STM32_SRAM_END (STM32_SRAM_BEGIN + (STM32_SRAM_SIZE * 1024))
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#define HEAP_BEGIN STM32_SRAM_BEGIN
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#define STM32_SRAM_SIZE (64)
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#define STM32_SRAM_END (0x10030000 + 64 * 1024)
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#if defined(__CC_ARM) || defined(__CLANG_ARM)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN (&__bss_end)
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#endif
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#define HEAP_END STM32_SRAM_END
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void SystemClock_Config(void);
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@ -46,4 +51,3 @@ extern void _Error_Handler(char *s, int num);
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#endif
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#endif
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