[bsp][STM32] update linker_scripts for stm32 bsp
This commit is contained in:
SummerGift
parent
633876a66b
commit
0a4abb8f94
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@ -7,6 +7,7 @@
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# RT-Thread Kernel
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#
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CONFIG_RT_NAME_MAX=8
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# CONFIG_RT_USING_SMP is not set
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CONFIG_RT_ALIGN_SIZE=4
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# CONFIG_RT_THREAD_PRIORITY_8 is not set
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CONFIG_RT_THREAD_PRIORITY_32=y
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@ -15,6 +16,7 @@ CONFIG_RT_THREAD_PRIORITY_MAX=32
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CONFIG_RT_TICK_PER_SECOND=1000
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CONFIG_RT_USING_OVERFLOW_CHECK=y
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CONFIG_RT_USING_HOOK=y
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CONFIG_RT_USING_IDLE_HOOK=y
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CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
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CONFIG_IDLE_THREAD_STACK_SIZE=1024
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# CONFIG_RT_USING_TIMER_SOFT is not set
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@ -63,6 +65,7 @@ CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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CONFIG_ARCH_ARM=y
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CONFIG_ARCH_ARM_CORTEX_M=y
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CONFIG_ARCH_ARM_CORTEX_M4=y
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# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
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#
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# RT-Thread Components
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@ -112,10 +115,12 @@ CONFIG_RT_USING_SERIAL=y
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
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CONFIG_RT_USING_PIN=y
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# CONFIG_RT_USING_ADC is not set
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# CONFIG_RT_USING_PWM is not set
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# CONFIG_RT_USING_MTD_NOR is not set
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# CONFIG_RT_USING_MTD_NAND is not set
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# CONFIG_RT_USING_MTD is not set
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# CONFIG_RT_USING_PM is not set
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# CONFIG_RT_USING_RTC is not set
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# CONFIG_RT_USING_SDIO is not set
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# CONFIG_RT_USING_SPI is not set
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@ -173,6 +178,7 @@ CONFIG_RT_USING_PIN=y
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#
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# CONFIG_RT_USING_LOGTRACE is not set
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# CONFIG_RT_USING_RYM is not set
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# CONFIG_RT_USING_ULOG is not set
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#
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# ARM CMSIS
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@ -245,7 +251,6 @@ CONFIG_RT_USING_PIN=y
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#
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# CONFIG_PKG_USING_OPENMV is not set
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# CONFIG_PKG_USING_MUPDF is not set
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# CONFIG_PKG_USING_BEEPPLAYER is not set
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#
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# tools packages
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@ -273,6 +278,7 @@ CONFIG_RT_USING_PIN=y
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# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
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# CONFIG_PKG_USING_CMSIS is not set
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# CONFIG_PKG_USING_DFS_YAFFS is not set
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# CONFIG_PKG_USING_LITTLEFS is not set
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#
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# peripheral libraries and drivers
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@ -329,22 +335,28 @@ CONFIG_SOC_STM32F407ZG=y
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#
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# Onboard Peripheral Drivers
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#
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CONFIG_BSP_USING_USB_TO_USART=y
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# CONFIG_BSP_USING_SPI_FLASH is not set
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# CONFIG_BSP_USING_COM3 is not set
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# CONFIG_BSP_USING_EEPROM is not set
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# CONFIG_BSP_USING_ETH is not set
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# CONFIG_BSP_USING_MPU6050 is not set
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#
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# Offboard Peripheral Drivers
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#
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#
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# On-chip Peripheral Drivers
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#
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CONFIG_BSP_USING_GPIO=y
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CONFIG_BSP_USING_UART=y
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CONFIG_BSP_USING_UART1=y
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# CONFIG_BSP_USING_UART2 is not set
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# CONFIG_BSP_USING_UART3 is not set
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# CONFIG_BSP_USING_UART6 is not set
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# CONFIG_BSP_UART_USING_DMA_RX is not set
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# CONFIG_BSP_USING_SPI is not set
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# CONFIG_BSP_USING_I2C is not set
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# CONFIG_BSP_USING_SPI1 is not set
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# CONFIG_BSP_USING_SPI2 is not set
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# CONFIG_BSP_USING_SPI3 is not set
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# CONFIG_BSP_SPI_USING_DMA is not set
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# CONFIG_BSP_USING_I2C1 is not set
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#
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# Board extended module Drivers
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#
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@ -116,7 +116,7 @@ msh >
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## 注意事项
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- STM32F407 有两块 RAM：RAM1(0x20000000,128K) 、RAM2(0x10000000,64K) ，本 BSP 将 RT-Thread HEAP 放到了 RAM1，将 RW 段数据放到了 RAM2（此地址空间不能使用 DMA 传输）。因此，如需使用 DMA 功能需使用 `rt_malloc/rt_calloc` 函数为缓冲区分配 RAM1 的空间。
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暂无
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## 联系人信息
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@ -22,12 +22,21 @@
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#define LED1_PIN GET_PIN(F, 10)
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#endif
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#define STM32_SRAM1_SIZE (128)
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#define STM32_SRAM1_START (0x20000000)
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#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024)
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#define STM32_SRAM_SIZE (128)
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#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
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#define HEAP_BEGIN STM32_SRAM1_START
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#define HEAP_END STM32_SRAM1_END
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#ifdef __CC_ARM
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END STM32_SRAM_END
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void SystemClock_Config(void);
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void MX_GPIO_Init(void);
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@ -18,7 +18,6 @@ define symbol __ICFEDIT_size_heap__ = 0x0000;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
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define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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@ -28,5 +27,4 @@ do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM1_region { section .sram };
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place in RAM2_region { readwrite, block CSTACK};
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place in RAM1_region { readwrite, last block CSTACK };
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@ -78,7 +78,7 @@ SECTIONS
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM2
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} >RAM1
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.stack :
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{
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@ -87,7 +87,7 @@ SECTIONS
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. = . + _system_stack_size;
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. = ALIGN(4);
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_estack = .;
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} >RAM2
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} >RAM1
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__bss_start = .;
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.bss :
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@ -105,7 +105,7 @@ SECTIONS
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_ebss = . ;
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*(.bss.init)
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} > RAM2
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} > RAM1
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__bss_end = .;
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_end = .;
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@ -8,7 +8,7 @@ LR_IROM1 0x08000000 0x00100000 { ; load region size_region
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM2 0x10000000 0x00010000 { ; RW data
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RW_IRAM1 0x20000000 0x00020000 { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -2,7 +2,7 @@
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<project>
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<fileVersion>3</fileVersion>
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<configuration>
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<name>Debug</name>
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<name>rt-thread</name>
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<toolchain>
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<name>ARM</name>
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</toolchain>
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@ -80,7 +80,7 @@
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</option>
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<option>
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<name>OCProductVersion</name>
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<state>8.11.3.13977</state>
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<state>8.20.1.14181</state>
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</option>
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<option>
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<name>OCDynDriverList</name>
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@ -88,7 +88,7 @@
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</option>
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<option>
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<name>OCLastSavedByProductVersion</name>
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<state>8.11.3.13977</state>
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<state>8.20.1.14181</state>
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</option>
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<option>
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<name>UseFlashLoader</name>
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@ -1403,11 +1403,11 @@
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<loadFlag>1</loadFlag>
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</plugin>
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<plugin>
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<file>$EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin</file>
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<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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<loadFlag>0</loadFlag>
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</plugin>
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<plugin>
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<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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<file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
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<loadFlag>0</loadFlag>
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</plugin>
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<plugin>
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@ -2818,11 +2818,11 @@
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<loadFlag>1</loadFlag>
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</plugin>
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<plugin>
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<file>$EW_DIR$\common\plugins\IARProbe\IarProbePlugin.ENU.ewplugin</file>
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<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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<loadFlag>0</loadFlag>
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</plugin>
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<plugin>
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<file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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<file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
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<loadFlag>0</loadFlag>
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</plugin>
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<plugin>
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@ -13,6 +13,7 @@
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#define RT_TICK_PER_SECOND 1000
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#define RT_USING_OVERFLOW_CHECK
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#define RT_USING_HOOK
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#define RT_USING_IDLE_HOOK
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#define RT_IDEL_HOOK_LIST_SIZE 4
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#define IDLE_THREAD_STACK_SIZE 1024
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#define RT_DEBUG
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@ -153,6 +154,9 @@
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/* example package: hello */
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/* rtpkgs online packages */
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#define SOC_FAMILY_STM32
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#define SOC_SERIES_STM32F4
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@ -162,13 +166,14 @@
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/* Onboard Peripheral Drivers */
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/* Offboard Peripheral Drivers */
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#define BSP_USING_USB_TO_USART
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/* On-chip Peripheral Drivers */
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#define BSP_USING_GPIO
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#define BSP_USING_UART
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#define BSP_USING_UART1
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/* Board extended module Drivers */
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#endif
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@ -120,7 +120,7 @@ msh >
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## 注意事项
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STM32F429 有两块 RAM：RAM1(0x20000000,192K) 、RAM2(0x10000000,64K) ，本 BSP 将 RT-Thread HEAP 放到了 RAM1，将 RW 段数据放到了 RAM2（此地址空间不能使用 DMA 传输）。因此，如需使用 DMA 功能传输缓冲区内的数据，需要使用 `rt_malloc/rt_calloc` 函数为需要使用 DMA 传输的缓冲区分配内存，这样申请的内存地址将存在于 RAM1 空间内。
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暂无
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## 联系人信息
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@ -19,12 +19,21 @@
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#include "drv_gpio.h"
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#endif
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#define STM32_SRAM1_SIZE (192)
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#define STM32_SRAM1_START (0x20000000)
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#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024)
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#define STM32_SRAM_SIZE (192)
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#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
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#define HEAP_BEGIN STM32_SRAM1_START
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#define HEAP_END STM32_SRAM1_END
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#if defined(__CC_ARM) || defined(__CLANG_ARM)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN (&__bss_end)
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#endif
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#define HEAP_END STM32_SRAM_END
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/* Board Pin definitions */
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#define LED0_PIN GET_PIN(B, 1)
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@ -18,7 +18,6 @@ define symbol __ICFEDIT_size_heap__ = 0x0000;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
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define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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@ -28,5 +27,4 @@ do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM1_region { section .sram };
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place in RAM2_region { readwrite, block CSTACK};
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place in RAM1_region { readwrite, last block CSTACK };
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@ -78,7 +78,7 @@ SECTIONS
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. = ALIGN(4);
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/* This is used by the startup in order to initialize the .data secion */
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_edata = . ;
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} >RAM2
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} >RAM1
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.stack :
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{
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@ -87,7 +87,7 @@ SECTIONS
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. = . + _system_stack_size;
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. = ALIGN(4);
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_estack = .;
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} >RAM2
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} >RAM1
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__bss_start = .;
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.bss :
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@ -105,7 +105,7 @@ SECTIONS
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_ebss = . ;
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*(.bss.init)
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} > RAM2
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} > RAM1
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__bss_end = .;
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_end = .;
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@ -8,7 +8,7 @@ LR_IROM1 0x08000000 0x00100000 { ; load region size_region
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM2 0x10000000 0x00010000 { ; RW data
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RW_IRAM1 0x20000000 0x00030000 { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -47,7 +47,6 @@
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| SD卡 | 即将支持 | |
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| CAN | 即将支持 | |
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| SDRAM | 即将支持 | |
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| ESP8266 模块 | 即将支持 | |
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| EMW1062 | 暂不支持 | |
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| **片上外设** | **支持情况** | **备注** |
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| GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...176 |
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@ -119,7 +118,7 @@ msh >
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## 注意事项
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STM32F429 有两块 RAM：RAM1(0x20000000,192K) 、RAM2(0x10000000,64K) ，本 BSP 将 RT-Thread HEAP 放到了 RAM1，将 RW 段数据放到了 RAM2（此地址空间不能使用 DMA 传输）。因此，如需使用 DMA 功能传输缓冲区内的数据，需要使用 `rt_malloc/rt_calloc` 函数为需要使用 DMA 传输的缓冲区分配内存，这样申请的内存地址将存在于 RAM1 空间内。
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暂无
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## 联系人信息
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@ -19,12 +19,21 @@
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#include "drv_gpio.h"
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#endif
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#define STM32_SRAM1_SIZE (192)
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#define STM32_SRAM1_START (0x20000000)
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#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024)
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#define STM32_SRAM_SIZE (192)
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#define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
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#define HEAP_BEGIN STM32_SRAM1_START
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#define HEAP_END STM32_SRAM1_END
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#if defined(__CC_ARM) || defined(__CLANG_ARM)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
|
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extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END STM32_SRAM_END
|
||||
|
||||
/* Board Pin definitions */
|
||||
#define LED0_PIN GET_PIN(H, 10)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@ define symbol __ICFEDIT_size_heap__ = 0x0000;
|
|||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
|
||||
|
|
@ -28,5 +27,4 @@ do not initialize { section .noinit };
|
|||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM1_region { section .sram };
|
||||
place in RAM2_region { readwrite, block CSTACK};
|
||||
place in RAM1_region { readwrite, last block CSTACK };
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >RAM2
|
||||
} >RAM1
|
||||
|
||||
.stack :
|
||||
{
|
||||
|
|
@ -87,7 +87,7 @@ SECTIONS
|
|||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >RAM2
|
||||
} >RAM1
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
|
|
@ -105,7 +105,7 @@ SECTIONS
|
|||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > RAM2
|
||||
} > RAM1
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ LR_IROM1 0x08000000 0x00100000 { ; load region size_region
|
|||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
RW_IRAM2 0x10000000 0x00010000 { ; RW data
|
||||
RW_IRAM1 0x20000000 0x00030000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue