Merge pull request #1731 from jesven/master
[bsp][raspi2] add raspberry pi 2 support
This commit is contained in:
Bernard Xiong
GitHub
commit
095872e914
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@ -0,0 +1,290 @@
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#
|
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# Automatically generated file; DO NOT EDIT.
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# RT-Thread Project Configuration
|
||||
#
|
||||
|
||||
#
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# RT-Thread Kernel
|
||||
#
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||||
CONFIG_RT_NAME_MAX=8
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CONFIG_RT_ALIGN_SIZE=4
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||||
# CONFIG_RT_THREAD_PRIORITY_8 is not set
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||||
CONFIG_RT_THREAD_PRIORITY_32=y
|
||||
# CONFIG_RT_THREAD_PRIORITY_256 is not set
|
||||
CONFIG_RT_THREAD_PRIORITY_MAX=32
|
||||
CONFIG_RT_TICK_PER_SECOND=100
|
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CONFIG_RT_USING_OVERFLOW_CHECK=y
|
||||
CONFIG_RT_USING_HOOK=y
|
||||
CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
|
||||
CONFIG_IDLE_THREAD_STACK_SIZE=256
|
||||
# CONFIG_RT_USING_TIMER_SOFT is not set
|
||||
CONFIG_RT_DEBUG=y
|
||||
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
|
||||
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
|
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|
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#
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# Inter-Thread communication
|
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#
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CONFIG_RT_USING_SEMAPHORE=y
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CONFIG_RT_USING_MUTEX=y
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CONFIG_RT_USING_EVENT=y
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CONFIG_RT_USING_MAILBOX=y
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||||
CONFIG_RT_USING_MESSAGEQUEUE=y
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# CONFIG_RT_USING_SIGNALS is not set
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|
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#
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# Memory Management
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#
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CONFIG_RT_USING_MEMPOOL=y
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# CONFIG_RT_USING_MEMHEAP is not set
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# CONFIG_RT_USING_NOHEAP is not set
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CONFIG_RT_USING_SMALL_MEM=y
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# CONFIG_RT_USING_SLAB is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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CONFIG_RT_USING_HEAP=y
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#
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# Kernel Device Object
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#
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CONFIG_RT_USING_DEVICE=y
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# CONFIG_RT_USING_DEVICE_OPS is not set
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# CONFIG_RT_USING_INTERRUPT_INFO is not set
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=128
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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# CONFIG_RT_USING_MODULE is not set
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CONFIG_ARCH_ARM=y
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CONFIG_ARCH_ARM_CORTEX_A=y
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CONFIG_ARCH_ARM_CORTEX_A7=y
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#
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# RT-Thread Components
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#
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CONFIG_RT_USING_COMPONENTS_INIT=y
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CONFIG_RT_USING_USER_MAIN=y
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CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
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CONFIG_RT_MAIN_THREAD_PRIORITY=10
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#
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# C++ features
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#
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# CONFIG_RT_USING_CPLUSPLUS is not set
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#
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# Command shell
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#
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CONFIG_RT_USING_FINSH=y
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CONFIG_FINSH_THREAD_NAME="tshell"
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CONFIG_FINSH_USING_HISTORY=y
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CONFIG_FINSH_HISTORY_LINES=5
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CONFIG_FINSH_USING_SYMTAB=y
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CONFIG_FINSH_USING_DESCRIPTION=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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CONFIG_FINSH_THREAD_PRIORITY=20
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CONFIG_FINSH_THREAD_STACK_SIZE=4096
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CONFIG_FINSH_CMD_SIZE=80
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_USING_MSH=y
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CONFIG_FINSH_USING_MSH_DEFAULT=y
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CONFIG_FINSH_USING_MSH_ONLY=y
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CONFIG_FINSH_ARG_MAX=10
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#
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# Device virtual file system
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#
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# CONFIG_RT_USING_DFS is not set
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#
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# Device Drivers
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#
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CONFIG_RT_USING_DEVICE_IPC=y
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CONFIG_RT_PIPE_BUFSZ=512
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CONFIG_RT_USING_SERIAL=y
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# CONFIG_RT_USING_CAN is not set
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# CONFIG_RT_USING_HWTIMER is not set
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# CONFIG_RT_USING_CPUTIME is not set
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# CONFIG_RT_USING_I2C is not set
|
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# CONFIG_RT_USING_PIN is not set
|
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# CONFIG_RT_USING_PWM is not set
|
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# CONFIG_RT_USING_MTD_NOR is not set
|
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# CONFIG_RT_USING_MTD_NAND is not set
|
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# CONFIG_RT_USING_RTC is not set
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# CONFIG_RT_USING_SDIO is not set
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# CONFIG_RT_USING_SPI is not set
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# CONFIG_RT_USING_WDT is not set
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# CONFIG_RT_USING_WIFI is not set
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# CONFIG_RT_USING_AUDIO is not set
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#
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# Using USB
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#
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# CONFIG_RT_USING_USB_HOST is not set
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# CONFIG_RT_USING_USB_DEVICE is not set
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#
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# POSIX layer and C standard library
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#
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# CONFIG_RT_USING_LIBC is not set
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# CONFIG_RT_USING_PTHREADS is not set
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#
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# Network
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#
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#
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# Socket abstraction layer
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#
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# CONFIG_RT_USING_SAL is not set
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#
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# light weight TCP/IP stack
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#
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# CONFIG_RT_USING_LWIP is not set
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#
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# Modbus master and slave stack
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#
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# CONFIG_RT_USING_MODBUS is not set
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#
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# AT commands
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#
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# CONFIG_RT_USING_AT is not set
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#
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# VBUS(Virtual Software BUS)
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#
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# CONFIG_RT_USING_VBUS is not set
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#
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# Utilities
|
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#
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# CONFIG_RT_USING_LOGTRACE is not set
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# CONFIG_RT_USING_RYM is not set
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|
||||
#
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# RT-Thread online packages
|
||||
#
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#
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# IoT - internet of things
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#
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# CONFIG_PKG_USING_PAHOMQTT is not set
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# CONFIG_PKG_USING_WEBCLIENT is not set
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# CONFIG_PKG_USING_MONGOOSE is not set
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# CONFIG_PKG_USING_WEBTERMINAL is not set
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# CONFIG_PKG_USING_CJSON is not set
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# CONFIG_PKG_USING_JSMN is not set
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# CONFIG_PKG_USING_LJSON is not set
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# CONFIG_PKG_USING_EZXML is not set
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# CONFIG_PKG_USING_NANOPB is not set
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#
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# Wi-Fi
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#
|
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#
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# Marvell WiFi
|
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#
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# CONFIG_PKG_USING_WLANMARVELL is not set
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#
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# Wiced WiFi
|
||||
#
|
||||
# CONFIG_PKG_USING_WLAN_WICED is not set
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# CONFIG_PKG_USING_COAP is not set
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# CONFIG_PKG_USING_NOPOLL is not set
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# CONFIG_PKG_USING_NETUTILS is not set
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# CONFIG_PKG_USING_AT_DEVICE is not set
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#
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# IoT Cloud
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#
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# CONFIG_PKG_USING_ONENET is not set
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# CONFIG_PKG_USING_GAGENT_CLOUD is not set
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# CONFIG_PKG_USING_ALI_IOTKIT is not set
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# CONFIG_PKG_USING_AZURE is not set
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#
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# security packages
|
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#
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# CONFIG_PKG_USING_MBEDTLS is not set
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# CONFIG_PKG_USING_libsodium is not set
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# CONFIG_PKG_USING_TINYCRYPT is not set
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#
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# language packages
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#
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# CONFIG_PKG_USING_LUA is not set
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# CONFIG_PKG_USING_JERRYSCRIPT is not set
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# CONFIG_PKG_USING_MICROPYTHON is not set
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#
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# multimedia packages
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#
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# CONFIG_PKG_USING_OPENMV is not set
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# CONFIG_PKG_USING_MUPDF is not set
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#
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# tools packages
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#
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# CONFIG_PKG_USING_CMBACKTRACE is not set
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# CONFIG_PKG_USING_EASYFLASH is not set
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# CONFIG_PKG_USING_EASYLOGGER is not set
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# CONFIG_PKG_USING_SYSTEMVIEW is not set
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#
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# system packages
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#
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# CONFIG_PKG_USING_GUIENGINE is not set
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# CONFIG_PKG_USING_PERSIMMON is not set
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# CONFIG_PKG_USING_CAIRO is not set
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# CONFIG_PKG_USING_PIXMAN is not set
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# CONFIG_PKG_USING_LWEXT4 is not set
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# CONFIG_PKG_USING_PARTITION is not set
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# CONFIG_PKG_USING_FAL is not set
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# CONFIG_PKG_USING_SQLITE is not set
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# CONFIG_PKG_USING_RTI is not set
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# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
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#
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# peripheral libraries and drivers
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#
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# CONFIG_PKG_USING_STM32F4_HAL is not set
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# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
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# CONFIG_PKG_USING_REALTEK_AMEBA is not set
|
||||
# CONFIG_PKG_USING_SHT2X is not set
|
||||
# CONFIG_PKG_USING_AHT10 is not set
|
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|
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#
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# miscellaneous packages
|
||||
#
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# CONFIG_PKG_USING_LIBCSV is not set
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# CONFIG_PKG_USING_OPTPARSE is not set
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# CONFIG_PKG_USING_FASTLZ is not set
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# CONFIG_PKG_USING_MINILZO is not set
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# CONFIG_PKG_USING_QUICKLZ is not set
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# CONFIG_PKG_USING_MULTIBUTTON is not set
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# CONFIG_PKG_USING_CANFESTIVAL is not set
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# CONFIG_PKG_USING_ZLIB is not set
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# CONFIG_PKG_USING_DSTR is not set
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#
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# sample package
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#
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# CONFIG_PKG_USING_SAMPLES is not set
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#
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# example package: hello
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#
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# CONFIG_PKG_USING_HELLO is not set
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CONFIG_BCM2836_SOC=y
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CONFIG_RT_USING_UART1=y
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@ -0,0 +1,26 @@
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mainmenu "RT-Thread Project Configuration"
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config $BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config $RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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config $PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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config BCM2836_SOC
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bool
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select ARCH_ARM_CORTEX_A7
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default y
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source "driver/Kconfig"
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@ -0,0 +1,108 @@
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|# Raspberry A7板级支持包说明
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|
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## 1. 简介
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|
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树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派2采用4核Broadcom BCM2836 (ARMv7-A)芯片、双核VideoCore IV GPU和1GB内存。
|
||||
|
||||
这份RT-Thread BSP是针对 Raspberry Pi 2B 的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
|
||||
|
||||
当前Raspberry Pi 2B对应的硬件特性：
|
||||
|
||||
| 硬件 | 描述 |
|
||||
|------- | ------------------------------- |
|
||||
| CPU | ARM Cortex-A7（4核心） |
|
||||
| 主频 | 900M |
|
||||
| Memory | 1GB (0x0000000 - 0x40000000) |
|
||||
| | 其中0x3f000000 - 0x40000000为peripheral |
|
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|
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## 2. 编译说明
|
||||
|
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Windows环境下推荐使用[env工具][1]
|
||||
|
||||
Linux下推荐使用gcc工具 [gcc-arm-none-eabi-4_8-2014q1_linux][2]，如果还没有编译工具，下载后，解开文件。
|
||||
|
||||
```
|
||||
tar vxf gcc-arm-none-eabi-4_8-2014q1_linux.tar.bz2
|
||||
```
|
||||
|
||||
Linux环境可能需要修改编译器目录设置，修改bsp/raspi2/rtconfig.py中的
|
||||
|
||||
```
|
||||
EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
|
||||
```
|
||||
|
||||
为编译工具的实际所在目录，这里注意要加上后缀 /bin
|
||||
|
||||
进入到`bsp/raspi2`目录中，运行以下命令：
|
||||
|
||||
```
|
||||
scons
|
||||
```
|
||||
|
||||
来编译这个板级支持包。如果编译正确无误，会产生kernel.elf、kernel.img文件。
|
||||
kernel.img即是要cp到raspberry SD卡中根目录的文件
|
||||
|
||||
|
||||
## 3. 执行
|
||||
|
||||
### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
|
||||
|
||||
Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
|
||||
|
||||
解开下载的镜像文件, linux下使用如下的命令
|
||||
|
||||
```
|
||||
unzip 2018-06-27-raspbian-stretch-lite.zip
|
||||
```
|
||||
|
||||
准备一张空SD卡，linux环境下，插入电脑并执行
|
||||
|
||||
```
|
||||
sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
|
||||
```
|
||||
|
||||
**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
|
||||
|
||||
Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
|
||||
|
||||
最后把kernel7.img放入SD boot分区，覆盖原来的文件。
|
||||
|
||||
### 3.2 准备好串口线
|
||||
|
||||
目前版本是使用raspi2的 GPIO 14, GPIO 15来作路口输出。
|
||||
|
||||
串口参数： 115200 8N1 ，硬件和软件流控为关。
|
||||
|
||||
按上面的方法做好SD卡后，插入树莓派2B，通电。
|
||||
|
||||
输出到串口的信息应该是这样的：
|
||||
|
||||
```text
|
||||
heap: 0x00020b20 - 0x00400000
|
||||
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 3.1.0 build Aug 23 2018
|
||||
2006 - 2018 Copyright by rt-thread team
|
||||
Hello RT-Thread!
|
||||
msh >
|
||||
|
||||
```
|
||||
|
||||
|
||||
## 4. 支持情况
|
||||
|
||||
| 驱动 | 支持情况 | 备注 |
|
||||
| ------ | ---- | :------: |
|
||||
| UART | 支持 | UART0|
|
||||
|
||||
## 5. 联系人信息
|
||||
|
||||
维护人：[bernard][5]
|
||||
|
||||
[1]: https://www.rt-thread.org/page/download.html
|
||||
[2]: https://launchpad.net/gcc-arm-embedded/4.8/4.8-2014-q1-update/+download/gcc-arm-none-eabi-4_8-2014q1-20140314-linux.tar.bz2
|
||||
|
||||
[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
|
||||
[4]: https://etcher.io
|
||||
[5:] https://github.com/BernardXiong
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
# for module compiling
|
||||
import os
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
from rtconfig import RTT_ROOT
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
from building import *
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
CPPPATH = [cwd, str(Dir('#'))]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* File : main.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-5-30 Bernard the first version
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
int main(int argc, char** argv)
|
||||
{
|
||||
rt_kprintf("Hello RT-Thread!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* File : mnt.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
int mnt_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
#ifndef __ARMV7_H__
|
||||
#define __ARMV7_H__
|
||||
|
||||
/* the exception stack without VFP registers */
|
||||
struct rt_hw_exp_stack
|
||||
{
|
||||
unsigned long r0;
|
||||
unsigned long r1;
|
||||
unsigned long r2;
|
||||
unsigned long r3;
|
||||
unsigned long r4;
|
||||
unsigned long r5;
|
||||
unsigned long r6;
|
||||
unsigned long r7;
|
||||
unsigned long r8;
|
||||
unsigned long r9;
|
||||
unsigned long r10;
|
||||
unsigned long fp;
|
||||
unsigned long ip;
|
||||
unsigned long sp;
|
||||
unsigned long lr;
|
||||
unsigned long pc;
|
||||
unsigned long cpsr;
|
||||
};
|
||||
|
||||
struct rt_hw_stack
|
||||
{
|
||||
unsigned long cpsr;
|
||||
unsigned long r0;
|
||||
unsigned long r1;
|
||||
unsigned long r2;
|
||||
unsigned long r3;
|
||||
unsigned long r4;
|
||||
unsigned long r5;
|
||||
unsigned long r6;
|
||||
unsigned long r7;
|
||||
unsigned long r8;
|
||||
unsigned long r9;
|
||||
unsigned long r10;
|
||||
unsigned long fp;
|
||||
unsigned long ip;
|
||||
unsigned long lr;
|
||||
unsigned long pc;
|
||||
};
|
||||
|
||||
#define USERMODE 0x10
|
||||
#define FIQMODE 0x11
|
||||
#define IRQMODE 0x12
|
||||
#define SVCMODE 0x13
|
||||
#define MONITORMODE 0x16
|
||||
#define ABORTMODE 0x17
|
||||
#define HYPMODE 0x1b
|
||||
#define UNDEFMODE 0x1b
|
||||
#define MODEMASK 0x1f
|
||||
#define NOINT 0xc0
|
||||
|
||||
#define T_Bit (1<<5)
|
||||
#define F_Bit (1<<6)
|
||||
#define I_Bit (1<<7)
|
||||
#define A_Bit (1<<8)
|
||||
#define E_Bit (1<<9)
|
||||
#define J_Bit (1<<24)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* File : context.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-05 Bernard the first version
|
||||
*/
|
||||
|
||||
.section .text, "ax"
|
||||
/*
|
||||
* rt_base_t rt_hw_interrupt_disable();
|
||||
*/
|
||||
.globl rt_hw_interrupt_disable
|
||||
rt_hw_interrupt_disable:
|
||||
mrs r0, cpsr
|
||||
cpsid i
|
||||
bx lr
|
||||
|
||||
/*
|
||||
* void rt_hw_interrupt_enable(rt_base_t level);
|
||||
*/
|
||||
.globl rt_hw_interrupt_enable
|
||||
rt_hw_interrupt_enable:
|
||||
msr cpsr_c, r0
|
||||
bx lr
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_to(rt_uint32 to);
|
||||
* r0 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch_to
|
||||
rt_hw_context_switch_to:
|
||||
ldr sp, [r0] @ get new task stack pointer
|
||||
|
||||
ldmfd sp!, {r4} @ pop new task spsr
|
||||
msr spsr_cxsf, r4
|
||||
|
||||
ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc
|
||||
|
||||
.section .bss.share.isr
|
||||
_guest_switch_lvl:
|
||||
.word 0
|
||||
|
||||
.globl vmm_virq_update
|
||||
|
||||
.section .text.isr, "ax"
|
||||
/*
|
||||
* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
|
||||
* r0 --> from
|
||||
* r1 --> to
|
||||
*/
|
||||
.globl rt_hw_context_switch
|
||||
rt_hw_context_switch:
|
||||
stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
|
||||
stmfd sp!, {r0-r12, lr} @ push lr & register file
|
||||
|
||||
mrs r4, cpsr
|
||||
tst lr, #0x01
|
||||
orrne r4, r4, #0x20 @ it's thumb code
|
||||
|
||||
stmfd sp!, {r4} @ push cpsr
|
||||
|
||||
str sp, [r0] @ store sp in preempted tasks TCB
|
||||
ldr sp, [r1] @ get new task stack pointer
|
||||
|
||||
ldmfd sp!, {r4} @ pop new task cpsr to spsr
|
||||
msr spsr_cxsf, r4
|
||||
ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr
|
||||
|
||||
/*
|
||||
* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
|
||||
*/
|
||||
.globl rt_thread_switch_interrupt_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
.globl rt_hw_context_switch_interrupt
|
||||
rt_hw_context_switch_interrupt:
|
||||
ldr r2, =rt_thread_switch_interrupt_flag
|
||||
ldr r3, [r2]
|
||||
cmp r3, #1
|
||||
beq _reswitch
|
||||
ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
|
||||
mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1
|
||||
str r0, [ip]
|
||||
str r3, [r2]
|
||||
_reswitch:
|
||||
ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
|
||||
str r1, [r2]
|
||||
bx lr
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef __CP15_H__
|
||||
#define __CP15_H__
|
||||
|
||||
unsigned long rt_cpu_get_smp_id(void);
|
||||
|
||||
void rt_cpu_mmu_disable(void);
|
||||
void rt_cpu_mmu_enable(void);
|
||||
void rt_cpu_tlb_set(volatile unsigned long*);
|
||||
|
||||
void rt_cpu_vector_set_base(unsigned int addr);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* File : cp15_gcc.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Development Team
|
||||
* http://www.rt-thread.org
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-05 Bernard the first version
|
||||
*/
|
||||
|
||||
.globl rt_cpu_get_smp_id
|
||||
rt_cpu_get_smp_id:
|
||||
mrc p15, #0, r0, c0, c0, #5
|
||||
bx lr
|
||||
|
||||
.globl rt_cpu_vector_set_base
|
||||
rt_cpu_vector_set_base:
|
||||
mcr p15, #0, r0, c12, c0, #0
|
||||
dsb
|
||||
bx lr
|
||||
|
||||
.globl rt_hw_cpu_dcache_enable
|
||||
rt_hw_cpu_dcache_enable:
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #0x00000004
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
bx lr
|
||||
|
||||
.globl rt_hw_cpu_icache_enable
|
||||
rt_hw_cpu_icache_enable:
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #0x00001000
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
bx lr
|
||||
|
||||
_FLD_MAX_WAY:
|
||||
.word 0x3ff
|
||||
_FLD_MAX_IDX:
|
||||
.word 0x7ff
|
||||
|
||||
.globl rt_cpu_dcache_clean_flush
|
||||
rt_cpu_dcache_clean_flush:
|
||||
push {r4-r11}
|
||||
dmb
|
||||
mrc p15, #1, r0, c0, c0, #1 @ read clid register
|
||||
ands r3, r0, #0x7000000 @ get level of coherency
|
||||
mov r3, r3, lsr #23
|
||||
beq finished
|
||||
mov r10, #0
|
||||
loop1:
|
||||
add r2, r10, r10, lsr #1
|
||||
mov r1, r0, lsr r2
|
||||
and r1, r1, #7
|
||||
cmp r1, #2
|
||||
blt skip
|
||||
mcr p15, #2, r10, c0, c0, #0
|
||||
isb
|
||||
mrc p15, #1, r1, c0, c0, #0
|
||||
and r2, r1, #7
|
||||
add r2, r2, #4
|
||||
ldr r4, _FLD_MAX_WAY
|
||||
ands r4, r4, r1, lsr #3
|
||||
clz r5, r4
|
||||
ldr r7, _FLD_MAX_IDX
|
||||
ands r7, r7, r1, lsr #13
|
||||
loop2:
|
||||
mov r9, r4
|
||||
loop3:
|
||||
orr r11, r10, r9, lsl r5
|
||||
orr r11, r11, r7, lsl r2
|
||||
mcr p15, #0, r11, c7, c14, #2
|
||||
subs r9, r9, #1
|
||||
bge loop3
|
||||
subs r7, r7, #1
|
||||
bge loop2
|
||||
skip:
|
||||
add r10, r10, #2
|
||||
cmp r3, r10
|
||||
bgt loop1
|
||||
|
||||
finished:
|
||||
dsb
|
||||
isb
|
||||
pop {r4-r11}
|
||||
bx lr
|
||||
|
||||
.globl rt_hw_cpu_dcache_disable
|
||||
rt_hw_cpu_dcache_disable:
|
||||
push {r4-r11, lr}
|
||||
bl rt_cpu_dcache_clean_flush
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
bic r0, r0, #0x00000004
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
pop {r4-r11, lr}
|
||||
bx lr
|
||||
|
||||
.globl rt_hw_cpu_icache_disable
|
||||
rt_hw_cpu_icache_disable:
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
bic r0, r0, #0x00001000
|
||||
mcr p15, #0, r0, c1, c0, #0
|
||||
bx lr
|
||||
|
||||
.globl rt_cpu_mmu_disable
|
||||
rt_cpu_mmu_disable:
|
||||
mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
bic r0, r0, #1
|
||||
mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit
|
||||
dsb
|
||||
bx lr
|
||||
|
||||
.globl rt_cpu_mmu_enable
|
||||
rt_cpu_mmu_enable:
|
||||
mrc p15, #0, r0, c1, c0, #0
|
||||
orr r0, r0, #0x001
|
||||
mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit
|
||||
dsb
|
||||
bx lr
|
||||
|
||||
.globl rt_cpu_tlb_set
|
||||
rt_cpu_tlb_set:
|
||||
mcr p15, #0, r0, c2, c0, #0
|
||||
dmb
|
||||
bx lr
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/*
|
||||
* File : cpu.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-09-15 Bernard first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/**
|
||||
* @addtogroup AM33xx
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/** shutdown CPU */
|
||||
void rt_hw_cpu_shutdown()
|
||||
{
|
||||
rt_uint32_t level;
|
||||
rt_kprintf("shutdown...\n");
|
||||
|
||||
level = rt_hw_interrupt_disable();
|
||||
while (level)
|
||||
{
|
||||
RT_ASSERT(0);
|
||||
}
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* File : interrupt.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013-2014, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/5/3 Bernard first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "cp15.h"
|
||||
#include <board.h>
|
||||
|
||||
#define MAX_HANDLERS 64
|
||||
|
||||
extern volatile rt_uint8_t rt_interrupt_nest;
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
struct rt_irq_desc isr_table[MAX_HANDLERS];
|
||||
|
||||
rt_uint32_t rt_interrupt_from_thread;
|
||||
rt_uint32_t rt_interrupt_to_thread;
|
||||
rt_uint32_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
extern int system_vectors;
|
||||
|
||||
static void default_isr_handler(int vector, void *param)
|
||||
{
|
||||
rt_kprintf("unhandled irq: %d\n", vector);
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
uint32_t index;
|
||||
|
||||
/* mask all of interrupts */
|
||||
IRQ_DISABLE_BASIC = 0x000000ff;
|
||||
IRQ_DISABLE1 = 0xffffffff;
|
||||
IRQ_DISABLE2 = 0xffffffff;
|
||||
|
||||
for (index = 0; index < MAX_HANDLERS; index ++)
|
||||
{
|
||||
isr_table[index].handler = default_isr_handler;
|
||||
isr_table[index].param = NULL;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_strncpy(isr_table[index].name, "unknown", RT_NAME_MAX);
|
||||
isr_table[index].counter = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* init interrupt nest, and context in thread sp */
|
||||
rt_interrupt_nest = 0;
|
||||
rt_interrupt_from_thread = 0;
|
||||
rt_interrupt_to_thread = 0;
|
||||
rt_thread_switch_interrupt_flag = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
if (vector < 8)
|
||||
{
|
||||
IRQ_DISABLE_BASIC = (1 << vector);
|
||||
}
|
||||
else if (vector < 32)
|
||||
{
|
||||
IRQ_DISABLE1 = (1 << vector);
|
||||
}
|
||||
else
|
||||
{
|
||||
vector = vector % 32;
|
||||
IRQ_DISABLE2 = (1 << vector);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will un-mask a interrupt.
|
||||
* @param vector the interrupt number
|
||||
*/
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
if (vector < 8)
|
||||
{
|
||||
IRQ_ENABLE_BASIC = (1 << vector);
|
||||
}
|
||||
else if (vector < 32)
|
||||
{
|
||||
IRQ_ENABLE1 = (1 << vector);
|
||||
}
|
||||
else
|
||||
{
|
||||
vector = vector % 32;
|
||||
IRQ_ENABLE2 = (1 << vector);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param new_handler the interrupt service routine to be installed
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if (vector < MAX_HANDLERS)
|
||||
{
|
||||
old_handler = isr_table[vector].handler;
|
||||
|
||||
if (handler != RT_NULL)
|
||||
{
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
isr_table[vector].handler = handler;
|
||||
isr_table[vector].param = param;
|
||||
}
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
|
|
@ -0,0 +1,207 @@
|
|||
/*
|
||||
* File : mmu.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2006, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2012-01-10 bernard porting to AM1808
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#include "cp15.h"
|
||||
|
||||
#define DESC_SEC (0x2)
|
||||
#define CB (3<<2) //cache_on, write_back
|
||||
#define CNB (2<<2) //cache_on, write_through
|
||||
#define NCB (1<<2) //cache_off,WR_BUF on
|
||||
#define NCNB (0<<2) //cache_off,WR_BUF off
|
||||
#define AP_RW (3<<10) //supervisor=RW, user=RW
|
||||
#define AP_RO (2<<10) //supervisor=RW, user=RO
|
||||
#define XN (1<<4) // eXecute Never
|
||||
|
||||
#define DOMAIN_FAULT (0x0)
|
||||
#define DOMAIN_CHK (0x1)
|
||||
#define DOMAIN_NOTCHK (0x3)
|
||||
#define DOMAIN0 (0x0<<5)
|
||||
#define DOMAIN1 (0x1<<5)
|
||||
|
||||
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
|
||||
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
|
||||
|
||||
/* Read/Write, cache, write back */
|
||||
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
|
||||
/* Read/Write, cache, write through */
|
||||
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
|
||||
/* Read/Write without cache and write buffer */
|
||||
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
|
||||
/* Read/Write without cache and write buffer, no execute */
|
||||
#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
|
||||
/* Read/Write without cache and write buffer */
|
||||
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
|
||||
|
||||
/* dump 2nd level page table */
|
||||
void rt_hw_cpu_dump_page_table_2nd(rt_uint32_t *ptb)
|
||||
{
|
||||
int i;
|
||||
int fcnt = 0;
|
||||
|
||||
for (i = 0; i < 256; i++)
|
||||
{
|
||||
rt_uint32_t pte2 = ptb[i];
|
||||
if ((pte2 & 0x3) == 0)
|
||||
{
|
||||
if (fcnt == 0)
|
||||
rt_kprintf(" ");
|
||||
rt_kprintf("%04x: ", i);
|
||||
fcnt++;
|
||||
if (fcnt == 16)
|
||||
{
|
||||
rt_kprintf("fault\n");
|
||||
fcnt = 0;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
if (fcnt != 0)
|
||||
{
|
||||
rt_kprintf("fault\n");
|
||||
fcnt = 0;
|
||||
}
|
||||
|
||||
rt_kprintf(" %04x: %x: ", i, pte2);
|
||||
if ((pte2 & 0x3) == 0x1)
|
||||
{
|
||||
rt_kprintf("L,ap:%x,xn:%d,texcb:%02x\n",
|
||||
((pte2 >> 7) | (pte2 >> 4))& 0xf,
|
||||
(pte2 >> 15) & 0x1,
|
||||
((pte2 >> 10) | (pte2 >> 2)) & 0x1f);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("S,ap:%x,xn:%d,texcb:%02x\n",
|
||||
((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1,
|
||||
((pte2 >> 4) | (pte2 >> 2)) & 0x1f);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
|
||||
{
|
||||
int i;
|
||||
int fcnt = 0;
|
||||
|
||||
rt_kprintf("page table@%p\n", ptb);
|
||||
for (i = 0; i < 1024*4; i++)
|
||||
{
|
||||
rt_uint32_t pte1 = ptb[i];
|
||||
if ((pte1 & 0x3) == 0)
|
||||
{
|
||||
rt_kprintf("%03x: ", i);
|
||||
fcnt++;
|
||||
if (fcnt == 16)
|
||||
{
|
||||
rt_kprintf("fault\n");
|
||||
fcnt = 0;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
if (fcnt != 0)
|
||||
{
|
||||
rt_kprintf("fault\n");
|
||||
fcnt = 0;
|
||||
}
|
||||
|
||||
rt_kprintf("%03x: %08x: ", i, pte1);
|
||||
if ((pte1 & 0x3) == 0x3)
|
||||
{
|
||||
rt_kprintf("LPAE\n");
|
||||
}
|
||||
else if ((pte1 & 0x3) == 0x1)
|
||||
{
|
||||
rt_kprintf("pte,ns:%d,domain:%d\n",
|
||||
(pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
|
||||
/*
|
||||
*rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
|
||||
* - 0x80000000 + 0xC0000000));
|
||||
*/
|
||||
}
|
||||
else if (pte1 & (1 << 18))
|
||||
{
|
||||
rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
|
||||
(pte1 >> 19) & 0x1,
|
||||
((pte1 >> 13) | (pte1 >> 10))& 0xf,
|
||||
(pte1 >> 4) & 0x1,
|
||||
((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("section,ns:%d,ap:%x,"
|
||||
"xn:%d,texcb:%02x,domain:%d\n",
|
||||
(pte1 >> 19) & 0x1,
|
||||
((pte1 >> 13) | (pte1 >> 10))& 0xf,
|
||||
(pte1 >> 4) & 0x1,
|
||||
(((pte1 & (0x7 << 12)) >> 10) |
|
||||
((pte1 & 0x0c) >> 2)) & 0x1f,
|
||||
(pte1 >> 5) & 0xf);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* level1 page table, each entry for 1MB memory. */
|
||||
volatile static unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024)));
|
||||
void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
|
||||
rt_uint32_t vaddrEnd,
|
||||
rt_uint32_t paddrStart,
|
||||
rt_uint32_t attr)
|
||||
{
|
||||
volatile rt_uint32_t *pTT;
|
||||
volatile int i, nSec;
|
||||
pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
|
||||
nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
|
||||
for(i = 0; i <= nSec; i++)
|
||||
{
|
||||
*pTT = attr | (((paddrStart >> 20) + i) << 20);
|
||||
pTT++;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned long rt_hw_set_domain_register(unsigned long domain_val)
|
||||
{
|
||||
unsigned long old_domain;
|
||||
|
||||
asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
|
||||
asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
|
||||
|
||||
return old_domain;
|
||||
}
|
||||
|
||||
void rt_hw_mmu_init(void)
|
||||
{
|
||||
rt_hw_cpu_dcache_disable();
|
||||
rt_hw_cpu_icache_disable();
|
||||
rt_cpu_mmu_disable();
|
||||
|
||||
/* set page table */
|
||||
/* 4G 1:1 memory */
|
||||
rt_hw_mmu_setmtt(0, 0xffffffff-1, 0, RW_CB);
|
||||
/* IO memory region */
|
||||
rt_hw_mmu_setmtt(0x44000000, 0x80000000-1, 0x44000000, RW_NCNBXN);
|
||||
|
||||
/*rt_hw_cpu_dump_page_table(MMUTable);*/
|
||||
rt_hw_set_domain_register(0x55555555);
|
||||
|
||||
rt_cpu_tlb_set(MMUTable);
|
||||
|
||||
rt_cpu_mmu_enable();
|
||||
|
||||
rt_hw_cpu_icache_enable();
|
||||
rt_hw_cpu_dcache_enable();
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* File : stack.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2011, RT-Thread Development Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-09-23 Bernard the first version
|
||||
* 2011-10-05 Bernard add thumb mode
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
#include <armv7.h>
|
||||
|
||||
/**
|
||||
* @addtogroup AM33xx
|
||||
*/
|
||||
/*@{*/
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_uint32_t *stk;
|
||||
|
||||
stack_addr += sizeof(rt_uint32_t);
|
||||
stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
|
||||
stk = (rt_uint32_t *)stack_addr;
|
||||
*(--stk) = (rt_uint32_t)tentry; /* entry point */
|
||||
*(--stk) = (rt_uint32_t)texit; /* lr */
|
||||
*(--stk) = 0xdeadbeef; /* r12 */
|
||||
*(--stk) = 0xdeadbeef; /* r11 */
|
||||
*(--stk) = 0xdeadbeef; /* r10 */
|
||||
*(--stk) = 0xdeadbeef; /* r9 */
|
||||
*(--stk) = 0xdeadbeef; /* r8 */
|
||||
*(--stk) = 0xdeadbeef; /* r7 */
|
||||
*(--stk) = 0xdeadbeef; /* r6 */
|
||||
*(--stk) = 0xdeadbeef; /* r5 */
|
||||
*(--stk) = 0xdeadbeef; /* r4 */
|
||||
*(--stk) = 0xdeadbeef; /* r3 */
|
||||
*(--stk) = 0xdeadbeef; /* r2 */
|
||||
*(--stk) = 0xdeadbeef; /* r1 */
|
||||
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
|
||||
|
||||
/* cpsr */
|
||||
if ((rt_uint32_t)tentry & 0x01)
|
||||
*(--stk) = SVCMODE | 0x20; /* thumb mode */
|
||||
else
|
||||
*(--stk) = SVCMODE; /* arm mode */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
|
@ -0,0 +1,279 @@
|
|||
/*
|
||||
* File : start_gcc.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013-2014, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-05 Bernard the first version
|
||||
*/
|
||||
|
||||
.equ Mode_USR, 0x10
|
||||
.equ Mode_FIQ, 0x11
|
||||
.equ Mode_IRQ, 0x12
|
||||
.equ Mode_SVC, 0x13
|
||||
.equ Mode_ABT, 0x17
|
||||
.equ Mode_UND, 0x1B
|
||||
.equ Mode_SYS, 0x1F
|
||||
|
||||
.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
|
||||
.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
|
||||
|
||||
.equ UND_Stack_Size, 0x00000000
|
||||
.equ SVC_Stack_Size, 0x00000100
|
||||
.equ ABT_Stack_Size, 0x00000000
|
||||
.equ RT_FIQ_STACK_PGSZ, 0x00000000
|
||||
.equ RT_IRQ_STACK_PGSZ, 0x00000100
|
||||
.equ USR_Stack_Size, 0x00000100
|
||||
|
||||
#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
|
||||
RT_FIQ_STACK_PGSZ + RT_IRQ_STACK_PGSZ)
|
||||
|
||||
.section .data.share.isr
|
||||
/* stack */
|
||||
.globl stack_start
|
||||
.globl stack_top
|
||||
|
||||
stack_start:
|
||||
.rept ISR_Stack_Size
|
||||
.byte 0
|
||||
.endr
|
||||
stack_top:
|
||||
|
||||
.text
|
||||
/* reset entry */
|
||||
.globl _reset
|
||||
_reset:
|
||||
/* Disable IRQ & FIQ */
|
||||
cpsid if
|
||||
|
||||
/* Check for HYP mode */
|
||||
mrs r0, cpsr_all
|
||||
and r0, r0, #0x1F
|
||||
mov r8, #0x1A
|
||||
cmp r0, r8
|
||||
beq overHyped
|
||||
b continue
|
||||
|
||||
overHyped: /* Get out of HYP mode */
|
||||
ldr r1, =continue
|
||||
msr ELR_hyp, r1
|
||||
mrs r1, cpsr_all
|
||||
and r1, r1, #0x1f ;@ CPSR_MODE_MASK
|
||||
orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR
|
||||
msr SPSR_hyp, r1
|
||||
eret
|
||||
|
||||
continue:
|
||||
|
||||
/* disable smp */
|
||||
bl arm_smp_disable
|
||||
|
||||
/* disable mmu */
|
||||
bl rt_cpu_mmu_disable
|
||||
/* set the cpu to SVC32 mode and disable interrupt */
|
||||
mrs r0, cpsr
|
||||
bic r0, r0, #0x1f
|
||||
orr r0, r0, #0x13
|
||||
msr cpsr_c, r0
|
||||
|
||||
/* setup stack */
|
||||
bl stack_setup
|
||||
|
||||
/* clear .bss */
|
||||
mov r0,#0 /* get a zero */
|
||||
ldr r1,=__bss_start /* bss start */
|
||||
ldr r2,=__bss_end /* bss end */
|
||||
|
||||
bss_loop:
|
||||
cmp r1,r2 /* check if data to clear */
|
||||
strlo r0,[r1],#4 /* clear 4 bytes */
|
||||
blo bss_loop /* loop until done */
|
||||
|
||||
/* start RT-Thread Kernel */
|
||||
ldr pc, _rtthread_startup
|
||||
_rtthread_startup:
|
||||
.word rtthread_startup
|
||||
|
||||
stack_setup:
|
||||
ldr r0, =stack_top
|
||||
|
||||
@ Set the startup stack for svc
|
||||
mov sp, r0
|
||||
sub r0, r0, #SVC_Stack_Size
|
||||
|
||||
@ Enter Undefined Instruction Mode and set its Stack Pointer
|
||||
msr cpsr_c, #Mode_UND|I_Bit|F_Bit
|
||||
mov sp, r0
|
||||
sub r0, r0, #UND_Stack_Size
|
||||
|
||||
@ Enter Abort Mode and set its Stack Pointer
|
||||
msr cpsr_c, #Mode_ABT|I_Bit|F_Bit
|
||||
mov sp, r0
|
||||
sub r0, r0, #ABT_Stack_Size
|
||||
|
||||
@ Enter FIQ Mode and set its Stack Pointer
|
||||
msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit
|
||||
mov sp, r0
|
||||
sub r0, r0, #RT_FIQ_STACK_PGSZ
|
||||
|
||||
@ Enter IRQ Mode and set its Stack Pointer
|
||||
msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit
|
||||
mov sp, r0
|
||||
sub r0, r0, #RT_IRQ_STACK_PGSZ
|
||||
|
||||
/* come back to SVC mode */
|
||||
msr cpsr_c, #Mode_SVC|I_Bit|F_Bit
|
||||
bx lr
|
||||
|
||||
.text
|
||||
;@ void arm_smp_enable(void);
|
||||
.globl arm_smp_enable
|
||||
arm_smp_enable:
|
||||
mrc p15, 0, r0, c1, c0, 1 ;@ set SMP bit in ACTLR
|
||||
orr r0, r0, #0x40
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
bx lr
|
||||
|
||||
.text
|
||||
;@ void arm_smp_disable(void);
|
||||
.globl arm_smp_disable
|
||||
arm_smp_disable:
|
||||
mrc p15, 0, r0, c1, c0, 1 ;@ clear SMP bit in ACTLR
|
||||
bic r0, r0, #0x40
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
bx lr
|
||||
|
||||
/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
|
||||
.section .text.isr, "ax"
|
||||
.align 5
|
||||
.globl vector_fiq
|
||||
vector_fiq:
|
||||
stmfd sp!,{r0-r7,lr}
|
||||
bl rt_hw_trap_fiq
|
||||
ldmfd sp!,{r0-r7,lr}
|
||||
subs pc, lr, #4
|
||||
|
||||
.globl rt_interrupt_enter
|
||||
.globl rt_interrupt_leave
|
||||
.globl rt_thread_switch_interrupt_flag
|
||||
.globl rt_interrupt_from_thread
|
||||
.globl rt_interrupt_to_thread
|
||||
|
||||
.globl rt_current_thread
|
||||
.globl vmm_thread
|
||||
.globl vmm_virq_check
|
||||
|
||||
.align 5
|
||||
.globl vector_irq
|
||||
vector_irq:
|
||||
stmfd sp!, {r0-r12,lr}
|
||||
|
||||
bl rt_interrupt_enter
|
||||
bl rt_hw_trap_irq
|
||||
bl rt_interrupt_leave
|
||||
|
||||
@ if rt_thread_switch_interrupt_flag set, jump to
|
||||
@ rt_hw_context_switch_interrupt_do and don't return
|
||||
ldr r0, =rt_thread_switch_interrupt_flag
|
||||
ldr r1, [r0]
|
||||
cmp r1, #1
|
||||
beq rt_hw_context_switch_interrupt_do
|
||||
|
||||
ldmfd sp!, {r0-r12,lr}
|
||||
subs pc, lr, #4
|
||||
|
||||
rt_hw_context_switch_interrupt_do:
|
||||
mov r1, #0 @ clear flag
|
||||
str r1, [r0]
|
||||
|
||||
mov r1, sp @ r1 point to {r0-r3} in stack
|
||||
add sp, sp, #4*4
|
||||
ldmfd sp!, {r4-r12,lr}@ reload saved registers
|
||||
mrs r0, spsr @ get cpsr of interrupt thread
|
||||
sub r2, lr, #4 @ save old task's pc to r2
|
||||
|
||||
@ Switch to SVC mode with no interrupt. If the usr mode guest is
|
||||
@ interrupted, this will just switch to the stack of kernel space.
|
||||
@ save the registers in kernel space won't trigger data abort.
|
||||
msr cpsr_c, #I_Bit|F_Bit|Mode_SVC
|
||||
|
||||
stmfd sp!, {r2} @ push old task's pc
|
||||
stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4
|
||||
ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread
|
||||
stmfd sp!, {r1-r4} @ push old task's r0-r3
|
||||
stmfd sp!, {r0} @ push old task's cpsr
|
||||
|
||||
ldr r4, =rt_interrupt_from_thread
|
||||
ldr r5, [r4]
|
||||
str sp, [r5] @ store sp in preempted tasks's TCB
|
||||
|
||||
ldr r6, =rt_interrupt_to_thread
|
||||
ldr r6, [r6]
|
||||
ldr sp, [r6] @ get new task's stack pointer
|
||||
|
||||
ldmfd sp!, {r4} @ pop new task's cpsr to spsr
|
||||
msr spsr_cxsf, r4
|
||||
|
||||
ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
|
||||
|
||||
.macro push_svc_reg
|
||||
sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */
|
||||
stmia sp, {r0 - r12} @/* Calling r0-r12 */
|
||||
mov r0, sp
|
||||
mrs r6, spsr @/* Save CPSR */
|
||||
str lr, [r0, #15*4] @/* Push PC */
|
||||
str r6, [r0, #16*4] @/* Push CPSR */
|
||||
cps #Mode_SVC
|
||||
str sp, [r0, #13*4] @/* Save calling SP */
|
||||
str lr, [r0, #14*4] @/* Save calling PC */
|
||||
.endm
|
||||
|
||||
.align 5
|
||||
.globl vector_swi
|
||||
vector_swi:
|
||||
push_svc_reg
|
||||
bl rt_hw_trap_swi
|
||||
b .
|
||||
|
||||
.align 5
|
||||
.globl vector_undef
|
||||
vector_undef:
|
||||
push_svc_reg
|
||||
bl rt_hw_trap_undef
|
||||
b .
|
||||
|
||||
.align 5
|
||||
.globl vector_pabt
|
||||
vector_pabt:
|
||||
push_svc_reg
|
||||
bl rt_hw_trap_pabt
|
||||
b .
|
||||
|
||||
.align 5
|
||||
.globl vector_dabt
|
||||
vector_dabt:
|
||||
push_svc_reg
|
||||
bl rt_hw_trap_dabt
|
||||
b .
|
||||
|
||||
.align 5
|
||||
.globl vector_resv
|
||||
vector_resv:
|
||||
push_svc_reg
|
||||
bl rt_hw_trap_resv
|
||||
b .
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/*
|
||||
* File : trap.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Develop Team
|
||||
*
|
||||
* The license and distribution terms for this file may be
|
||||
* found in the file LICENSE in this distribution or at
|
||||
* http://www.rt-thread.org/license/LICENSE
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-20 Bernard first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "armv7.h"
|
||||
|
||||
extern struct rt_thread *rt_current_thread;
|
||||
#ifdef RT_USING_FINSH
|
||||
extern long list_thread(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* this function will show registers of CPU
|
||||
*
|
||||
* @param regs the registers point
|
||||
*/
|
||||
void rt_hw_show_register(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("Execption:\n");
|
||||
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
|
||||
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
|
||||
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
|
||||
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
|
||||
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
|
||||
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
|
||||
}
|
||||
|
||||
/**
|
||||
* When comes across an instruction which it cannot handle,
|
||||
* it takes the undefined instruction trap.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("undefined instruction:\n");
|
||||
rt_hw_show_register(regs);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* The software interrupt instruction (SWI) is used for entering
|
||||
* Supervisor mode, usually to request a particular supervisor
|
||||
* function.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("software interrupt:\n");
|
||||
rt_hw_show_register(regs);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* An abort indicates that the current memory access cannot be completed,
|
||||
* which occurs during an instruction prefetch.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("prefetch abort:\n");
|
||||
rt_hw_show_register(regs);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* An abort indicates that the current memory access cannot be completed,
|
||||
* which occurs during a data access.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("data abort:");
|
||||
rt_hw_show_register(regs);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
/**
|
||||
* Normally, system will never reach here
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("reserved trap:\n");
|
||||
rt_hw_show_register(regs);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
void rt_hw_trap_irq(void)
|
||||
{
|
||||
void *param;
|
||||
rt_isr_handler_t isr_func;
|
||||
extern struct rt_irq_desc isr_table[];
|
||||
|
||||
uint32_t value = 0;
|
||||
|
||||
// rt_kprintf("pend basic: 0x%08x\n", IRQ_PEND_BASIC);
|
||||
// rt_kprintf(" pend1: 0x%08x\n", IRQ_PEND1);
|
||||
// rt_kprintf(" pend2: 0x%08x\n", IRQ_PEND2);
|
||||
|
||||
value = IRQ_PEND_BASIC & 0x3ff;
|
||||
if (value)
|
||||
{
|
||||
uint32_t irq;
|
||||
|
||||
if (value & (1 << 8))
|
||||
{
|
||||
value = IRQ_PEND1;
|
||||
irq = __rt_ffs(value) - 1;
|
||||
}
|
||||
else if (value & (1 << 9))
|
||||
{
|
||||
value = IRQ_PEND2;
|
||||
irq = __rt_ffs(value) + 31;
|
||||
}
|
||||
else
|
||||
{
|
||||
value &= 0x0f;
|
||||
irq = __rt_ffs(value) - 1;
|
||||
}
|
||||
|
||||
/* get interrupt service routine */
|
||||
isr_func = isr_table[irq].handler;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
isr_table[irq].counter++;
|
||||
#endif
|
||||
if (isr_func)
|
||||
{
|
||||
/* Interrupt for myself. */
|
||||
param = isr_table[irq].param;
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(irq, param);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_trap_fiq(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* File : vector_gcc.S
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2013, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2013-07-05 Bernard the first version
|
||||
*/
|
||||
|
||||
.section .vectors, "ax"
|
||||
.code 32
|
||||
|
||||
.globl system_vectors
|
||||
system_vectors:
|
||||
ldr pc, _vector_reset
|
||||
ldr pc, _vector_undef
|
||||
ldr pc, _vector_swi
|
||||
ldr pc, _vector_pabt
|
||||
ldr pc, _vector_dabt
|
||||
ldr pc, _vector_resv
|
||||
ldr pc, _vector_irq
|
||||
ldr pc, _vector_fiq
|
||||
|
||||
.globl _reset
|
||||
.globl vector_undef
|
||||
.globl vector_swi
|
||||
.globl vector_pabt
|
||||
.globl vector_dabt
|
||||
.globl vector_resv
|
||||
.globl vector_irq
|
||||
.globl vector_fiq
|
||||
|
||||
_vector_reset:
|
||||
.word _reset
|
||||
_vector_undef:
|
||||
.word vector_undef
|
||||
_vector_swi:
|
||||
.word vector_swi
|
||||
_vector_pabt:
|
||||
.word vector_pabt
|
||||
_vector_dabt:
|
||||
.word vector_dabt
|
||||
_vector_resv:
|
||||
.word vector_resv
|
||||
_vector_irq:
|
||||
.word vector_irq
|
||||
_vector_fiq:
|
||||
.word vector_fiq
|
||||
|
||||
.balignl 16,0xdeadbeef
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
config RT_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Split('''
|
||||
board.c
|
||||
drv_uart.c
|
||||
''')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
if GetDepend('RT_USING_PIN'):
|
||||
src += ['drv_gpio.c']
|
||||
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,125 @@
|
|||
#ifndef BCM283X_H__
|
||||
#define BCM283X_H__
|
||||
|
||||
#include <rthw.h>
|
||||
|
||||
#define PER_BASE (0x3F000000)
|
||||
#define PER_BASE_40000000 (0x40000000)
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
#define GPIO_BASE (PER_BASE + 0x200000)
|
||||
#define GPIO_GPFSEL0 HWREG32(GPIO_BASE + 0x00) /* GPIO Function Select 0 32bit R/W */
|
||||
#define GPIO_GPFSEL1 HWREG32(GPIO_BASE + 0x04) /* GPIO Function Select 1 32bit R/W */
|
||||
#define GPIO_GPFSEL2 HWREG32(GPIO_BASE + 0x08) /* GPIO Function Select 2 32bit R/W */
|
||||
#define GPIO_GPFSEL4 HWREG32(GPIO_BASE + 0x10) /* GPIO Function Select 4 32bit R/W */
|
||||
#define GPIO_GPSET0 HWREG32(GPIO_BASE + 0x1C)
|
||||
#define GPIO_GPCLR0 HWREG32(GPIO_BASE + 0x28)
|
||||
#define GPIO_GPPUD HWREG32(GPIO_BASE + 0x94) /* GPIO Pin Pull-up/down Enable */
|
||||
#define GPIO_GPPUDCLK0 HWREG32(GPIO_BASE + 0x98) /* GPIO Pin Pull-up/down Enable Clock 0 */
|
||||
#define GPIO_GPPUDCLK1 HWREG32(GPIO_BASE + 0x9C) /* GPIO Pin Pull-up/down Enable Clock 1 */
|
||||
|
||||
/*
|
||||
* Interrupt Controler
|
||||
*/
|
||||
#define IRQ_BASE (PER_BASE + 0xB200)
|
||||
#define IRQ_PEND_BASIC HWREG32(IRQ_BASE + 0x00)
|
||||
#define IRQ_PEND1 HWREG32(IRQ_BASE + 0x04)
|
||||
#define IRQ_PEND2 HWREG32(IRQ_BASE + 0x08)
|
||||
#define IRQ_FIQ_CONTROL HWREG32(IRQ_BASE + 0x0C)
|
||||
#define IRQ_ENABLE1 HWREG32(IRQ_BASE + 0x10)
|
||||
#define IRQ_ENABLE2 HWREG32(IRQ_BASE + 0x14)
|
||||
#define IRQ_ENABLE_BASIC HWREG32(IRQ_BASE + 0x18)
|
||||
#define IRQ_DISABLE1 HWREG32(IRQ_BASE + 0x1C)
|
||||
#define IRQ_DISABLE2 HWREG32(IRQ_BASE + 0x20)
|
||||
#define IRQ_DISABLE_BASIC HWREG32(IRQ_BASE + 0x24)
|
||||
|
||||
/*
|
||||
* System Timer
|
||||
*/
|
||||
#define STIMER_BASE (PER_BASE + 0x3000)
|
||||
#define STIMER_CS HWREG32(STIMER_BASE + 0x00)
|
||||
#define STIMER_CLO HWREG32(STIMER_BASE + 0x04)
|
||||
#define STIMER_CHI HWREG32(STIMER_BASE + 0x08)
|
||||
#define STIMER_C0 HWREG32(STIMER_BASE + 0x0C)
|
||||
#define STIMER_C1 HWREG32(STIMER_BASE + 0x10)
|
||||
#define STIMER_C2 HWREG32(STIMER_BASE + 0x14)
|
||||
#define STIMER_C3 HWREG32(STIMER_BASE + 0x18)
|
||||
|
||||
/*
|
||||
* ARM Timer
|
||||
*/
|
||||
#define ARM_TIMER_BASE (PER_BASE + 0xB000)
|
||||
|
||||
#define ARM_TIMER_LOAD HWREG32(ARM_TIMER_BASE + 0x400)
|
||||
#define ARM_TIMER_VALUE HWREG32(ARM_TIMER_BASE + 0x404)
|
||||
#define ARM_TIMER_CTRL HWREG32(ARM_TIMER_BASE + 0x408)
|
||||
#define ARM_TIMER_IRQCLR HWREG32(ARM_TIMER_BASE + 0x40C)
|
||||
#define ARM_TIMER_RAWIRQ HWREG32(ARM_TIMER_BASE + 0x410)
|
||||
#define ARM_TIMER_MASKIRQ HWREG32(ARM_TIMER_BASE + 0x414)
|
||||
#define ARM_TIMER_RELOAD HWREG32(ARM_TIMER_BASE + 0x418)
|
||||
#define ARM_TIMER_PREDIV HWREG32(ARM_TIMER_BASE + 0x41C)
|
||||
#define ARM_TIMER_CNTR HWREG32(ARM_TIMER_BASE + 0x420)
|
||||
|
||||
/*
|
||||
* Core Timer
|
||||
*/
|
||||
#define CTIMER_CTL HWREG32(PER_BASE_40000000 + 0x00) /* Control register */
|
||||
#define CTIMER_PRE HWREG32(PER_BASE_40000000 + 0x08) /* Core timer prescaler */
|
||||
#define CTIMER_LS32B HWREG32(PER_BASE_40000000 + 0x1C) /* Core timer access LS 32 bits */
|
||||
#define CTIMER_MS32B HWREG32(PER_BASE_40000000 + 0x20) /* Core timer access MS 32 bits */
|
||||
|
||||
/*
|
||||
* ARM Core Timer
|
||||
*/
|
||||
#define C0TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x40) /* Core0 timers Interrupt control */
|
||||
#define C1TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x44) /* Core1 timers Interrupt control */
|
||||
#define C2TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x48) /* Core2 timers Interrupt control */
|
||||
#define C3TIMER_INTCTL HWREG32(PER_BASE_40000000 + 0x4C) /* Core3 timers Interrupt control */
|
||||
|
||||
/*
|
||||
* ARM Core Mailbox interrupt
|
||||
*/
|
||||
#define C0MB_INTCTL HWREG32(PER_BASE_40000000 + 0x50) /* Core0 Mailboxes Interrupt control */
|
||||
#define C1MB_INTCTL HWREG32(PER_BASE_40000000 + 0x54) /* Core1 Mailboxes Interrupt control */
|
||||
#define C2MB_INTCTL HWREG32(PER_BASE_40000000 + 0x58) /* Core2 Mailboxes Interrupt control */
|
||||
#define C3MB_INTCTL HWREG32(PER_BASE_40000000 + 0x5C) /* Core3 Mailboxes Interrupt control */
|
||||
|
||||
/*
|
||||
* ARM Core IRQ/FIQ status
|
||||
*/
|
||||
#define C0_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x60) /* Core0 IRQ Source */
|
||||
#define C1_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x64) /* Core1 IRQ Source */
|
||||
#define C2_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x68) /* Core2 IRQ Source */
|
||||
#define C3_IRQSOURCE HWREG32(PER_BASE_40000000 + 0x6C) /* Core3 IRQ Source */
|
||||
#define C0_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x70) /* Core0 FIQ Source */
|
||||
#define C1_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x74) /* Core1 FIQ Source */
|
||||
#define C2_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x78) /* Core2 FIQ Source */
|
||||
#define C3_FIQSOURCE HWREG32(PER_BASE_40000000 + 0x7C) /* Core3 FIQ Source */
|
||||
|
||||
#define IRQ_ARM_TIMER 0
|
||||
#define IRQ_ARM_MAILBOX 1
|
||||
#define IRQ_ARM_DB0 2
|
||||
#define IRQ_ARM_DB1 3
|
||||
#define IRQ_ARM_GPU0_HALT 4
|
||||
#define IRQ_ARM_GPU1_HALT 5
|
||||
#define IRQ_ARM_ILLEGAL_ACC1 6
|
||||
#define IRQ_ARM_ILLEGAL_ACC0 7
|
||||
|
||||
#define IRQ_AUX 29
|
||||
#define IRQ_IIC_SPI_SLV 43
|
||||
#define IRQ_PWA0 45
|
||||
#define IRQ_PWA1 46
|
||||
#define IRQ_SMI 48
|
||||
#define IRQ_GPIO0 49
|
||||
#define IRQ_GPIO1 50
|
||||
#define IRQ_GPIO2 51
|
||||
#define IRQ_GPIO3 52
|
||||
#define IRQ_IIC 53
|
||||
#define IRQ_SPI 54
|
||||
#define IRQ_PCM 55
|
||||
#define IRQ_UART 57
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* File : board.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
|
||||
void rt_hw_timer_isr(int vector, void *parameter)
|
||||
{
|
||||
ARM_TIMER_IRQCLR = 0;
|
||||
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
int rt_hw_timer_init(void)
|
||||
{
|
||||
/* timer_clock = apb_clock/(pre_divider + 1) */
|
||||
ARM_TIMER_PREDIV = (250 - 1);
|
||||
|
||||
ARM_TIMER_RELOAD = 0;
|
||||
ARM_TIMER_LOAD = 0;
|
||||
ARM_TIMER_IRQCLR = 0;
|
||||
ARM_TIMER_CTRL = 0;
|
||||
|
||||
ARM_TIMER_RELOAD = 10000;
|
||||
ARM_TIMER_LOAD = 10000;
|
||||
|
||||
/* 23-bit counter, enable interrupt, enable timer */
|
||||
ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
|
||||
|
||||
rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
|
||||
rt_hw_interrupt_umask(IRQ_ARM_TIMER);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void vector_copy(void)
|
||||
{
|
||||
rt_memcpy((void*)0x0, (void*)0x8000, 64);
|
||||
}
|
||||
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
/* initialize hardware interrupt */
|
||||
rt_hw_interrupt_init();
|
||||
vector_copy();
|
||||
|
||||
/* initialize uart */
|
||||
rt_hw_uart_init();
|
||||
|
||||
#ifdef RT_USING_CONSOLE
|
||||
/* set console device */
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif /* RT_USING_CONSOLE */
|
||||
|
||||
#ifdef RT_USING_HEAP
|
||||
/* initialize memory system */
|
||||
rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
#endif
|
||||
|
||||
/* initialize timer for os tick */
|
||||
// rt_hw_timer_init();
|
||||
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* File : board.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-5-30 Bernard the first version
|
||||
*/
|
||||
|
||||
#ifndef BOARD_H__
|
||||
#define BOARD_H__
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <rthw.h>
|
||||
#include <bcm283x.h>
|
||||
|
||||
extern unsigned char __bss_start;
|
||||
extern unsigned char __bss_end;
|
||||
|
||||
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
|
||||
#define RT_HW_HEAP_END (void*)(0x0 + 4 * 1024 * 1024)
|
||||
|
||||
void rt_hw_board_init(void);
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* File : drv_uart.c
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018/5/5 Bernard The first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
|
||||
#include <rtdevice.h>
|
||||
|
||||
#define AUX_BASE (0x3F000000 + 0x215000)
|
||||
|
||||
struct hw_uart_device
|
||||
{
|
||||
rt_uint32_t hw_base;
|
||||
rt_uint32_t irqno;
|
||||
};
|
||||
|
||||
static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct hw_uart_device *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
if (uart->hw_base == AUX_BASE)
|
||||
{
|
||||
uint32_t value;
|
||||
|
||||
/* GPIO function set */
|
||||
value = GPIO_GPFSEL1;
|
||||
value &= ~(7<<12); /* GPIO14 */
|
||||
value |= 2<<12 ; /* ALT5 */
|
||||
value &= ~(7<<15); /* GPIO15 */
|
||||
value |= 2<<15 ; /* ALT5 */
|
||||
GPIO_GPFSEL1 = value;
|
||||
|
||||
/* PullUD disable */
|
||||
GPIO_GPPUD = 0;
|
||||
GPIO_GPPUDCLK0 = (1 << 14) | (1 << 15);
|
||||
GPIO_GPPUDCLK0 = 0;
|
||||
|
||||
AUX_ENABLES(uart->hw_base) = 1; /* Enable UART1 */
|
||||
AUX_MU_IER_REG(uart->hw_base) = 0; /* Disable interrupt */
|
||||
AUX_MU_CNTL_REG(uart->hw_base) = 0; /* Disable Transmitter and Receiver */
|
||||
AUX_MU_LCR_REG(uart->hw_base) = 3; /* Works in 8-bit mode */
|
||||
AUX_MU_MCR_REG(uart->hw_base) = 0; /* Disable RTS */
|
||||
AUX_MU_IIR_REG(uart->hw_base) = 0xC6; /* Enable FIFO, Clear FIFO */
|
||||
AUX_MU_BAUD_REG(uart->hw_base) = 270; /* 115200 = system clock 250MHz / (8 * (baud + 1)), baud = 270 */
|
||||
AUX_MU_CNTL_REG(uart->hw_base) = 3; /* Enable Transmitter and Receiver */
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct hw_uart_device *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
AUX_MU_IER_REG(uart->hw_base) = 0x0;
|
||||
rt_hw_interrupt_mask(uart->irqno);
|
||||
break;
|
||||
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
AUX_MU_IER_REG(uart->hw_base) = 0x1;
|
||||
rt_hw_interrupt_umask(uart->irqno);
|
||||
break;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static int uart_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct hw_uart_device *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
while (!(AUX_MU_LSR_REG(uart->hw_base) & 0x20));
|
||||
AUX_MU_IO_REG(uart->hw_base) = c;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int uart_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
int ch = -1;
|
||||
struct hw_uart_device *uart;
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = (struct hw_uart_device *)serial->parent.user_data;
|
||||
|
||||
if ((AUX_MU_LSR_REG(uart->hw_base) & 0x01))
|
||||
{
|
||||
ch = AUX_MU_IO_REG(uart->hw_base) & 0xff;
|
||||
}
|
||||
|
||||
return ch;
|
||||
}
|
||||
|
||||
static const struct rt_uart_ops _uart_ops =
|
||||
{
|
||||
uart_configure,
|
||||
uart_control,
|
||||
uart_putc,
|
||||
uart_getc,
|
||||
};
|
||||
|
||||
static void rt_hw_uart_isr(int irqno, void *param)
|
||||
{
|
||||
struct rt_serial_device *serial = (struct rt_serial_device*)param;
|
||||
|
||||
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||
}
|
||||
|
||||
#ifdef RT_USING_UART0
|
||||
/* UART device driver structure */
|
||||
static struct hw_uart_device _uart0_device =
|
||||
{
|
||||
RPI_UART0_BASE,
|
||||
IRQ_PBA8_UART0,
|
||||
};
|
||||
static struct rt_serial_device _serial0;
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART1
|
||||
/* UART1 device driver structure */
|
||||
static struct hw_uart_device _uart1_device =
|
||||
{
|
||||
AUX_BASE,
|
||||
IRQ_AUX,
|
||||
};
|
||||
static struct rt_serial_device _serial1;
|
||||
#endif
|
||||
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
struct hw_uart_device *uart;
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
|
||||
#ifdef RT_USING_UART0
|
||||
uart = &_uart0_device;
|
||||
|
||||
_serial0.ops = &_uart_ops;
|
||||
_serial0.config = config;
|
||||
|
||||
/* register UART1 device */
|
||||
rt_hw_serial_register(&_serial0, "uart0",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
|
||||
uart);
|
||||
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart0");
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_UART1
|
||||
uart = &_uart1_device;
|
||||
_serial1.ops = &_uart_ops;
|
||||
_serial1.config = config;
|
||||
|
||||
/* register UART1 device */
|
||||
rt_hw_serial_register(&_serial1, "uart1",
|
||||
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, uart);
|
||||
/* enable Rx and Tx of UART */
|
||||
rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial1, "uart1");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* File : drv_uart.h
|
||||
* This file is part of RT-Thread RTOS
|
||||
* COPYRIGHT (C) 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2017-5-30 Bernard the first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef DRV_UART_H__
|
||||
#define DRV_UART_H__
|
||||
|
||||
/*
|
||||
* Auxiliary
|
||||
*/
|
||||
#define AUX_IRQ(BASE) HWREG32(BASE + 0x00) /* Auxiliary Interrupt status 3 */
|
||||
#define AUX_ENABLES(BASE) HWREG32(BASE + 0x04) /* Auxiliary enables 3bit */
|
||||
#define AUX_MU_IO_REG(BASE) HWREG32(BASE + 0x40) /* Mini Uart I/O Data 8bit */
|
||||
#define AUX_MU_IER_REG(BASE) HWREG32(BASE + 0x44) /* Mini Uart Interrupt Enable 8bit */
|
||||
#define AUX_MU_IIR_REG(BASE) HWREG32(BASE + 0x48) /* Mini Uart Interrupt Identify 8bit */
|
||||
#define AUX_MU_LCR_REG(BASE) HWREG32(BASE + 0x4C) /* Mini Uart Line Control 8bit */
|
||||
#define AUX_MU_MCR_REG(BASE) HWREG32(BASE + 0x50) /* Mini Uart Modem Control 8bit */
|
||||
#define AUX_MU_LSR_REG(BASE) HWREG32(BASE + 0x54) /* Mini Uart Line Status 8bit */
|
||||
#define AUX_MU_MSR_REG(BASE) HWREG32(BASE + 0x58) /* Mini Uart Modem Status 8bit */
|
||||
#define AUX_MU_SCRATCH(BASE) HWREG32(BASE + 0x5C) /* Mini Uart Scratch 8bit */
|
||||
#define AUX_MU_CNTL_REG(BASE) HWREG32(BASE + 0x60) /* Mini Uart Extra Control 8bit */
|
||||
#define AUX_MU_STAT_REG(BASE) HWREG32(BASE + 0x64) /* Mini Uart Extra Status 32bit */
|
||||
#define AUX_MU_BAUD_REG(BASE) HWREG32(BASE + 0x68) /* Mini Uart Baudrate 16bit */
|
||||
#define AUX_SPI0_CNTL0_REG(BASE) HWREG32(BASE + 0x80) /* SPI 1 Control register 0 32bit */
|
||||
#define AUX_SPI0_CNTL1_REG(BASE) HWREG32(BASE + 0x84) /* SPI 1 Control register 1 8bit */
|
||||
#define AUX_SPI0_STAT_REG(BASE) HWREG32(BASE + 0x88) /* SPI 1 Status 32bit */
|
||||
#define AUX_SPI0_IO_REG(BASE) HWREG32(BASE + 0x90) /* SPI 1 Data 32bit */
|
||||
#define AUX_SPI0_PEEK_REG(BASE) HWREG32(BASE + 0x94) /* SPI 1 Peek 16bit */
|
||||
#define AUX_SPI1_CNTL0_REG(BASE) HWREG32(BASE + 0xC0) /* SPI 2 Control register 0 32bit */
|
||||
#define AUX_SPI1_CNTL1_REG(BASE) HWREG32(BASE + 0xC4) /* SPI 2 Control register 1 8bit */
|
||||
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
#endif /* DRV_UART_H__ */
|
||||
|
||||
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* File : link.lds
|
||||
* COPYRIGHT (C) 2017, RT-Thread Development Team
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*
|
||||
* Change Logs:
|
||||
* 2017-5-30 bernard first version
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00008000;
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.vectors)
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
}
|
||||
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame_entry)
|
||||
}
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
|
||||
*(.data1)
|
||||
*(.data1.*)
|
||||
|
||||
. = ALIGN(8);
|
||||
_gp = ABSOLUTE(.); /* Base of small data */
|
||||
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.ctors :
|
||||
{
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*(.ctors))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
}
|
||||
|
||||
.dtors :
|
||||
{
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
PROVIDE(__bss_start = .);
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(.dynbss)
|
||||
*(COMMON)
|
||||
PROVIDE(__bss_end = .);
|
||||
}
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Project Configuration */
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
/* RT_THREAD_PRIORITY_8 is not set */
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
/* RT_THREAD_PRIORITY_256 is not set */
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 100
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_IDEL_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
/* RT_USING_TIMER_SOFT is not set */
|
||||
#define RT_DEBUG
|
||||
/* RT_DEBUG_INIT_CONFIG is not set */
|
||||
/* RT_DEBUG_THREAD_CONFIG is not set */
|
||||
/* RT_DEBUG_SCHEDULER_CONFIG is not set */
|
||||
/* RT_DEBUG_IPC_CONFIG is not set */
|
||||
/* RT_DEBUG_TIMER_CONFIG is not set */
|
||||
/* RT_DEBUG_IRQ_CONFIG is not set */
|
||||
/* RT_DEBUG_MEM_CONFIG is not set */
|
||||
/* RT_DEBUG_SLAB_CONFIG is not set */
|
||||
/* RT_DEBUG_MEMHEAP_CONFIG is not set */
|
||||
/* RT_DEBUG_MODULE_CONFIG is not set */
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
/* RT_USING_SIGNALS is not set */
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
/* RT_USING_MEMHEAP is not set */
|
||||
/* RT_USING_NOHEAP is not set */
|
||||
#define RT_USING_SMALL_MEM
|
||||
/* RT_USING_SLAB is not set */
|
||||
/* RT_USING_MEMTRACE is not set */
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
/* RT_USING_DEVICE_OPS is not set */
|
||||
/* RT_USING_INTERRUPT_INFO is not set */
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 128
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
/* RT_USING_MODULE is not set */
|
||||
#define ARCH_ARM
|
||||
#define ARCH_ARM_CORTEX_A
|
||||
#define ARCH_ARM_CORTEX_A7
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
|
||||
/* RT_USING_CPLUSPLUS is not set */
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
/* FINSH_ECHO_DISABLE_DEFAULT is not set */
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_CMD_SIZE 80
|
||||
/* FINSH_USING_AUTH is not set */
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_USING_MSH_DEFAULT
|
||||
#define FINSH_USING_MSH_ONLY
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
||||
/* RT_USING_DFS is not set */
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
/* RT_USING_CAN is not set */
|
||||
/* RT_USING_HWTIMER is not set */
|
||||
/* RT_USING_CPUTIME is not set */
|
||||
/* RT_USING_I2C is not set */
|
||||
/* RT_USING_PIN is not set */
|
||||
/* RT_USING_PWM is not set */
|
||||
/* RT_USING_MTD_NOR is not set */
|
||||
/* RT_USING_MTD_NAND is not set */
|
||||
/* RT_USING_RTC is not set */
|
||||
/* RT_USING_SDIO is not set */
|
||||
/* RT_USING_SPI is not set */
|
||||
/* RT_USING_WDT is not set */
|
||||
/* RT_USING_WIFI is not set */
|
||||
/* RT_USING_AUDIO is not set */
|
||||
|
||||
/* Using USB */
|
||||
|
||||
/* RT_USING_USB_HOST is not set */
|
||||
/* RT_USING_USB_DEVICE is not set */
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
/* RT_USING_LIBC is not set */
|
||||
/* RT_USING_PTHREADS is not set */
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
/* RT_USING_SAL is not set */
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
/* RT_USING_LWIP is not set */
|
||||
|
||||
/* Modbus master and slave stack */
|
||||
|
||||
/* RT_USING_MODBUS is not set */
|
||||
|
||||
/* AT commands */
|
||||
|
||||
/* RT_USING_AT is not set */
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
/* RT_USING_VBUS is not set */
|
||||
|
||||
/* Utilities */
|
||||
|
||||
/* RT_USING_LOGTRACE is not set */
|
||||
/* RT_USING_RYM is not set */
|
||||
|
||||
/* RT-Thread online packages */
|
||||
|
||||
/* IoT - internet of things */
|
||||
|
||||
/* PKG_USING_PAHOMQTT is not set */
|
||||
/* PKG_USING_WEBCLIENT is not set */
|
||||
/* PKG_USING_MONGOOSE is not set */
|
||||
/* PKG_USING_WEBTERMINAL is not set */
|
||||
/* PKG_USING_CJSON is not set */
|
||||
/* PKG_USING_JSMN is not set */
|
||||
/* PKG_USING_LJSON is not set */
|
||||
/* PKG_USING_EZXML is not set */
|
||||
/* PKG_USING_NANOPB is not set */
|
||||
|
||||
/* Wi-Fi */
|
||||
|
||||
/* Marvell WiFi */
|
||||
|
||||
/* PKG_USING_WLANMARVELL is not set */
|
||||
|
||||
/* Wiced WiFi */
|
||||
|
||||
/* PKG_USING_WLAN_WICED is not set */
|
||||
/* PKG_USING_COAP is not set */
|
||||
/* PKG_USING_NOPOLL is not set */
|
||||
/* PKG_USING_NETUTILS is not set */
|
||||
/* PKG_USING_AT_DEVICE is not set */
|
||||
|
||||
/* IoT Cloud */
|
||||
|
||||
/* PKG_USING_ONENET is not set */
|
||||
/* PKG_USING_GAGENT_CLOUD is not set */
|
||||
/* PKG_USING_ALI_IOTKIT is not set */
|
||||
/* PKG_USING_AZURE is not set */
|
||||
|
||||
/* security packages */
|
||||
|
||||
/* PKG_USING_MBEDTLS is not set */
|
||||
/* PKG_USING_libsodium is not set */
|
||||
/* PKG_USING_TINYCRYPT is not set */
|
||||
|
||||
/* language packages */
|
||||
|
||||
/* PKG_USING_LUA is not set */
|
||||
/* PKG_USING_JERRYSCRIPT is not set */
|
||||
/* PKG_USING_MICROPYTHON is not set */
|
||||
|
||||
/* multimedia packages */
|
||||
|
||||
/* PKG_USING_OPENMV is not set */
|
||||
/* PKG_USING_MUPDF is not set */
|
||||
|
||||
/* tools packages */
|
||||
|
||||
/* PKG_USING_CMBACKTRACE is not set */
|
||||
/* PKG_USING_EASYFLASH is not set */
|
||||
/* PKG_USING_EASYLOGGER is not set */
|
||||
/* PKG_USING_SYSTEMVIEW is not set */
|
||||
|
||||
/* system packages */
|
||||
|
||||
/* PKG_USING_GUIENGINE is not set */
|
||||
/* PKG_USING_PERSIMMON is not set */
|
||||
/* PKG_USING_CAIRO is not set */
|
||||
/* PKG_USING_PIXMAN is not set */
|
||||
/* PKG_USING_LWEXT4 is not set */
|
||||
/* PKG_USING_PARTITION is not set */
|
||||
/* PKG_USING_FAL is not set */
|
||||
/* PKG_USING_SQLITE is not set */
|
||||
/* PKG_USING_RTI is not set */
|
||||
/* PKG_USING_LITTLEVGL2RTT is not set */
|
||||
|
||||
/* peripheral libraries and drivers */
|
||||
|
||||
/* PKG_USING_STM32F4_HAL is not set */
|
||||
/* PKG_USING_STM32F4_DRIVERS is not set */
|
||||
/* PKG_USING_REALTEK_AMEBA is not set */
|
||||
/* PKG_USING_SHT2X is not set */
|
||||
/* PKG_USING_AHT10 is not set */
|
||||
|
||||
/* miscellaneous packages */
|
||||
|
||||
/* PKG_USING_LIBCSV is not set */
|
||||
/* PKG_USING_OPTPARSE is not set */
|
||||
/* PKG_USING_FASTLZ is not set */
|
||||
/* PKG_USING_MINILZO is not set */
|
||||
/* PKG_USING_QUICKLZ is not set */
|
||||
/* PKG_USING_MULTIBUTTON is not set */
|
||||
/* PKG_USING_CANFESTIVAL is not set */
|
||||
/* PKG_USING_ZLIB is not set */
|
||||
/* PKG_USING_DSTR is not set */
|
||||
|
||||
/* sample package */
|
||||
|
||||
/* PKG_USING_SAMPLES is not set */
|
||||
|
||||
/* example package: hello */
|
||||
|
||||
/* PKG_USING_HELLO is not set */
|
||||
#define BCM2836_SOC
|
||||
#define RT_USING_UART1
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
import os
|
||||
|
||||
# toolchains options
|
||||
ARCH ='arm'
|
||||
CPU ='cortex-a7'
|
||||
CROSS_TOOL ='gcc'
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = r'../..'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'/opt/gcc-arm-none-eabi-4_8-2014q1_gri/bin'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mfpu=neon-vfpv4 -mfloat-abi=softfp -march=armv7-a -mtune=cortex-a7 -ftree-vectorize -ffast-math'
|
||||
CFLAGS = DEVICE + ' -Wall'
|
||||
AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
|
||||
LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET kernel7.img\n' + SIZE + ' $TARGET \n'
|
||||
Loading…
Reference in New Issue