diff --git a/bsp/raspberry-pi/raspi4-32/driver/board.c b/bsp/raspberry-pi/raspi4-32/driver/board.c index 01b3a79882..455bd28ee2 100644 --- a/bsp/raspberry-pi/raspi4-32/driver/board.c +++ b/bsp/raspberry-pi/raspi4-32/driver/board.c @@ -24,7 +24,7 @@ struct mem_desc platform_mem_desc[] = { {0x0E000000, 0x0EE00000, 0x0E000000, DEVICE_MEM}, //framebuffer {0x0F400000, 0x0FA00000, 0x0F400000, DEVICE_MEM}, //dsi_touch {0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac - {0xFE000000, 0xFEA00000, 0xFE000000, DEVICE_MEM}, //peripheral + {0xFE000000, 0xFF000000, 0xFE000000, DEVICE_MEM}, //peripheral {0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic }; diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c new file mode 100644 index 0000000000..353a6f30ec --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-02 bigmagic first version + */ +#include "drv_dma.h" +#include "raspi4.h" + +volatile unsigned int __attribute__((aligned(256))) dma_disc[32]; +//https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=10276 +static struct rt_semaphore dma_sem; + +//DMA 0 1 2 3 4 5 6 +typedef struct _dma_ctrl_block +{ + unsigned int TI; // Transfer information + unsigned int SOURCE_AD; // source address + unsigned int DEST_AD; // destination address + unsigned int TXFR_LEN; // transfer length + unsigned int STRIDE; // 2D mode stride + struct _dma_ctrl_block *NEXTCONBK; // Next control block address + unsigned int DEBUG; + unsigned int reserved1; + +} dma_ctrl_block_t; + +//DMA 7 8 9 10 +typedef struct _dma_lite_ctrl_block +{ + unsigned int TI; // Transfer information + unsigned int SOURCE_AD; // source address + unsigned int DEST_AD; // destination address + unsigned int TXFR_LEN; // transfer length + struct _dma_lite_ctrl_block *NEXTCONBK; // Next control block address + unsigned int DEBUG; + unsigned int reserved1; + unsigned int reserved2; + +} dma_lite_ctrl_block_t; + +//DMA 11 12 13 14 15 +typedef struct _dma4_ctrl_block +{ + unsigned int TI; // Transfer information + unsigned int SOURCE_AD0; // source address0 + unsigned int SOURCE_AD1; // source address1 + unsigned int DEST_AD0; // destination address0 + unsigned int DEST_AD1; // destination address1 + unsigned int TXFR_LEN; // transfer length + unsigned int STRIDE; // 2D mode stride + struct _dma4_ctrl_block *NEXTCONBK; // Next control block address +} dma4_ctrl_block_t; + +static dma_lite_ctrl_block_t *ctr_blocks; + +static void dma_irq(int irq, void *param) +{ + if (DMA_INT_STATUS_REG & DMA_INT7) + { + DMA_CS(7) = DMA_CS_INT; + rt_sem_release(&dma_sem); + } +} + +//dma 7 8 9 10:XLENGTH +rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout) +{ + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, dst, size); + + /* Stop DMA, if it was already started */ + DMA_CS(dch) = DMA_CS_RESET; + + /* Clear DMA status flags */ + DMA_CS(dch) = DMA_CS_INT | DMA_CS_END; /* Interrupted flag & Transmission ended flag*/ + //cb info + ctr_blocks->TI = DMA_TI_SRC_INC | DMA_TI_DEST_INC | DMA_TI_INTEN; + ctr_blocks->SOURCE_AD = (unsigned int)src; + ctr_blocks->DEST_AD = (unsigned int)dst; + ctr_blocks->TXFR_LEN = size; + ctr_blocks->NEXTCONBK = 0; + ctr_blocks->reserved1 = 0; + ctr_blocks->reserved2 = 0; + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, ctr_blocks, sizeof(dma_lite_ctrl_block_t) * 8); + + DMA_CONBLK_AD(dch) = (rt_uint32_t)ctr_blocks; + DMA_CS(dch) = DMA_CS_INT | DMA_CS_END | DMA_CS_ACTIVE; + + if(rt_sem_take(&dma_sem, timeout) != RT_EOK) + { + rt_kprintf("dma transfer timeout!\n"); + return RT_ERROR; + } + + return RT_EOK; +} + +void dma_init(rt_uint8_t dch) +{ + rt_sem_init(&dma_sem, "dma_sem", 0, RT_IPC_FLAG_FIFO); + + ctr_blocks = (dma_lite_ctrl_block_t *)&dma_disc[0]; //rt_malloc(sizeof(DMA_Lite_Control_Block)); + //Make sure DMA channel is enabled by + //writing the corresponding bit in DMA_ENABLE in the DMA register to 1 + DMA_ENABLE_REG = (1 << dch); + + rt_hw_interrupt_install(IRQ_DMA7_DMA8, dma_irq, RT_NULL, "dma_irq"); + rt_hw_interrupt_umask(IRQ_DMA7_DMA8); +} diff --git a/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h new file mode 100644 index 0000000000..99152167d5 --- /dev/null +++ b/bsp/raspberry-pi/raspi4-32/driver/drv_dma.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-12-02 bigmagic first version + */ +#ifndef __DRV_DMA_H__ +#define __DRV_DMA_H__ + +#include + +#define DMA_PER_BASE (0xFE000000) + +//DMA +#define DMA_BASE (DMA_PER_BASE+0x7000) +#define DMA_INT_STATUS (DMA_BASE + 0xFE0) //Interrupt Status of each DMA Channel +#define DMA_ENABLE (DMA_BASE + 0xFF0) //Global Enable bits for each DMA Channel */ +#define DMA15_BASE (DMA_PER_BASE+0xE05000) //DMA Channel 15 Register Set */ + + +#define DMA_INT_STATUS_REG __REG32(DMA_INT_STATUS) +#define DMA_ENABLE_REG __REG32(DMA_ENABLE) +//DMA dch 1~14 +#define DMA_CS(dch) __REG32(DMA_BASE + dch*0x100 + 0x000) /* Control and Status */ +#define DMA_CONBLK_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x004) /* Control Block Address */ +#define DMA_TI(dch) __REG32(DMA_BASE + dch*0x100 + 0x008) /* CB Word 0(Transfer Information) */ +#define DMA_SOURCE_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x00c) /* CB Word 1(Source Address) */ +#define DMA_DEST_AD(dch) __REG32(DMA_BASE + dch*0x100 + 0x010) /* CB Word 2(Destination Address) */ +#define DMA_TXFR_LEN(dch) __REG32(DMA_BASE + dch*0x100 + 0x014) /* CB Word 3(Transfer Length) */ +#define DMA_STRIDE(dch) __REG32(DMA_BASE + dch*0x100 + 0x018) /* CB Word 4(2D Stride) */ +#define DMA_NEXTCONBK(dch) __REG32(DMA_BASE + dch*0x100 + 0x01c) /* CB Word 5(Next CB Address) */ +#define DMA_DEBUG(dch) __REG32(DMA_BASE + dch*0x100 + 0x01c) /* Debug */ + +//DMA dch 15 +#define DMA15_CS __REG32(DMA15_BASE + 0x000) /* Control and Status */ +#define DMA15_CONBLK_AD __REG32(DMA15_BASE + 0x004) /* Control Block Address */ +#define DMA15_TI __REG32(DMA15_BASE + 0x008) /* CB Word 0(Transfer Information) */ +#define DMA15_SOURCE_AD __REG32(DMA15_BASE + 0x00c) /* CB Word 1(Source Address) */ +#define DMA15_DEST_AD __REG32(DMA15_BASE + 0x010) /* CB Word 2(Destination Address) */ +#define DMA15_TXFR_LEN __REG32(DMA15_BASE + 0x014) /* CB Word 3(Transfer Length) */ +#define DMA15_STRIDE __REG32(DMA15_BASE + 0x018) /* CB Word 4(2D Stride) */ +#define DMA15_NEXTCONBK __REG32(DMA15_BASE + 0x01c) /* CB Word 5(Next CB Address) */ +#define DMA15_DEBUG __REG32(DMA15_BASE + 0x01c) /* Debug */ + +#define DMA15_ENABLE (1 << 15) +#define DMA14_ENABLE (1 << 14) +#define DMA13_ENABLE (1 << 13) +#define DMA12_ENABLE (1 << 12) +#define DMA11_ENABLE (1 << 11) +#define DMA10_ENABLE (1 << 10) +#define DMA9_ENABLE (1 << 9) +#define DMA8_ENABLE (1 << 8) +#define DMA7_ENABLE (1 << 7) +#define DMA6_ENABLE (1 << 6) +#define DMA5_ENABLE (1 << 5) +#define DMA4_ENABLE (1 << 4) +#define DMA3_ENABLE (1 << 3) +#define DMA2_ENABLE (1 << 2) +#define DMA1_ENABLE (1 << 1) +#define DMA0_ENABLE (1 << 0) + +//Peripheral DREQ Signals +#define DREQ_DSI0_PWM1 (1) +#define DREQ_PCM_TX (2) +#define DREQ_PCM_RX (3) +#define DREQ_SMI (4) +#define DREQ_PWM0 (5) +#define DREQ_SPI0_TX (6) +#define DREQ_SPI0_RX (7) +#define DREQ_BSC_SPI_SLAVE_TX (8) +#define DREQ_BSC_SPI_SLAVE_RX (9) +#define DREQ_HSMI0 (10) +#define DREQ_EMMC (11) +#define DREQ_UART0_TX (12) +#define DREQ_SD_HOST (13) +#define DREQ_UART0_RX (14) +#define DREQ_DSI1 (15) +#define DREQ_SPI1_TX (16) +#define DREQ_HDMI1 (17) +#define DREQ_SPI1_RX (18) +#define DREQ_UART3_TX_SPI4_TX (19) +#define DREQ_UART3_RX_SPI4_RX (20) +#define DREQ_UART5_TX_SPI5_TX (21) +#define DREQ_UART5_RX_SPI5_RX (22) +#define DREQ_SPI6_TX (23) +#define DREQ_SCALER_FIFO0_SMI (24) +#define DREQ_SCALER_FIFO1_SMI (25) +#define DREQ_SCALER_FIFO2_SMI (26) +#define DREQ_SPI6_RX (27) +#define DREQ_UART2_TX (28) +#define DREQ_UART2_RX (29) +#define DREQ_UART4_TX (30) +#define DREQ_UART4_RX (31) + +//IRQ +#define DMA_INT15 (1 << 15) +#define DMA_INT14 (1 << 14) +#define DMA_INT13 (1 << 13) +#define DMA_INT12 (1 << 12) +#define DMA_INT11 (1 << 11) +#define DMA_INT10 (1 << 10) +#define DMA_INT9 (1 << 9) +#define DMA_INT8 (1 << 8) +#define DMA_INT7 (1 << 7) +#define DMA_INT6 (1 << 6) +#define DMA_INT5 (1 << 5) +#define DMA_INT4 (1 << 4) +#define DMA_INT3 (1 << 3) +#define DMA_INT2 (1 << 2) +#define DMA_INT1 (1 << 1) +#define DMA_INT0 (1 << 0) + +//IRQ_NUMBER +#define IRQ_DMA0 (96 + 16) +#define IRQ_DMA1 (96 + 17) +#define IRQ_DMA2 (96 + 18) +#define IRQ_DMA3 (96 + 19) +#define IRQ_DMA4 (96 + 20) +#define IRQ_DMA5 (96 + 21) +#define IRQ_DMA6 (96 + 22) +#define IRQ_DMA7_DMA8 (96 + 23) +#define IRQ_DMA9_DMA10 (96 + 24) +#define IRQ_DMA11 (96 + 25) +#define IRQ_DMA12 (96 + 26) +#define IRQ_DMA13 (96 + 27) +#define IRQ_DMA14 (96 + 28) +#define IRQ_DMA15 (96 + 31) + +//CS +#define DMA_CS_RESET (1 << 31) +#define DMA_CS_ABORT (1 << 30) +#define DMA_CS_DISDEBUG (1 << 29) +#define DMA_CS_DREQ_STOPS_DMA (1 << 5) +#define DMA_CS_PAUSED (1 << 4) +#define DMA_CS_DREQ (1 << 3) +#define DMA_CS_INT (1 << 2) +#define DMA_CS_END (1 << 1) +#define DMA_CS_ACTIVE (1 << 0) + +//CONBLK_AD +//The address must be256-bit aligned, so the bottom 5 bits of the address mustbe zero. + +//TI +//DMA Transfer Information. +#define DMA_TI_SRC_IGNORE (1 << 11) +#define DMA_TI_SRC_DREQ (1 << 10) +#define DMA_TI_SRC_WIDTH (1 << 9) +#define DMA_TI_SRC_INC (1 << 8) +#define DMA_TI_DEST_IGNORE (1 << 7) +#define DMA_TI_DEST_DREQ (1 << 6) +#define DMA_TI_DEST_WIDTH (1 << 5) +#define DMA_TI_DEST_INC (1 << 4) +#define DMA_TI_WAIT_RESP (1 << 3) +#define DMA_TI_TDMODE (1 << 1) +#define DMA_TI_INTEN (1 << 0) + +//SOURCE_AD +//DMA Source Address + +//DEST_AD +//DMA Destination Address + +//TXFR_LEN +//DMA Transfer Length + +void dma_init(dch); +rt_err_t dma_memcpy(void *src, void *dst, unsigned int size, unsigned int dch, unsigned int timeout); + +#endif