update lpc17xx libcpu
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1761 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
parent
eb3ae3e3ca
commit
06e810dfe8
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@ -31,6 +31,7 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
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IMPORT rt_thread_switch_interrupt_flag
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IMPORT rt_thread_switch_interrupt_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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IMPORT rt_interrupt_to_thread
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IMPORT rt_hw_hard_fault_exception
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;/*
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; * rt_base_t rt_hw_interrupt_disable();
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@ -85,8 +86,8 @@ _reswitch
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; r0 --> swith from thread stack
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; r0 --> swith from thread stack
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; r1 --> swith to thread stack
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; r1 --> swith to thread stack
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; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
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; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
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rt_hw_pend_sv PROC
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PendSV_Handler PROC
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EXPORT rt_hw_pend_sv
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EXPORT PendSV_Handler
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; disable interrupt to protect context switch
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; disable interrupt to protect context switch
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MRS r2, PRIMASK
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MRS r2, PRIMASK
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@ -172,4 +173,17 @@ rt_hw_interrupt_thread_switch PROC
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NOP
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NOP
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ENDP
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ENDP
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HardFault_Handler PROC
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EXPORT HardFault_Handler
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; get current context
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MRS r0, psp ; get fault thread stack pointer
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PUSH {lr}
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BL rt_hw_hard_fault_exception
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POP {lr}
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ORR lr, lr, #0x04
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BX lr
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ENDP
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END
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END
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@ -1,43 +0,0 @@
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/*
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* File : cpu.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first version
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* 2010-02-04 Magicoe Edit for LPC17xx Series
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*/
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#include <rtthread.h>
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/**
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* @addtogroup LPC17xx
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*/
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/*@{*/
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/**
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* reset cpu by dog's time-out
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*
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*/
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void rt_hw_cpu_reset()
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{
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/*NOTREACHED*/
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}
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/**
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* shutdown CPU
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*
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*/
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void rt_hw_cpu_shutdown()
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{
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rt_kprintf("shutdown...\n");
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RT_ASSERT(0);
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}
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/*@}*/
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@ -1,5 +1,5 @@
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/*
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/*
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* File : stack.c
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* File : cpu.c
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* This file is part of RT-Thread RTOS
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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*
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@ -9,9 +9,11 @@
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*
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*
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* Change Logs:
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* Change Logs:
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* Date Author Notes
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* Date Author Notes
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* 2006-08-23 Bernard the first version
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* 2009-01-05 Bernard first version
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* 2010-02-04 Magicoe Edit for LPC17xx Series
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* 2010-02-04 Magicoe Edit for LPC17xx Series
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* 2011-10-14 aozima merge all of C source code into cpuport.c
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*/
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*/
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#include <rtthread.h>
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#include <rtthread.h>
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/**
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/**
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@ -19,6 +21,22 @@
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*/
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*/
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/*@{*/
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/*@{*/
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struct stack_contex
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{
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r12;
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rt_uint32_t lr;
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rt_uint32_t pc;
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rt_uint32_t psr;
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};
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/* exception and interrupt handler table */
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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/**
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/**
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* This function will initialize thread stack
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* This function will initialize thread stack
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*
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*
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@ -57,4 +75,24 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
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return (rt_uint8_t *)stk;
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return (rt_uint8_t *)stk;
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}
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}
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extern void list_thread(void);
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extern rt_thread_t rt_current_thread;
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void rt_hw_hard_fault_exception(struct stack_contex* contex)
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{
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rt_kprintf("psr: 0x%08x\n", contex->psr);
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rt_kprintf(" pc: 0x%08x\n", contex->pc);
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rt_kprintf(" lr: 0x%08x\n", contex->lr);
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rt_kprintf("r12: 0x%08x\n", contex->r12);
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rt_kprintf("r03: 0x%08x\n", contex->r3);
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rt_kprintf("r02: 0x%08x\n", contex->r2);
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rt_kprintf("r01: 0x%08x\n", contex->r1);
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rt_kprintf("r00: 0x%08x\n", contex->r0);
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rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
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#ifdef RT_USING_FINSH
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list_thread();
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#endif
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while (1);
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}
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/*@}*/
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/*@}*/
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@ -1,47 +0,0 @@
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/*
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* File : fault.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first version
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*/
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#include <rtthread.h>
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struct stack_contex
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{
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rt_uint32_t r0;
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rt_uint32_t r1;
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rt_uint32_t r2;
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rt_uint32_t r3;
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rt_uint32_t r12;
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rt_uint32_t lr;
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rt_uint32_t pc;
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rt_uint32_t psr;
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};
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extern void rt_hw_interrupt_thread_switch(void);
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extern void list_thread(void);
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extern rt_thread_t rt_current_thread;
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void rt_hw_hard_fault_exception(struct stack_contex* contex)
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{
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rt_kprintf("psr: 0x%08x\n", contex->psr);
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rt_kprintf(" pc: 0x%08x\n", contex->pc);
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rt_kprintf(" lr: 0x%08x\n", contex->lr);
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rt_kprintf("r12: 0x%08x\n", contex->r12);
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rt_kprintf("r03: 0x%08x\n", contex->r3);
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rt_kprintf("r02: 0x%08x\n", contex->r2);
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rt_kprintf("r01: 0x%08x\n", contex->r1);
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rt_kprintf("r00: 0x%08x\n", contex->r0);
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rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
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#ifdef RT_USING_FINSH
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list_thread();
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#endif
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while (1);
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}
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@ -1,35 +0,0 @@
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;/*
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; * File : fault_iar.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; * 2010-12-20 aozima edit for IAR
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; */
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SECTION .text:CODE(2)
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THUMB
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REQUIRE8
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PRESERVE8
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IMPORT rt_hw_hard_fault_exception
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EXPORT rt_hw_hard_fault
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rt_hw_hard_fault:
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; get current context
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MRS r0, psp ; get fault thread stack pointer
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PUSH {lr}
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BL rt_hw_hard_fault_exception
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POP {lr}
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ORR lr, lr, #0x04
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BX lr
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END
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@ -1,35 +0,0 @@
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;/*
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; * File : fault_rvds.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-17 Bernard first version
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; */
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AREA |.text|, CODE, READONLY, ALIGN=2
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THUMB
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REQUIRE8
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PRESERVE8
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IMPORT rt_hw_hard_fault_exception
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rt_hw_hard_fault PROC
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EXPORT rt_hw_hard_fault
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; get current context
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MRS r0, psp ; get fault thread stack pointer
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PUSH {lr}
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BL rt_hw_hard_fault_exception
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POP {lr}
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ORR lr, lr, #0x04
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BX lr
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ENDP
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END
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/*
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* File : interrupt.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first version
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*/
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#include <rtthread.h>
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/* exception and interrupt handler table */
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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/*@}*/
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@ -1,345 +0,0 @@
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;/*****************************************************************************
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; * @file: start_iar.S
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; * @purpose: CMSIS Cortex-M3 Core Device Startup File
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; * for the NXP LPC17xx Device Series
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; * @version: V1.02
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; * @date: 31. July 2009
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; *----------------------------------------------------------------------------
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; *
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; * Copyright (C) 2009 ARM Limited. All rights reserved.
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; *
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; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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IMPORT rt_hw_hard_fault
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IMPORT rt_hw_pend_sv
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IMPORT rt_hw_timer_handler
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler
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DCD NMI_Handler
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DCD rt_hw_hard_fault
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DCD MemManage_Handler
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DCD BusFault_Handler
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DCD UsageFault_Handler
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__vector_table_0x1c
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD SVC_Handler
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DCD DebugMon_Handler
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DCD 0
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DCD rt_hw_pend_sv
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DCD rt_hw_timer_handler
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; External Interrupts
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DCD WDT_IRQHandler ; 16: Watchdog Timer
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DCD TIMER0_IRQHandler ; 17: Timer0
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DCD TIMER1_IRQHandler ; 18: Timer1
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DCD TIMER2_IRQHandler ; 19: Timer2
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DCD TIMER3_IRQHandler ; 20: Timer3
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DCD UART0_IRQHandler ; 21: UART0
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DCD UART1_IRQHandler ; 22: UART1
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DCD UART2_IRQHandler ; 23: UART2
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DCD UART3_IRQHandler ; 24: UART3
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DCD PWM1_IRQHandler ; 25: PWM1
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DCD I2C0_IRQHandler ; 26: I2C0
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DCD I2C1_IRQHandler ; 27: I2C1
|
|
||||||
DCD I2C2_IRQHandler ; 28: I2C2
|
|
||||||
DCD SPI_IRQHandler ; 29: SPI
|
|
||||||
DCD SSP0_IRQHandler ; 30: SSP0
|
|
||||||
DCD SSP1_IRQHandler ; 31: SSP1
|
|
||||||
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
|
|
||||||
DCD RTC_IRQHandler ; 33: Real Time Clock
|
|
||||||
DCD EINT0_IRQHandler ; 34: External Interrupt 0
|
|
||||||
DCD EINT1_IRQHandler ; 35: External Interrupt 1
|
|
||||||
DCD EINT2_IRQHandler ; 36: External Interrupt 2
|
|
||||||
DCD EINT3_IRQHandler ; 37: External Interrupt 3
|
|
||||||
DCD ADC_IRQHandler ; 38: A/D Converter
|
|
||||||
DCD BOD_IRQHandler ; 39: Brown-Out Detect
|
|
||||||
DCD USB_IRQHandler ; 40: USB
|
|
||||||
DCD CAN_IRQHandler ; 41: CAN
|
|
||||||
DCD DMA_IRQHandler ; 42: General Purpose DMA
|
|
||||||
DCD I2S_IRQHandler ; 43: I2S
|
|
||||||
DCD ENET_IRQHandler ; 44: Ethernet
|
|
||||||
DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
|
|
||||||
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
|
|
||||||
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
|
|
||||||
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors EQU __vector_table
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
|
|
||||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
||||||
;;
|
|
||||||
;; Default interrupt handlers.
|
|
||||||
;;
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
PUBWEAK Reset_Handler
|
|
||||||
SECTION .text:CODE:REORDER(2)
|
|
||||||
Reset_Handler
|
|
||||||
LDR R0, =SystemInit
|
|
||||||
BLX R0
|
|
||||||
LDR R0, =__iar_program_start
|
|
||||||
BX R0
|
|
||||||
|
|
||||||
PUBWEAK NMI_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
NMI_Handler
|
|
||||||
B NMI_Handler
|
|
||||||
|
|
||||||
PUBWEAK HardFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
HardFault_Handler
|
|
||||||
B HardFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK MemManage_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
MemManage_Handler
|
|
||||||
B MemManage_Handler
|
|
||||||
|
|
||||||
PUBWEAK BusFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
BusFault_Handler
|
|
||||||
B BusFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK UsageFault_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
UsageFault_Handler
|
|
||||||
B UsageFault_Handler
|
|
||||||
|
|
||||||
PUBWEAK SVC_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
SVC_Handler
|
|
||||||
B SVC_Handler
|
|
||||||
|
|
||||||
PUBWEAK DebugMon_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
DebugMon_Handler
|
|
||||||
B DebugMon_Handler
|
|
||||||
|
|
||||||
PUBWEAK PendSV_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
PendSV_Handler
|
|
||||||
B PendSV_Handler
|
|
||||||
|
|
||||||
PUBWEAK SysTick_Handler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
SysTick_Handler
|
|
||||||
B SysTick_Handler
|
|
||||||
|
|
||||||
PUBWEAK WDT_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
WDT_IRQHandler
|
|
||||||
B WDT_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIMER0_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
TIMER0_IRQHandler
|
|
||||||
B TIMER0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIMER1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
TIMER1_IRQHandler
|
|
||||||
B TIMER1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIMER2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
TIMER2_IRQHandler
|
|
||||||
B TIMER2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK TIMER3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
TIMER3_IRQHandler
|
|
||||||
B TIMER3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK UART0_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
UART0_IRQHandler
|
|
||||||
B UART0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK UART1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
UART1_IRQHandler
|
|
||||||
B UART1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK UART2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
UART2_IRQHandler
|
|
||||||
B UART2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK UART3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
UART3_IRQHandler
|
|
||||||
B UART3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PWM1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
PWM1_IRQHandler
|
|
||||||
B PWM1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C0_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
I2C0_IRQHandler
|
|
||||||
B I2C0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
I2C1_IRQHandler
|
|
||||||
B I2C1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2C2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
I2C2_IRQHandler
|
|
||||||
B I2C2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SPI_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
SPI_IRQHandler
|
|
||||||
B SPI_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SSP0_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
SSP0_IRQHandler
|
|
||||||
B SSP0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK SSP1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
SSP1_IRQHandler
|
|
||||||
B SSP1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PLL0_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
PLL0_IRQHandler
|
|
||||||
B PLL0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RTC_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
RTC_IRQHandler
|
|
||||||
B RTC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EINT0_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
EINT0_IRQHandler
|
|
||||||
B EINT0_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EINT1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
EINT1_IRQHandler
|
|
||||||
B EINT1_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EINT2_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
EINT2_IRQHandler
|
|
||||||
B EINT2_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK EINT3_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
EINT3_IRQHandler
|
|
||||||
B EINT3_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK ADC_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
ADC_IRQHandler
|
|
||||||
B ADC_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK BOD_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
BOD_IRQHandler
|
|
||||||
B BOD_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK USB_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
USB_IRQHandler
|
|
||||||
B USB_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK CAN_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
CAN_IRQHandler
|
|
||||||
B CAN_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK DMA_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
DMA_IRQHandler
|
|
||||||
B DMA_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK I2S_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
I2S_IRQHandler
|
|
||||||
B I2S_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK ENET_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
ENET_IRQHandler
|
|
||||||
B ENET_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK RIT_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
RIT_IRQHandler
|
|
||||||
B RIT_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK MCPWM_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
MCPWM_IRQHandler
|
|
||||||
B MCPWM_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK QEI_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
QEI_IRQHandler
|
|
||||||
B QEI_IRQHandler
|
|
||||||
|
|
||||||
PUBWEAK PLL1_IRQHandler
|
|
||||||
SECTION .text:CODE:REORDER(1)
|
|
||||||
PLL1_IRQHandler
|
|
||||||
B PLL1_IRQHandler
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
@ -1,266 +0,0 @@
|
||||||
; /*
|
|
||||||
; * File : start_rvds.s
|
|
||||||
; * This file is part of RT-Thread RTOS
|
|
||||||
; * COPYRIGHT (C) 2009, RT-Thread Development Team
|
|
||||||
; *
|
|
||||||
; * The license and distribution terms for this file may be
|
|
||||||
; * found in the file LICENSE in this distribution or at
|
|
||||||
; * http://www.rt-thread.org/license/LICENSE
|
|
||||||
; *
|
|
||||||
; * Change Logs:
|
|
||||||
; * Date Author Notes
|
|
||||||
; * 2009-09-23 Bernard first implementation
|
|
||||||
; * 2010-02-04 Magicoe Edit for LPC17xx Series
|
|
||||||
; */
|
|
||||||
|
|
||||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
|
||||||
|
|
||||||
; Amount of memory (in bytes) allocated for Stack
|
|
||||||
; Tailor this value to your application needs
|
|
||||||
; <h> Stack Configuration
|
|
||||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Stack_Size EQU 0x00000200
|
|
||||||
|
|
||||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
|
||||||
Stack_Mem SPACE Stack_Size
|
|
||||||
__initial_sp
|
|
||||||
; not use external SRAM as data memory
|
|
||||||
|
|
||||||
; <h> Heap Configuration
|
|
||||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
|
||||||
; </h>
|
|
||||||
|
|
||||||
Heap_Size EQU 0x00000000
|
|
||||||
|
|
||||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
|
||||||
__heap_base
|
|
||||||
Heap_Mem SPACE Heap_Size
|
|
||||||
__heap_limit
|
|
||||||
|
|
||||||
PRESERVE8
|
|
||||||
THUMB
|
|
||||||
|
|
||||||
IMPORT rt_hw_hard_fault
|
|
||||||
IMPORT rt_hw_pend_sv
|
|
||||||
IMPORT rt_hw_timer_handler
|
|
||||||
|
|
||||||
; Vector Table Mapped to Address 0 at Reset
|
|
||||||
AREA RESET, DATA, READONLY
|
|
||||||
EXPORT __Vectors
|
|
||||||
EXPORT __Vectors_End
|
|
||||||
EXPORT __Vectors_Size
|
|
||||||
|
|
||||||
__Vectors DCD __initial_sp ; Top of Stack
|
|
||||||
DCD Reset_Handler ; Reset Handler
|
|
||||||
DCD NMI_Handler ; NMI Handler
|
|
||||||
DCD rt_hw_hard_fault ; Hard Fault Handler
|
|
||||||
DCD MemManage_Handler ; MPU Fault Handler
|
|
||||||
DCD BusFault_Handler ; Bus Fault Handler
|
|
||||||
DCD UsageFault_Handler ; Usage Fault Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD SVC_Handler ; SVCall Handler
|
|
||||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
|
||||||
DCD 0 ; Reserved
|
|
||||||
DCD rt_hw_pend_sv ; PendSV Handler in RT-Thread
|
|
||||||
DCD rt_hw_timer_handler ; SysTick Handler in RT-Thread
|
|
||||||
|
|
||||||
; External Interrupts
|
|
||||||
DCD WDT_IRQHandler ; 16: Watchdog Timer
|
|
||||||
DCD TIMER0_IRQHandler ; 17: Timer0
|
|
||||||
DCD TIMER1_IRQHandler ; 18: Timer1
|
|
||||||
DCD TIMER2_IRQHandler ; 19: Timer2
|
|
||||||
DCD TIMER3_IRQHandler ; 20: Timer3
|
|
||||||
DCD UART0_IRQHandler ; 21: UART0
|
|
||||||
DCD UART1_IRQHandler ; 22: UART1
|
|
||||||
DCD UART2_IRQHandler ; 23: UART2
|
|
||||||
DCD UART3_IRQHandler ; 24: UART3
|
|
||||||
DCD PWM1_IRQHandler ; 25: PWM1
|
|
||||||
DCD I2C0_IRQHandler ; 26: I2C0
|
|
||||||
DCD I2C1_IRQHandler ; 27: I2C1
|
|
||||||
DCD I2C2_IRQHandler ; 28: I2C2
|
|
||||||
DCD SPI_IRQHandler ; 29: SPI
|
|
||||||
DCD SSP0_IRQHandler ; 30: SSP0
|
|
||||||
DCD SSP1_IRQHandler ; 31: SSP1
|
|
||||||
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
|
|
||||||
DCD RTC_IRQHandler ; 33: Real Time Clock
|
|
||||||
DCD EINT0_IRQHandler ; 34: External Interrupt 0
|
|
||||||
DCD EINT1_IRQHandler ; 35: External Interrupt 1
|
|
||||||
DCD EINT2_IRQHandler ; 36: External Interrupt 2
|
|
||||||
DCD EINT3_IRQHandler ; 37: External Interrupt 3
|
|
||||||
DCD ADC_IRQHandler ; 38: A/D Converter
|
|
||||||
DCD BOD_IRQHandler ; 39: Brown-Out Detect
|
|
||||||
DCD USB_IRQHandler ; 40: USB
|
|
||||||
DCD CAN_IRQHandler ; 41: CAN
|
|
||||||
DCD DMA_IRQHandler ; 42: General Purpose DMA
|
|
||||||
DCD I2S_IRQHandler ; 43: I2S
|
|
||||||
DCD ENET_IRQHandler ; 44: Ethernet
|
|
||||||
DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
|
|
||||||
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
|
|
||||||
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
|
|
||||||
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
|
|
||||||
|
|
||||||
__Vectors_End
|
|
||||||
|
|
||||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
|
||||||
|
|
||||||
AREA |.text|, CODE, READONLY
|
|
||||||
|
|
||||||
; Reset handler routine
|
|
||||||
Reset_Handler PROC
|
|
||||||
EXPORT Reset_Handler [WEAK]
|
|
||||||
IMPORT __main
|
|
||||||
|
|
||||||
LDR R1, = __initial_sp ; restore original stack pointer
|
|
||||||
MSR MSP, R1
|
|
||||||
|
|
||||||
LDR R0, =__main
|
|
||||||
BX R0
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
|
||||||
|
|
||||||
NMI_Handler PROC
|
|
||||||
EXPORT NMI_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
HardFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT HardFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
MemManage_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT MemManage_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
BusFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT BusFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
UsageFault_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT UsageFault_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
SVC_Handler PROC
|
|
||||||
EXPORT SVC_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
DebugMon_Handler\
|
|
||||||
PROC
|
|
||||||
EXPORT DebugMon_Handler [WEAK]
|
|
||||||
B .
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
Default_Handler PROC
|
|
||||||
|
|
||||||
EXPORT WDT_IRQHandler [WEAK]
|
|
||||||
EXPORT TIMER0_IRQHandler [WEAK]
|
|
||||||
EXPORT TIMER1_IRQHandler [WEAK]
|
|
||||||
EXPORT TIMER2_IRQHandler [WEAK]
|
|
||||||
EXPORT TIMER3_IRQHandler [WEAK]
|
|
||||||
EXPORT UART0_IRQHandler [WEAK]
|
|
||||||
EXPORT UART1_IRQHandler [WEAK]
|
|
||||||
EXPORT UART2_IRQHandler [WEAK]
|
|
||||||
EXPORT UART3_IRQHandler [WEAK]
|
|
||||||
EXPORT PWM1_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C0_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C1_IRQHandler [WEAK]
|
|
||||||
EXPORT I2C2_IRQHandler [WEAK]
|
|
||||||
EXPORT SPI_IRQHandler [WEAK]
|
|
||||||
EXPORT SSP0_IRQHandler [WEAK]
|
|
||||||
EXPORT SSP1_IRQHandler [WEAK]
|
|
||||||
EXPORT PLL0_IRQHandler [WEAK]
|
|
||||||
EXPORT RTC_IRQHandler [WEAK]
|
|
||||||
EXPORT EINT0_IRQHandler [WEAK]
|
|
||||||
EXPORT EINT1_IRQHandler [WEAK]
|
|
||||||
EXPORT EINT2_IRQHandler [WEAK]
|
|
||||||
EXPORT EINT3_IRQHandler [WEAK]
|
|
||||||
EXPORT ADC_IRQHandler [WEAK]
|
|
||||||
EXPORT BOD_IRQHandler [WEAK]
|
|
||||||
EXPORT USB_IRQHandler [WEAK]
|
|
||||||
EXPORT CAN_IRQHandler [WEAK]
|
|
||||||
EXPORT DMA_IRQHandler [WEAK]
|
|
||||||
EXPORT I2S_IRQHandler [WEAK]
|
|
||||||
EXPORT ENET_IRQHandler [WEAK]
|
|
||||||
EXPORT RIT_IRQHandler [WEAK]
|
|
||||||
EXPORT MCPWM_IRQHandler [WEAK]
|
|
||||||
EXPORT QEI_IRQHandler [WEAK]
|
|
||||||
EXPORT PLL1_IRQHandler [WEAK]
|
|
||||||
|
|
||||||
WDT_IRQHandler
|
|
||||||
TIMER0_IRQHandler
|
|
||||||
TIMER1_IRQHandler
|
|
||||||
TIMER2_IRQHandler
|
|
||||||
TIMER3_IRQHandler
|
|
||||||
UART0_IRQHandler
|
|
||||||
UART1_IRQHandler
|
|
||||||
UART2_IRQHandler
|
|
||||||
UART3_IRQHandler
|
|
||||||
PWM1_IRQHandler
|
|
||||||
I2C0_IRQHandler
|
|
||||||
I2C1_IRQHandler
|
|
||||||
I2C2_IRQHandler
|
|
||||||
SPI_IRQHandler
|
|
||||||
SSP0_IRQHandler
|
|
||||||
SSP1_IRQHandler
|
|
||||||
PLL0_IRQHandler
|
|
||||||
RTC_IRQHandler
|
|
||||||
EINT0_IRQHandler
|
|
||||||
EINT1_IRQHandler
|
|
||||||
EINT2_IRQHandler
|
|
||||||
EINT3_IRQHandler
|
|
||||||
ADC_IRQHandler
|
|
||||||
BOD_IRQHandler
|
|
||||||
USB_IRQHandler
|
|
||||||
CAN_IRQHandler
|
|
||||||
DMA_IRQHandler
|
|
||||||
I2S_IRQHandler
|
|
||||||
ENET_IRQHandler
|
|
||||||
RIT_IRQHandler
|
|
||||||
MCPWM_IRQHandler
|
|
||||||
QEI_IRQHandler
|
|
||||||
PLL1_IRQHandler
|
|
||||||
|
|
||||||
B .
|
|
||||||
|
|
||||||
ENDP
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
;*******************************************************************************
|
|
||||||
; User Stack and Heap initialization
|
|
||||||
;*******************************************************************************
|
|
||||||
IF :DEF:__MICROLIB
|
|
||||||
|
|
||||||
EXPORT __initial_sp
|
|
||||||
EXPORT __heap_base
|
|
||||||
EXPORT __heap_limit
|
|
||||||
|
|
||||||
ELSE
|
|
||||||
|
|
||||||
IMPORT __use_two_region_memory
|
|
||||||
EXPORT __user_initial_stackheap
|
|
||||||
|
|
||||||
__user_initial_stackheap
|
|
||||||
|
|
||||||
LDR R0, = Heap_Mem
|
|
||||||
LDR R1, =(Stack_Mem + Stack_Size)
|
|
||||||
LDR R2, = (Heap_Mem + Heap_Size)
|
|
||||||
LDR R3, = Stack_Mem
|
|
||||||
BX LR
|
|
||||||
|
|
||||||
ALIGN
|
|
||||||
|
|
||||||
ENDIF
|
|
||||||
|
|
||||||
END
|
|
||||||
|
|
||||||
;******************* COPYLEFT 2010 Magicoe *****END OF FILE*****
|
|
||||||
|
|
||||||
Loading…
Reference in New Issue