fix bl808-d0 && cv1800b compile error (#8513)

2024-01-28 16:05:52 +08:00 · 2024-01-28 16:05:52 +08:00 · 06d3f29035
parent 3f41bd95d1
commit 06d3f29035
60 changed files with 2628 additions and 82 deletions
--- a/bsp/bouffalo_lab/bl808/d0/.config
+++ b/bsp/bouffalo_lab/bl808/d0/.config
@ -9,8 +9,10 @@
 CONFIG_RT_NAME_MAX=20
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 CONFIG_RT_USING_SMART=y
+# CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_AMP is not set
 # CONFIG_RT_USING_SMP is not set
+CONFIG_RT_CPUS_NR=1
 CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
@ -20,6 +22,7 @@ CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=16384
@ -38,7 +41,7 @@ CONFIG_RT_KPRINTF_USING_LONGLONG=y
 CONFIG_RT_USING_DEBUG=y
 CONFIG_RT_DEBUGING_COLOR=y
 CONFIG_RT_DEBUGING_CONTEXT=y
-# CONFIG_RT_DEBUGING_INIT is not set
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
 # CONFIG_RT_DEBUGING_PAGE_LEAK is not set

 #
@ -68,19 +71,16 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 CONFIG_RT_USING_MEMTRACE=y
 # CONFIG_RT_USING_HEAP_ISR is not set
 CONFIG_RT_USING_HEAP=y
-
-#
-# Kernel Device Object
-#
 CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
-# CONFIG_RT_USING_DM is not set
+CONFIG_RT_USING_DEVICE_OPS=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREDSAFE_PRINTF is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart3"
-CONFIG_RT_VER_NUM=0x50002
+CONFIG_RT_VER_NUM=0x50100
 # CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32
 CONFIG_ARCH_CPU_64BIT=y
 CONFIG_RT_USING_CACHE=y
 # CONFIG_RT_USING_HW_ATOMIC is not set
@ -123,35 +123,36 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 CONFIG_RT_USING_DFS=y
 CONFIG_DFS_USING_POSIX=y
 CONFIG_DFS_USING_WORKDIR=y
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
 CONFIG_DFS_FD_MAX=16
-CONFIG_RT_USING_DFS_V1=y
-# CONFIG_RT_USING_DFS_V2 is not set
-CONFIG_DFS_FILESYSTEMS_MAX=4
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_RT_USING_DFS_V2=y
 # CONFIG_RT_USING_DFS_ELMFAT is not set
 CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_CROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
 # CONFIG_RT_USING_DFS_TMPFS is not set
 # CONFIG_RT_USING_DFS_MQUEUE is not set
+CONFIG_RT_USING_PAGECACHE=y
+
+#
+# page cache config
+#
+CONFIG_RT_PAGECACHE_COUNT=4096
+CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024
+CONFIG_RT_PAGECACHE_PRELOAD=4
+CONFIG_RT_PAGECACHE_HASH_NR=1024
+CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90
+CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70
 # CONFIG_RT_USING_FAL is not set
-CONFIG_RT_USING_LWP=y
-CONFIG_RT_LWP_MAX_NR=30
-CONFIG_LWP_TASK_STACK_SIZE=16384
-CONFIG_RT_CH_MSG_MAX_NR=1024
-CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
-CONFIG_LWP_TID_MAX_NR=64
-CONFIG_RT_LWP_SHM_MAX_NR=64
-# CONFIG_LWP_UNIX98_PTY is not set

 #
 # Device Drivers
 #
+# CONFIG_RT_USING_DM is not set
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_USING_SERIAL_V2 is not set
@ -166,6 +167,7 @@ CONFIG_RT_USING_I2C=y
 # CONFIG_RT_I2C_DEBUG is not set
 CONFIG_RT_USING_I2C_BITOPS=y
 # CONFIG_RT_I2C_BITOPS_DEBUG is not set
+# CONFIG_RT_USING_SOFT_I2C is not set
 # CONFIG_RT_USING_PHY is not set
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
@ -177,7 +179,6 @@ CONFIG_RT_USING_RANDOM=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_FDT is not set
 CONFIG_RT_USING_RTC=y
 # CONFIG_RT_USING_ALARM is not set
 # CONFIG_RT_USING_SOFT_RTC is not set
@ -269,6 +270,12 @@ CONFIG_RT_USING_POSIX_PIPE_SIZE=512
 # CONFIG_RT_USING_LWIP is not set
 # CONFIG_RT_USING_AT is not set

+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
 #
 # Utilities
 #
@ -284,6 +291,23 @@ CONFIG_RT_USING_ADT_HASHMAP=y
 CONFIG_RT_USING_ADT_REF=y
 # CONFIG_RT_USING_RT_LINK is not set
 # CONFIG_RT_USING_VBUS is not set
+CONFIG_RT_USING_LWP=y
+# CONFIG_LWP_DEBUG is not set
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
+CONFIG_RT_USING_LDSO=y
+# CONFIG_ELF_DEBUG_ENABLE is not set
+# CONFIG_ELF_LOAD_RANDOMIZE is not set
+
+#
+# Memory management
+#
+# CONFIG_RT_USING_MEMBLOCK is not set

 #
 # RT-Thread Utestcases
@ -325,6 +349,21 @@ CONFIG_RT_USING_ADT_REF=y
 #
 # CONFIG_PKG_USING_WLAN_WICED is not set
 # CONFIG_PKG_USING_RW007 is not set
+
+#
+# CYW43012 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@ -346,7 +385,6 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@ -367,6 +405,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_NMEALIB is not set
 # CONFIG_PKG_USING_PDULIB is not set
 # CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_BT_CYW43012 is not set
 # CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 # CONFIG_PKG_USING_WAYZ_IOTKIT is not set
 # CONFIG_PKG_USING_MAVLINK is not set
@ -386,6 +425,8 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ZFTP is not set
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set

 #
 # security packages
@ -432,7 +473,6 @@ CONFIG_RT_USING_ADT_REF=y
 # LVGL: powerful and easy-to-use embedded GUI library
 #
 # CONFIG_PKG_USING_LVGL is not set
-# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
 # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
 # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set

@ -507,6 +547,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_HASH_MATCH is not set
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
 # CONFIG_PKG_USING_VOFA_PLUS is not set
+# CONFIG_PKG_USING_ZDEBUG is not set

 #
 # system packages
@ -543,6 +584,8 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_LITEOS_SDK is not set
+# CONFIG_PKG_USING_TZ_DATABASE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
 # CONFIG_PKG_USING_PARTITION is not set
@ -566,6 +609,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_QBOOT is not set
 # CONFIG_PKG_USING_PPOOL is not set
 # CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_RPMSG_LITE is not set
 # CONFIG_PKG_USING_LPM is not set
 # CONFIG_PKG_USING_TLSF is not set
 # CONFIG_PKG_USING_EVENT_RECORDER is not set
@ -579,6 +623,11 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_AGILE_UPGRADE is not set
 # CONFIG_PKG_USING_FLASH_BLOB is not set
 # CONFIG_PKG_USING_MLIBC is not set
+# CONFIG_PKG_USING_TASK_MSG_BUS is not set
+# CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set

 #
 # peripheral libraries and drivers
@ -643,6 +692,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_BALANCE is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_SHT4X is not set
 # CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_ADT74XX is not set
 # CONFIG_PKG_USING_MAX17048 is not set
@ -744,6 +794,10 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_FINGERPRINT is not set
 # CONFIG_PKG_USING_BT_ECB02C is not set
 # CONFIG_PKG_USING_UAT is not set
+# CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set

 #
@ -758,6 +812,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set

 #
 # Signal Processing and Control Algorithm Packages
@ -804,6 +859,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
 # CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
@ -988,6 +1044,7 @@ CONFIG_RT_USING_ADT_REF=y
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set
 # CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set
@ -996,6 +1053,7 @@ CONFIG_RT_USING_ADT_REF=y
 #
 # Timing
 #
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
 # CONFIG_PKG_USING_ARDUINO_TICKER is not set
 # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set
@ -1032,7 +1090,6 @@ CONFIG_RT_USING_ADT_REF=y
 #
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
-# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set

 #
 # Signal IO
--- a/bsp/bouffalo_lab/bl808/d0/board/Kconfig
+++ b/bsp/bouffalo_lab/bl808/d0/board/Kconfig
@ -6,6 +6,8 @@ config BSP_USING_BL808
    select RT_USING_CACHE
    select ARCH_MM_MMU
    select BL808_CORE_D0
+    select RT_USING_SYSTEM_WORKQUEUE
+    select RT_USING_DEVICE_OPS
    default y

 config BL808_CORE_D0
--- a/bsp/bouffalo_lab/bl808/d0/rtconfig.h
+++ b/bsp/bouffalo_lab/bl808/d0/rtconfig.h
@ -8,6 +8,7 @@

 #define RT_NAME_MAX 20
 #define RT_USING_SMART
+#define RT_CPUS_NR 1
 #define RT_ALIGN_SIZE 8
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
@ -46,14 +47,13 @@
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_MEMTRACE
 #define RT_USING_HEAP
-
-/* Kernel Device Object */
-
 #define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart3"
-#define RT_VER_NUM 0x50002
+#define RT_VER_NUM 0x50100
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
 #define ARCH_CPU_64BIT
 #define RT_USING_CACHE
 #define ARCH_MM_MMU
@ -88,22 +88,26 @@
 #define DFS_USING_POSIX
 #define DFS_USING_WORKDIR
 #define DFS_FD_MAX 16
-#define RT_USING_DFS_V1
-#define DFS_FILESYSTEMS_MAX 4
-#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_V2
 #define RT_USING_DFS_DEVFS
-#define RT_USING_LWP
-#define RT_LWP_MAX_NR 30
-#define LWP_TASK_STACK_SIZE 16384
-#define RT_CH_MSG_MAX_NR 1024
-#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
-#define LWP_TID_MAX_NR 64
-#define RT_LWP_SHM_MAX_NR 64
+#define RT_USING_PAGECACHE
+
+/* page cache config */
+
+#define RT_PAGECACHE_COUNT 4096
+#define RT_PAGECACHE_ASPACE_COUNT 1024
+#define RT_PAGECACHE_PRELOAD 4
+#define RT_PAGECACHE_HASH_NR 1024
+#define RT_PAGECACHE_GC_WORK_LEVEL 90
+#define RT_PAGECACHE_GC_STOP_LEVEL 70

 /* Device Drivers */

 #define RT_USING_DEVICE_IPC
 #define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
@ -156,6 +160,9 @@
 /* Network */


+/* Memory protection */
+
+
 /* Utilities */

 #define RT_USING_RESOURCE_ID
@ -164,6 +171,17 @@
 #define RT_USING_ADT_BITMAP
 #define RT_USING_ADT_HASHMAP
 #define RT_USING_ADT_REF
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define RT_LWP_SHM_MAX_NR 64
+#define RT_USING_LDSO
+
+/* Memory management */
+

 /* RT-Thread Utestcases */

@ -181,6 +199,15 @@
 /* Wiced WiFi */


+/* CYW43012 WiFi */
+
+
+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
 /* IoT Cloud */


--- a/bsp/cv1800b/fip.bin
+++ b/bsp/cv1800b/fip.bin
--- a/bsp/cvitek/.gitignore
+++ b/bsp/cvitek/.gitignore
@ -0,0 +1,2 @@
+fip.bin
+boot.sd
--- a/bsp/cvitek/README.md
+++ b/bsp/cvitek/README.md
@ -0,0 +1,13 @@
+# cvitek bsp
+
+## 支持芯片
+针对算能系列 RISC-V 芯片的 bsp，包括：
+
+| 芯片名称 | 内存大小 |
+| ------- | ------- |
+| cv1800b | 64MByte |
+| | |
+
+## FAQ
+1. 如遇到不能正常编译，请先使用 `scons --menuconfig` 重新生成配置。
+2. 编译成功后，会在 `bsp/cvitek` 目录下自动生成 `fip.bin` 和 `boot.sd` 文件。
--- a/bsp/cvitek/combine-fip.sh
+++ b/bsp/cvitek/combine-fip.sh
@ -0,0 +1,23 @@
+#!/bin/bash
+
+set -e
+
+LITTLE_BIN=$1
+
+. ./pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env && \
+./pre-build/fsbl/plat/cv180x/fiptool.py -v genfip \
+	'fip.bin' \
+	--MONITOR_RUNADDR="${MONITOR_RUNADDR}" \
+	--BLCP_2ND_RUNADDR="${BLCP_2ND_RUNADDR}" \
+	--CHIP_CONF='./pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin' \
+	--NOR_INFO='FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF' \
+	--NAND_INFO='00000000'\
+	--BL2='pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin' \
+	--BLCP_IMG_RUNADDR=0x05200200 \
+	--BLCP_PARAM_LOADADDR=0 \
+	--BLCP=pre-build/fsbl/test/empty.bin \
+	--DDR_PARAM='pre-build/fsbl/test/cv181x/ddr_param.bin' \
+	--BLCP_2ND=$LITTLE_BIN \
+	--MONITOR='pre-build/fw_dynamic.bin' \
+	--LOADER_2ND='pre-build/u-boot-raw.bin' \
+	--compress='lzma'
--- a/bsp/cvitek/cv1800b/.config
+++ b/bsp/cvitek/cv1800b/.config
@ -9,6 +9,7 @@
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 CONFIG_RT_USING_SMART=y
+# CONFIG_RT_USING_NANO is not set
 # CONFIG_RT_USING_AMP is not set
 # CONFIG_RT_USING_SMP is not set
 CONFIG_RT_CPUS_NR=1
@ -21,6 +22,7 @@ CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_HOOK_USING_FUNC_PTR=y
+# CONFIG_RT_USING_HOOKLIST is not set
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=1024
@ -39,7 +41,7 @@ CONFIG_RT_KPRINTF_USING_LONGLONG=y
 CONFIG_RT_USING_DEBUG=y
 CONFIG_RT_DEBUGING_COLOR=y
 CONFIG_RT_DEBUGING_CONTEXT=y
-# CONFIG_RT_DEBUGING_INIT is not set
+# CONFIG_RT_DEBUGING_AUTO_INIT is not set
 # CONFIG_RT_DEBUGING_PAGE_LEAK is not set

 #
@ -70,8 +72,9 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_HEAP_ISR is not set
 CONFIG_RT_USING_HEAP=y
 CONFIG_RT_USING_DEVICE=y
-# CONFIG_RT_USING_DEVICE_OPS is not set
+CONFIG_RT_USING_DEVICE_OPS=y
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
+# CONFIG_RT_USING_THREDSAFE_PRINTF is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
@ -120,29 +123,26 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y
 CONFIG_RT_USING_DFS=y
 CONFIG_DFS_USING_POSIX=y
 CONFIG_DFS_USING_WORKDIR=y
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
 CONFIG_DFS_FD_MAX=16
-CONFIG_RT_USING_DFS_V1=y
-# CONFIG_RT_USING_DFS_V2 is not set
-CONFIG_DFS_FILESYSTEMS_MAX=4
-CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_RT_USING_DFS_V2=y
 # CONFIG_RT_USING_DFS_ELMFAT is not set
 CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_CROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
 # CONFIG_RT_USING_DFS_TMPFS is not set
 # CONFIG_RT_USING_DFS_MQUEUE is not set
+CONFIG_RT_USING_PAGECACHE=y
+
+#
+# page cache config
+#
+CONFIG_RT_PAGECACHE_COUNT=4096
+CONFIG_RT_PAGECACHE_ASPACE_COUNT=1024
+CONFIG_RT_PAGECACHE_PRELOAD=4
+CONFIG_RT_PAGECACHE_HASH_NR=1024
+CONFIG_RT_PAGECACHE_GC_WORK_LEVEL=90
+CONFIG_RT_PAGECACHE_GC_STOP_LEVEL=70
 # CONFIG_RT_USING_FAL is not set
-CONFIG_RT_USING_LWP=y
-# CONFIG_LWP_DEBUG is not set
-CONFIG_RT_LWP_MAX_NR=30
-CONFIG_LWP_TASK_STACK_SIZE=16384
-CONFIG_RT_CH_MSG_MAX_NR=1024
-CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
-CONFIG_LWP_TID_MAX_NR=64
-CONFIG_RT_LWP_SHM_MAX_NR=64
-# CONFIG_LWP_UNIX98_PTY is not set

 #
 # Device Drivers
@ -259,6 +259,12 @@ CONFIG_RT_USING_POSIX_TIMER=y
 # CONFIG_RT_USING_LWIP is not set
 # CONFIG_RT_USING_AT is not set

+#
+# Memory protection
+#
+# CONFIG_RT_USING_MEM_PROTECTION is not set
+# CONFIG_RT_USING_HW_STACK_GUARD is not set
+
 #
 # Utilities
 #
@ -274,6 +280,18 @@ CONFIG_RT_USING_ADT_HASHMAP=y
 CONFIG_RT_USING_ADT_REF=y
 # CONFIG_RT_USING_RT_LINK is not set
 # CONFIG_RT_USING_VBUS is not set
+CONFIG_RT_USING_LWP=y
+# CONFIG_LWP_DEBUG is not set
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
+CONFIG_RT_USING_LDSO=y
+# CONFIG_ELF_DEBUG_ENABLE is not set
+# CONFIG_ELF_LOAD_RANDOMIZE is not set

 #
 # Memory management
@ -325,6 +343,16 @@ CONFIG_RT_USING_ADT_REF=y
 # CYW43012 WiFi
 #
 # CONFIG_PKG_USING_WLAN_CYW43012 is not set
+
+#
+# BL808 WiFi
+#
+# CONFIG_PKG_USING_WLAN_BL808 is not set
+
+#
+# CYW43439 WiFi
+#
+# CONFIG_PKG_USING_WLAN_CYW43439 is not set
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
@ -346,7 +374,6 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
 # CONFIG_PKG_USING_JOYLINK is not set
-# CONFIG_PKG_USING_EZ_IOT_OS is not set
 # CONFIG_PKG_USING_IOTSHARP_SDK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
@ -388,6 +415,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_WOL is not set
 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set
 # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set
+# CONFIG_PKG_USING_LHC_MODBUS is not set

 #
 # security packages
@ -586,6 +614,9 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_MLIBC is not set
 # CONFIG_PKG_USING_TASK_MSG_BUS is not set
 # CONFIG_PKG_USING_SFDB is not set
+# CONFIG_PKG_USING_RTP is not set
+# CONFIG_PKG_USING_REB is not set
+# CONFIG_PKG_USING_R_RHEALSTONE is not set

 #
 # peripheral libraries and drivers
@ -753,6 +784,9 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_BT_ECB02C is not set
 # CONFIG_PKG_USING_UAT is not set
 # CONFIG_PKG_USING_ST7789 is not set
+# CONFIG_PKG_USING_VS1003 is not set
+# CONFIG_PKG_USING_X9555 is not set
+# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set
 # CONFIG_PKG_USING_SPI_TOOLS is not set

 #
@ -767,6 +801,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
+# CONFIG_PKG_USING_R_TINYMAIX is not set

 #
 # Signal Processing and Control Algorithm Packages
@ -776,7 +811,6 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_DIGITALCTRL is not set
 # CONFIG_PKG_USING_KISSFFT is not set
-# CONFIG_PKG_USING_CMSIS_DSP is not set

 #
 # miscellaneous packages
@ -814,6 +848,7 @@ CONFIG_RT_USING_ADT_REF=y
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
 # CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_RALARAM is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 # CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
@ -1066,6 +1101,7 @@ CONFIG_RT_USING_ADT_REF=y
 #
 CONFIG_BSP_USING_UART=y
 CONFIG_RT_USING_UART0=y
+CONFIG_UART_IRQ_BASE=30
 # CONFIG_RT_USING_UART1 is not set
 # CONFIG_RT_USING_UART2 is not set
 # CONFIG_RT_USING_UART3 is not set
--- a/bsp/cvitek/cv1800b/.gitignore
+++ b/bsp/cvitek/cv1800b/.gitignore
--- a/bsp/cvitek/cv1800b/Kconfig
+++ b/bsp/cvitek/cv1800b/Kconfig
@ -8,7 +8,7 @@ config BSP_DIR
 config RTT_DIR
    string
    option env="RTT_ROOT"
-    default "../.."
+    default "../../.."

 config PKGS_DIR
    string
@ -17,7 +17,7 @@ config PKGS_DIR

 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
-source "drivers/Kconfig"
+source "board/Kconfig"

 config BSP_USING_CV1800B
    bool
@ -27,6 +27,7 @@ config BSP_USING_CV1800B
    select RT_USING_USER_MAIN
    select RT_USING_CACHE
    select ARCH_MM_MMU
+    select RT_USING_DEVICE_OPS
    default y

 config C906_PLIC_PHY_ADDR
--- a/bsp/cvitek/cv1800b/README.md
+++ b/bsp/cvitek/cv1800b/README.md
--- a/bsp/cvitek/cv1800b/README_en.md
+++ b/bsp/cvitek/cv1800b/README_en.md
--- a/bsp/cvitek/cv1800b/SConscript
+++ b/bsp/cvitek/cv1800b/SConscript
--- a/bsp/cvitek/cv1800b/SConstruct
+++ b/bsp/cvitek/cv1800b/SConstruct
@ -24,9 +24,6 @@ Export('rtconfig')
 rtconfig.CPU='virt64'
 rtconfig.ARCH='risc-v'

-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
-
 stack_size = 4096

 stack_lds = open('link_stacksize.lds', 'w')
@ -34,5 +31,18 @@ if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
 stack_lds.write('__STACKSIZE__ = %d;\n' % stack_size)
 stack_lds.close()

+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/drivers'):
+    drivers_path_prefix = SDK_ROOT + '/drivers'
+else:
+    drivers_path_prefix = os.path.dirname(SDK_ROOT) + '/drivers'
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# include libraries
+objs.extend(SConscript(drivers_path_prefix + '/SConscript', variant_dir='build/drivers', duplicate=0))
+
 # make a building
 DoBuilding(TARGET, objs)
--- a/bsp/cvitek/cv1800b/applications/SConscript
+++ b/bsp/cvitek/cv1800b/applications/SConscript
--- a/bsp/cvitek/cv1800b/applications/main.c
+++ b/bsp/cvitek/cv1800b/applications/main.c
--- a/bsp/cvitek/cv1800b/board/Kconfig
+++ b/bsp/cvitek/cv1800b/board/Kconfig
@ -10,6 +10,10 @@ menu "General Drivers Configuration"
            bool "Enable UART 0"
            default y

+            config UART_IRQ_BASE
+            int
+            default 30
+            
            config RT_USING_UART1
            bool "Enable UART 1"
            default n
--- a/bsp/cvitek/cv1800b/board/SConscript
+++ b/bsp/cvitek/cv1800b/board/SConscript
--- a/bsp/cvitek/cv1800b/board/board.c
+++ b/bsp/cvitek/cv1800b/board/board.c
--- a/bsp/cvitek/cv1800b/board/board.h
+++ b/bsp/cvitek/cv1800b/board/board.h
--- a/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb
+++ b/bsp/cvitek/cv1800b/cv1800b_milkv_duo_sd.dtb
--- a/bsp/cvitek/cv1800b/link.lds
+++ b/bsp/cvitek/cv1800b/link.lds
--- a/bsp/cvitek/cv1800b/link_stacksize.lds
+++ b/bsp/cvitek/cv1800b/link_stacksize.lds
--- a/bsp/cvitek/cv1800b/mkimage
+++ b/bsp/cvitek/cv1800b/mkimage
--- a/bsp/cvitek/cv1800b/mksdimg.sh
+++ b/bsp/cvitek/cv1800b/mksdimg.sh
@ -4,4 +4,4 @@ echo "start compress kernel..."

 lzma -c -9 -f -k Image > Image.lzma

-./mkimage -f multi.its -r boot.sd
+./mkimage -f multi.its -r ../boot.sd
--- a/bsp/cvitek/cv1800b/multi.its
+++ b/bsp/cvitek/cv1800b/multi.its
--- a/bsp/cvitek/cv1800b/rtconfig.h
+++ b/bsp/cvitek/cv1800b/rtconfig.h
@ -47,6 +47,7 @@
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
 #define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart0"
@ -86,17 +87,18 @@
 #define DFS_USING_POSIX
 #define DFS_USING_WORKDIR
 #define DFS_FD_MAX 16
-#define RT_USING_DFS_V1
-#define DFS_FILESYSTEMS_MAX 4
-#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_V2
 #define RT_USING_DFS_DEVFS
-#define RT_USING_LWP
-#define RT_LWP_MAX_NR 30
-#define LWP_TASK_STACK_SIZE 16384
-#define RT_CH_MSG_MAX_NR 1024
-#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
-#define LWP_TID_MAX_NR 64
-#define RT_LWP_SHM_MAX_NR 64
+#define RT_USING_PAGECACHE
+
+/* page cache config */
+
+#define RT_PAGECACHE_COUNT 4096
+#define RT_PAGECACHE_ASPACE_COUNT 1024
+#define RT_PAGECACHE_PRELOAD 4
+#define RT_PAGECACHE_HASH_NR 1024
+#define RT_PAGECACHE_GC_WORK_LEVEL 90
+#define RT_PAGECACHE_GC_STOP_LEVEL 70

 /* Device Drivers */

@ -150,6 +152,9 @@
 /* Network */


+/* Memory protection */
+
+
 /* Utilities */

 #define RT_USING_RESOURCE_ID
@ -158,6 +163,14 @@
 #define RT_USING_ADT_BITMAP
 #define RT_USING_ADT_HASHMAP
 #define RT_USING_ADT_REF
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define RT_LWP_SHM_MAX_NR 64
+#define RT_USING_LDSO

 /* Memory management */

@ -181,6 +194,12 @@
 /* CYW43012 WiFi */


+/* BL808 WiFi */
+
+
+/* CYW43439 WiFi */
+
+
 /* IoT Cloud */


@ -285,6 +304,7 @@

 #define BSP_USING_UART
 #define RT_USING_UART0
+#define UART_IRQ_BASE 30
 #define BSP_USING_CV1800B
 #define C906_PLIC_PHY_ADDR 0x70000000
 #define IRQ_MAX_NR 64
--- a/bsp/cvitek/cv1800b/rtconfig.py
+++ b/bsp/cvitek/cv1800b/rtconfig.py
@ -9,7 +9,7 @@ CROSS_TOOL  ='gcc'
 if os.getenv('RTT_ROOT'):
    RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = r'../..'
+    RTT_ROOT = r'../../..'

 if os.getenv('RTT_CC'):
    CROSS_TOOL = os.getenv('RTT_CC')
@ -56,4 +56,4 @@ if PLATFORM == 'gcc':
    CXXFLAGS = CFLAGS

 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread.asm\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET Image\n' + SIZE + ' $TARGET \n' + './mksdimg.sh\n' + 'cd ../ && ./combine-fip.sh\n'
--- a/bsp/cvitek/drivers/SConscript
+++ b/bsp/cvitek/drivers/SConscript
@ -0,0 +1,16 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPDEFINES = []
+
+CPPPATH = [cwd]
+
+if GetDepend('BSP_USING_CV1800B'):
+    CPPPATH += [cwd + r'/cv1800b']
+
+CPPDEFINES += ['-DCONFIG_64BIT']
+
+group = DefineGroup('drivers', src, depend = [''], CPPDEFINES = CPPDEFINES, CPPPATH = CPPPATH)
+
+Return('group')
--- a/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h
+++ b/bsp/cvitek/drivers/cv1800b/cv180x_pinlist_swconfig.h
@ -0,0 +1,407 @@
+//##==============================================================================
+//##=== This script is generate by genswconfig.pl from .\00_Phobos_Pinlist_20220315.xls
+//##=== Generate Time stamp is : 2022-03-17 14:04:49
+//##==============================================================================
+
+#ifndef __CV180X_PINLIST_SWCONFIG_H__
+#define __CV180X_PINLIST_SWCONFIG_H__
+
+#define SD0_CLK__SDIO0_CLK 0
+#define SD0_CLK__IIC1_SDA 1
+#define SD0_CLK__SPI0_SCK 2
+#define SD0_CLK__XGPIOA_7 3
+#define SD0_CLK__PWM_15 5
+#define SD0_CLK__EPHY_LNK_LED 6
+#define SD0_CLK__DBG_0 7
+#define SD0_CMD__SDIO0_CMD 0
+#define SD0_CMD__IIC1_SCL 1
+#define SD0_CMD__SPI0_SDO 2
+#define SD0_CMD__XGPIOA_8 3
+#define SD0_CMD__PWM_14 5
+#define SD0_CMD__EPHY_SPD_LED 6
+#define SD0_CMD__DBG_1 7
+#define SD0_D0__SDIO0_D_0 0
+#define SD0_D0__CAM_MCLK1 1
+#define SD0_D0__SPI0_SDI 2
+#define SD0_D0__XGPIOA_9 3
+#define SD0_D0__UART3_TX 4
+#define SD0_D0__PWM_13 5
+#define SD0_D0__WG0_D0 6
+#define SD0_D0__DBG_2 7
+#define SD0_D1__SDIO0_D_1 0
+#define SD0_D1__IIC1_SDA 1
+#define SD0_D1__AUX0 2
+#define SD0_D1__XGPIOA_10 3
+#define SD0_D1__UART1_TX 4
+#define SD0_D1__PWM_12 5
+#define SD0_D1__WG0_D1 6
+#define SD0_D1__DBG_3 7
+#define SD0_D2__SDIO0_D_2 0
+#define SD0_D2__IIC1_SCL 1
+#define SD0_D2__AUX1 2
+#define SD0_D2__XGPIOA_11 3
+#define SD0_D2__UART1_RX 4
+#define SD0_D2__PWM_11 5
+#define SD0_D2__WG1_D0 6
+#define SD0_D2__DBG_4 7
+#define SD0_D3__SDIO0_D_3 0
+#define SD0_D3__CAM_MCLK0 1
+#define SD0_D3__SPI0_CS_X 2
+#define SD0_D3__XGPIOA_12 3
+#define SD0_D3__UART3_RX 4
+#define SD0_D3__PWM_10 5
+#define SD0_D3__WG1_D1 6
+#define SD0_D3__DBG_5 7
+#define SD0_CD__SDIO0_CD 0
+#define SD0_CD__XGPIOA_13 3
+#define SD0_PWR_EN__SDIO0_PWR_EN 0
+#define SD0_PWR_EN__XGPIOA_14 3
+#define SPK_EN__XGPIOA_15 3
+#define UART0_TX__UART0_TX 0
+#define UART0_TX__CAM_MCLK1 1
+#define UART0_TX__PWM_4 2
+#define UART0_TX__XGPIOA_16 3
+#define UART0_TX__UART1_TX 4
+#define UART0_TX__AUX1 5
+#define UART0_TX__JTAG_TMS 6
+#define UART0_TX__DBG_6 7
+#define UART0_RX__UART0_RX 0
+#define UART0_RX__CAM_MCLK0 1
+#define UART0_RX__PWM_5 2
+#define UART0_RX__XGPIOA_17 3
+#define UART0_RX__UART1_RX 4
+#define UART0_RX__AUX0 5
+#define UART0_RX__JTAG_TCK 6
+#define UART0_RX__DBG_7 7
+#define SPINOR_HOLD_X__SPINOR_HOLD_X 1
+#define SPINOR_HOLD_X__SPINAND_HOLD 2
+#define SPINOR_HOLD_X__XGPIOA_26 3
+#define SPINOR_SCK__SPINOR_SCK 1
+#define SPINOR_SCK__SPINAND_CLK 2
+#define SPINOR_SCK__XGPIOA_22 3
+#define SPINOR_MOSI__SPINOR_MOSI 1
+#define SPINOR_MOSI__SPINAND_MOSI 2
+#define SPINOR_MOSI__XGPIOA_25 3
+#define SPINOR_WP_X__SPINOR_WP_X 1
+#define SPINOR_WP_X__SPINAND_WP 2
+#define SPINOR_WP_X__XGPIOA_27 3
+#define SPINOR_MISO__SPINOR_MISO 1
+#define SPINOR_MISO__SPINAND_MISO 2
+#define SPINOR_MISO__XGPIOA_23 3
+#define SPINOR_CS_X__SPINOR_CS_X 1
+#define SPINOR_CS_X__SPINAND_CS 2
+#define SPINOR_CS_X__XGPIOA_24 3
+#define JTAG_CPU_TMS__JTAG_TMS 0
+#define JTAG_CPU_TMS__CAM_MCLK0 1
+#define JTAG_CPU_TMS__PWM_7 2
+#define JTAG_CPU_TMS__XGPIOA_19 3
+#define JTAG_CPU_TMS__UART1_RTS 4
+#define JTAG_CPU_TMS__AUX0 5
+#define JTAG_CPU_TMS__UART1_TX 6
+#define JTAG_CPU_TCK__JTAG_TCK 0
+#define JTAG_CPU_TCK__CAM_MCLK1 1
+#define JTAG_CPU_TCK__PWM_6 2
+#define JTAG_CPU_TCK__XGPIOA_18 3
+#define JTAG_CPU_TCK__UART1_CTS 4
+#define JTAG_CPU_TCK__AUX1 5
+#define JTAG_CPU_TCK__UART1_RX 6
+#define IIC0_SCL__CV_SCL0__CR_4WTDI 0
+#define IIC0_SDA__CV_SDA0__CR_4WTDO 0
+#define IIC0_SCL__JTAG_TDI 0
+#define IIC0_SCL__UART1_TX 1
+#define IIC0_SCL__UART2_TX 2
+#define IIC0_SCL__XGPIOA_28 3
+#define IIC0_SCL__IIC0_SCL 4
+#define IIC0_SCL__WG0_D0 5
+#define IIC0_SCL__DBG_10 7
+#define IIC0_SDA__JTAG_TDO 0
+#define IIC0_SDA__UART1_RX 1
+#define IIC0_SDA__UART2_RX 2
+#define IIC0_SDA__XGPIOA_29 3
+#define IIC0_SDA__IIC0_SDA 4
+#define IIC0_SDA__WG0_D1 5
+#define IIC0_SDA__WG1_D0 6
+#define IIC0_SDA__DBG_11 7
+#define AUX0__AUX0 0
+#define AUX0__XGPIOA_30 3
+#define AUX0__IIS1_MCLK 4
+#define AUX0__WG1_D1 6
+#define AUX0__DBG_12 7
+#define GPIO_ZQ__PWR_GPIO_24 3
+#define GPIO_ZQ__PWM_2 4
+#define PWR_VBAT_DET__PWR_VBAT_DET 0
+#define PWR_RSTN__PWR_RSTN 0
+#define PWR_SEQ1__PWR_SEQ1 0
+#define PWR_SEQ1__PWR_GPIO_3 3
+#define PWR_SEQ2__PWR_SEQ2 0
+#define PWR_SEQ2__PWR_GPIO_4 3
+#define PTEST__PWR_PTEST 0
+#define PWR_WAKEUP0__PWR_WAKEUP0 0
+#define PWR_WAKEUP0__PWR_IR0 1
+#define PWR_WAKEUP0__PWR_UART0_TX 2
+#define PWR_WAKEUP0__PWR_GPIO_6 3
+#define PWR_WAKEUP0__UART1_TX 4
+#define PWR_WAKEUP0__IIC4_SCL 5
+#define PWR_WAKEUP0__EPHY_LNK_LED 6
+#define PWR_WAKEUP0__WG2_D0 7
+#define PWR_BUTTON1__PWR_BUTTON1 0
+#define PWR_BUTTON1__PWR_GPIO_8 3
+#define PWR_BUTTON1__UART1_RX 4
+#define PWR_BUTTON1__IIC4_SDA 5
+#define PWR_BUTTON1__EPHY_SPD_LED 6
+#define PWR_BUTTON1__WG2_D1 7
+#define XTAL_XIN__PWR_XTAL_CLKIN 0
+#define PWR_GPIO0__PWR_GPIO_0 0
+#define PWR_GPIO0__UART2_TX 1
+#define PWR_GPIO0__PWR_UART0_RX 2
+#define PWR_GPIO0__PWM_8 4
+#define PWR_GPIO1__PWR_GPIO_1 0
+#define PWR_GPIO1__UART2_RX 1
+#define PWR_GPIO1__EPHY_LNK_LED 3
+#define PWR_GPIO1__PWM_9 4
+#define PWR_GPIO1__PWR_IIC_SCL 5
+#define PWR_GPIO1__IIC2_SCL 6
+#define PWR_GPIO1__IIC0_SDA 7
+#define PWR_GPIO2__PWR_GPIO_2 0
+#define PWR_GPIO2__PWR_SECTICK 2
+#define PWR_GPIO2__EPHY_SPD_LED 3
+#define PWR_GPIO2__PWM_10 4
+#define PWR_GPIO2__PWR_IIC_SDA 5
+#define PWR_GPIO2__IIC2_SDA 6
+#define PWR_GPIO2__IIC0_SCL 7
+#define SD1_GPIO1__UART4_TX 1
+#define SD1_GPIO1__PWR_GPIO_26 3
+#define SD1_GPIO1__PWM_10 7
+#define SD1_GPIO0__UART4_RX 1
+#define SD1_GPIO0__PWR_GPIO_25 3
+#define SD1_GPIO0__PWM_11 7
+#define SD1_D3__PWR_SD1_D3 0
+#define SD1_D3__SPI2_CS_X 1
+#define SD1_D3__IIC1_SCL 2
+#define SD1_D3__PWR_GPIO_18 3
+#define SD1_D3__CAM_MCLK0 4
+#define SD1_D3__UART3_CTS 5
+#define SD1_D3__PWR_SPINOR1_CS_X 6
+#define SD1_D3__PWM_4 7
+#define SD1_D2__PWR_SD1_D2 0
+#define SD1_D2__IIC1_SCL 1
+#define SD1_D2__UART2_TX 2
+#define SD1_D2__PWR_GPIO_19 3
+#define SD1_D2__CAM_MCLK0 4
+#define SD1_D2__UART3_TX 5
+#define SD1_D2__PWR_SPINOR1_HOLD_X 6
+#define SD1_D2__PWM_5 7
+#define SD1_D1__PWR_SD1_D1 0
+#define SD1_D1__IIC1_SDA 1
+#define SD1_D1__UART2_RX 2
+#define SD1_D1__PWR_GPIO_20 3
+#define SD1_D1__CAM_MCLK1 4
+#define SD1_D1__UART3_RX 5
+#define SD1_D1__PWR_SPINOR1_WP_X 6
+#define SD1_D1__PWM_6 7
+#define SD1_D0__PWR_SD1_D0 0
+#define SD1_D0__SPI2_SDI 1
+#define SD1_D0__IIC1_SDA 2
+#define SD1_D0__PWR_GPIO_21 3
+#define SD1_D0__CAM_MCLK1 4
+#define SD1_D0__UART3_RTS 5
+#define SD1_D0__PWR_SPINOR1_MISO 6
+#define SD1_D0__PWM_7 7
+#define SD1_CMD__PWR_SD1_CMD 0
+#define SD1_CMD__SPI2_SDO 1
+#define SD1_CMD__IIC3_SCL 2
+#define SD1_CMD__PWR_GPIO_22 3
+#define SD1_CMD__CAM_VS0 4
+#define SD1_CMD__EPHY_LNK_LED 5
+#define SD1_CMD__PWR_SPINOR1_MOSI 6
+#define SD1_CMD__PWM_8 7
+#define SD1_CLK__PWR_SD1_CLK 0
+#define SD1_CLK__SPI2_SCK 1
+#define SD1_CLK__IIC3_SDA 2
+#define SD1_CLK__PWR_GPIO_23 3
+#define SD1_CLK__CAM_HS0 4
+#define SD1_CLK__EPHY_SPD_LED 5
+#define SD1_CLK__PWR_SPINOR1_SCK 6
+#define SD1_CLK__PWM_9 7
+#define PWM0_BUCK__PWM_0 0
+#define PWM0_BUCK__XGPIOB_0 3
+#define ADC1__XGPIOB_3 3
+#define ADC1__KEY_COL2 4
+#define ADC1__PWM_3 6
+#define USB_VBUS_DET__USB_VBUS_DET 0
+#define USB_VBUS_DET__XGPIOB_6 3
+#define USB_VBUS_DET__CAM_MCLK0 4
+#define USB_VBUS_DET__CAM_MCLK1 5
+#define USB_VBUS_DET__PWM_4 6
+#define MUX_SPI1_MISO__UART3_RTS 1
+#define MUX_SPI1_MISO__IIC1_SDA 2
+#define MUX_SPI1_MISO__XGPIOB_8 3
+#define MUX_SPI1_MISO__PWM_9 4
+#define MUX_SPI1_MISO__KEY_COL1 5
+#define MUX_SPI1_MISO__SPI1_SDI 6
+#define MUX_SPI1_MISO__DBG_14 7
+#define MUX_SPI1_MOSI__UART3_RX 1
+#define MUX_SPI1_MOSI__IIC1_SCL 2
+#define MUX_SPI1_MOSI__XGPIOB_7 3
+#define MUX_SPI1_MOSI__PWM_8 4
+#define MUX_SPI1_MOSI__KEY_COL0 5
+#define MUX_SPI1_MOSI__SPI1_SDO 6
+#define MUX_SPI1_MOSI__DBG_13 7
+#define MUX_SPI1_CS__UART3_CTS 1
+#define MUX_SPI1_CS__CAM_MCLK0 2
+#define MUX_SPI1_CS__XGPIOB_10 3
+#define MUX_SPI1_CS__PWM_11 4
+#define MUX_SPI1_CS__KEY_ROW3 5
+#define MUX_SPI1_CS__SPI1_CS_X 6
+#define MUX_SPI1_CS__DBG_16 7
+#define MUX_SPI1_SCK__UART3_TX 1
+#define MUX_SPI1_SCK__CAM_MCLK1 2
+#define MUX_SPI1_SCK__XGPIOB_9 3
+#define MUX_SPI1_SCK__PWM_10 4
+#define MUX_SPI1_SCK__KEY_ROW2 5
+#define MUX_SPI1_SCK__SPI1_SCK 6
+#define MUX_SPI1_SCK__DBG_15 7
+#define PAD_ETH_TXP__UART3_RX 1
+#define PAD_ETH_TXP__IIC1_SCL 2
+#define PAD_ETH_TXP__XGPIOB_25 3
+#define PAD_ETH_TXP__PWM_13 4
+#define PAD_ETH_TXP__CAM_MCLK0 5
+#define PAD_ETH_TXP__SPI1_SDO 6
+#define PAD_ETH_TXP__IIS2_LRCK 7
+#define PAD_ETH_TXM__UART3_RTS 1
+#define PAD_ETH_TXM__IIC1_SDA 2
+#define PAD_ETH_TXM__XGPIOB_24 3
+#define PAD_ETH_TXM__PWM_12 4
+#define PAD_ETH_TXM__CAM_MCLK1 5
+#define PAD_ETH_TXM__SPI1_SDI 6
+#define PAD_ETH_TXM__IIS2_BCLK 7
+#define PAD_ETH_RXP__UART3_TX 1
+#define PAD_ETH_RXP__CAM_MCLK1 2
+#define PAD_ETH_RXP__XGPIOB_27 3
+#define PAD_ETH_RXP__PWM_15 4
+#define PAD_ETH_RXP__CAM_HS0 5
+#define PAD_ETH_RXP__SPI1_SCK 6
+#define PAD_ETH_RXP__IIS2_DO 7
+#define PAD_ETH_RXM__UART3_CTS 1
+#define PAD_ETH_RXM__CAM_MCLK0 2
+#define PAD_ETH_RXM__XGPIOB_26 3
+#define PAD_ETH_RXM__PWM_14 4
+#define PAD_ETH_RXM__CAM_VS0 5
+#define PAD_ETH_RXM__SPI1_CS_X 6
+#define PAD_ETH_RXM__IIS2_DI 7
+#define GPIO_RTX__VI0_D_15 1
+#define GPIO_RTX__XGPIOB_23 3
+#define GPIO_RTX__PWM_1 4
+#define GPIO_RTX__CAM_MCLK0 5
+#define GPIO_RTX__IIS2_MCLK 7
+#define PAD_MIPIRX4N__VI0_CLK 1
+#define PAD_MIPIRX4N__IIC0_SCL 2
+#define PAD_MIPIRX4N__XGPIOC_2 3
+#define PAD_MIPIRX4N__IIC1_SDA 4
+#define PAD_MIPIRX4N__CAM_MCLK0 5
+#define PAD_MIPIRX4N__KEY_ROW0 6
+#define PAD_MIPIRX4N__MUX_SPI1_SCK 7
+#define PAD_MIPIRX4P__VI0_D_0 1
+#define PAD_MIPIRX4P__IIC0_SDA 2
+#define PAD_MIPIRX4P__XGPIOC_3 3
+#define PAD_MIPIRX4P__IIC1_SCL 4
+#define PAD_MIPIRX4P__CAM_MCLK1 5
+#define PAD_MIPIRX4P__KEY_ROW1 6
+#define PAD_MIPIRX4P__MUX_SPI1_CS 7
+#define PAD_MIPIRX3N__VI0_D_1 1
+#define PAD_MIPIRX3N__XGPIOC_4 3
+#define PAD_MIPIRX3N__CAM_MCLK0 4
+#define PAD_MIPIRX3N__MUX_SPI1_MISO 7
+#define PAD_MIPIRX3P__VI0_D_2 1
+#define PAD_MIPIRX3P__XGPIOC_5 3
+#define PAD_MIPIRX3P__MUX_SPI1_MOSI 7
+#define PAD_MIPIRX2N__VI0_D_3 1
+#define PAD_MIPIRX2N__XGPIOC_6 3
+#define PAD_MIPIRX2N__IIC4_SCL 5
+#define PAD_MIPIRX2N__DBG_6 7
+#define PAD_MIPIRX2P__VI0_D_4 1
+#define PAD_MIPIRX2P__XGPIOC_7 3
+#define PAD_MIPIRX2P__IIC4_SDA 5
+#define PAD_MIPIRX2P__DBG_7 7
+#define PAD_MIPIRX1N__VI0_D_5 1
+#define PAD_MIPIRX1N__XGPIOC_8 3
+#define PAD_MIPIRX1N__KEY_ROW3 6
+#define PAD_MIPIRX1N__DBG_8 7
+#define PAD_MIPIRX1P__VI0_D_6 1
+#define PAD_MIPIRX1P__XGPIOC_9 3
+#define PAD_MIPIRX1P__IIC1_SDA 4
+#define PAD_MIPIRX1P__KEY_ROW2 6
+#define PAD_MIPIRX1P__DBG_9 7
+#define PAD_MIPIRX0N__VI0_D_7 1
+#define PAD_MIPIRX0N__XGPIOC_10 3
+#define PAD_MIPIRX0N__IIC1_SCL 4
+#define PAD_MIPIRX0N__CAM_MCLK1 5
+#define PAD_MIPIRX0N__DBG_10 7
+#define PAD_MIPIRX0P__VI0_D_8 1
+#define PAD_MIPIRX0P__XGPIOC_11 3
+#define PAD_MIPIRX0P__CAM_MCLK0 4
+#define PAD_MIPIRX0P__DBG_11 7
+#define PAD_MIPI_TXM2__VI0_D_13 1
+#define PAD_MIPI_TXM2__IIC0_SDA 2
+#define PAD_MIPI_TXM2__XGPIOC_16 3
+#define PAD_MIPI_TXM2__IIC1_SDA 4
+#define PAD_MIPI_TXM2__PWM_8 5
+#define PAD_MIPI_TXM2__SPI0_SCK 6
+#define PAD_MIPI_TXP2__VI0_D_14 1
+#define PAD_MIPI_TXP2__IIC0_SCL 2
+#define PAD_MIPI_TXP2__XGPIOC_17 3
+#define PAD_MIPI_TXP2__IIC1_SCL 4
+#define PAD_MIPI_TXP2__PWM_9 5
+#define PAD_MIPI_TXP2__SPI0_CS_X 6
+#define PAD_MIPI_TXP2__IIS1_MCLK 7
+#define PAD_MIPI_TXM1__SPI3_SDO 0
+#define PAD_MIPI_TXM1__VI0_D_11 1
+#define PAD_MIPI_TXM1__IIS1_LRCK 2
+#define PAD_MIPI_TXM1__XGPIOC_14 3
+#define PAD_MIPI_TXM1__IIC2_SDA 4
+#define PAD_MIPI_TXM1__PWM_10 5
+#define PAD_MIPI_TXM1__SPI0_SDO 6
+#define PAD_MIPI_TXM1__DBG_14 7
+#define PAD_MIPI_TXP1__SPI3_SDI 0
+#define PAD_MIPI_TXP1__VI0_D_12 1
+#define PAD_MIPI_TXP1__IIS1_DO 2
+#define PAD_MIPI_TXP1__XGPIOC_15 3
+#define PAD_MIPI_TXP1__IIC2_SCL 4
+#define PAD_MIPI_TXP1__PWM_11 5
+#define PAD_MIPI_TXP1__SPI0_SDI 6
+#define PAD_MIPI_TXP1__DBG_15 7
+#define PAD_MIPI_TXM0__SPI3_SCK 0
+#define PAD_MIPI_TXM0__VI0_D_9 1
+#define PAD_MIPI_TXM0__IIS1_DI 2
+#define PAD_MIPI_TXM0__XGPIOC_12 3
+#define PAD_MIPI_TXM0__CAM_MCLK1 4
+#define PAD_MIPI_TXM0__PWM_14 5
+#define PAD_MIPI_TXM0__CAM_VS0 6
+#define PAD_MIPI_TXM0__DBG_12 7
+#define PAD_MIPI_TXP0__SPI3_CS_X 0
+#define PAD_MIPI_TXP0__VI0_D_10 1
+#define PAD_MIPI_TXP0__IIS1_BCLK 2
+#define PAD_MIPI_TXP0__XGPIOC_13 3
+#define PAD_MIPI_TXP0__CAM_MCLK0 4
+#define PAD_MIPI_TXP0__PWM_15 5
+#define PAD_MIPI_TXP0__CAM_HS0 6
+#define PAD_MIPI_TXP0__DBG_13 7
+#define PKG_TYPE0__PKG_TYPE0 0
+#define PKG_TYPE1__PKG_TYPE1 0
+#define PKG_TYPE2__PKG_TYPE2 0
+#define PAD_AUD_AINL_MIC__XGPIOC_23 3
+#define PAD_AUD_AINL_MIC__IIS1_BCLK 4
+#define PAD_AUD_AINL_MIC__IIS2_BCLK 5
+#define PAD_AUD_AINR_MIC__XGPIOC_22 3
+#define PAD_AUD_AINR_MIC__IIS1_DO 4
+#define PAD_AUD_AINR_MIC__IIS2_DI 5
+#define PAD_AUD_AINR_MIC__IIS1_DI 6
+#define PAD_AUD_AOUTL__XGPIOC_25 3
+#define PAD_AUD_AOUTL__IIS1_LRCK 4
+#define PAD_AUD_AOUTL__IIS2_LRCK 5
+#define PAD_AUD_AOUTR__XGPIOC_24 3
+#define PAD_AUD_AOUTR__IIS1_DI 4
+#define PAD_AUD_AOUTR__IIS2_DO 5
+#define PAD_AUD_AOUTR__IIS1_DO 6
+
+#endif /* __CV180X_PINLIST_SWCONFIG_H__ */
--- a/bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h
+++ b/bsp/cvitek/drivers/cv1800b/cv180x_pinmux.h
@ -0,0 +1,51 @@
+#ifndef _CV180X_PINMUX_H_
+#define _CV180X_PINMUX_H_
+
+/*
+ * Pinmux definitions
+ */
+#define PINMUX_UART0    0
+#define PINMUX_UART1    1
+#define PINMUX_UART2    2
+#define PINMUX_UART3    3
+#define PINMUX_UART3_2  4
+#define PINMUX_I2C0     5
+#define PINMUX_I2C1     6
+#define PINMUX_I2C2     7
+#define PINMUX_I2C3     8
+#define PINMUX_I2C4     9
+#define PINMUX_I2C4_2   10
+#define PINMUX_SPI0     11
+#define PINMUX_SPI1     12
+#define PINMUX_SPI2     13
+#define PINMUX_SPI2_2   14
+#define PINMUX_SPI3     15
+#define PINMUX_SPI3_2   16
+#define PINMUX_I2S0     17
+#define PINMUX_I2S1     18
+#define PINMUX_I2S2     19
+#define PINMUX_I2S3     20
+#define PINMUX_USBID    21
+#define PINMUX_SDIO0    22
+#define PINMUX_SDIO1    23
+#define PINMUX_ND       24
+#define PINMUX_EMMC     25
+#define PINMUX_SPI_NOR  26
+#define PINMUX_SPI_NAND 27
+#define PINMUX_CAM0     28
+#define PINMUX_CAM1     29
+#define PINMUX_PCM0     30
+#define PINMUX_PCM1     31
+#define PINMUX_CSI0     32
+#define PINMUX_CSI1     33
+#define PINMUX_CSI2     34
+#define PINMUX_DSI      35
+#define PINMUX_VI0      36
+#define PINMUX_VO       37
+#define PINMUX_RMII1    38
+#define PINMUX_EPHY_LED 39
+#define PINMUX_I80      40
+#define PINMUX_LVDS     41
+#define PINMUX_USB     42
+
+#endif // end of _CV180X_PINMUX_H_
--- a/bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h
+++ b/bsp/cvitek/drivers/cv1800b/cv180x_reg_fmux_gpio.h
@ -0,0 +1,337 @@
+// $Module: fmux_gpio $
+// $RegisterBank Version: V 1.0.00 $
+// $Author: ghost $
+// $Date: Thu, 17 Mar 2022 04:53:31 PM $
+//
+
+//GEN REG ADDR/OFFSET/MASK
+
+#ifndef __CV180X_REG_FMUX_GPIO_H__
+#define __CV180X_REG_FMUX_GPIO_H__
+
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CLK  0x0
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CMD  0x4
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D0  0x8
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D1  0xc
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D2  0x10
+#define  FMUX_GPIO_REG_IOCTRL_SD0_D3  0x14
+#define  FMUX_GPIO_REG_IOCTRL_SD0_CD  0x18
+#define  FMUX_GPIO_REG_IOCTRL_SD0_PWR_EN  0x1c
+#define  FMUX_GPIO_REG_IOCTRL_SPK_EN  0x20
+#define  FMUX_GPIO_REG_IOCTRL_UART0_TX  0x24
+#define  FMUX_GPIO_REG_IOCTRL_UART0_RX  0x28
+#define  FMUX_GPIO_REG_IOCTRL_SPINOR_HOLD_X  0x2c
+#define  FMUX_GPIO_REG_IOCTRL_SPINOR_SCK  0x30
+#define  FMUX_GPIO_REG_IOCTRL_SPINOR_MOSI  0x34
+#define  FMUX_GPIO_REG_IOCTRL_SPINOR_WP_X  0x38
+#define  FMUX_GPIO_REG_IOCTRL_SPINOR_MISO  0x3c
+#define  FMUX_GPIO_REG_IOCTRL_SPINOR_CS_X  0x40
+#define  FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TMS  0x44
+#define  FMUX_GPIO_REG_IOCTRL_JTAG_CPU_TCK  0x48
+#define  FMUX_GPIO_REG_IOCTRL_IIC0_SCL  0x4c
+#define  FMUX_GPIO_REG_IOCTRL_IIC0_SDA  0x50
+#define  FMUX_GPIO_REG_IOCTRL_AUX0  0x54
+#define  FMUX_GPIO_REG_IOCTRL_GPIO_ZQ  0x58
+#define  FMUX_GPIO_REG_IOCTRL_PWR_VBAT_DET  0x5c
+#define  FMUX_GPIO_REG_IOCTRL_PWR_RSTN  0x60
+#define  FMUX_GPIO_REG_IOCTRL_PWR_SEQ1  0x64
+#define  FMUX_GPIO_REG_IOCTRL_PWR_SEQ2  0x68
+#define  FMUX_GPIO_REG_IOCTRL_PWR_WAKEUP0  0x6c
+#define  FMUX_GPIO_REG_IOCTRL_PWR_BUTTON1  0x70
+#define  FMUX_GPIO_REG_IOCTRL_XTAL_XIN  0x74
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO0  0x78
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO1  0x7c
+#define  FMUX_GPIO_REG_IOCTRL_PWR_GPIO2  0x80
+#define  FMUX_GPIO_REG_IOCTRL_SD1_GPIO1  0x84
+#define  FMUX_GPIO_REG_IOCTRL_SD1_GPIO0  0x88
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D3  0x8c
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D2  0x90
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D1  0x94
+#define  FMUX_GPIO_REG_IOCTRL_SD1_D0  0x98
+#define  FMUX_GPIO_REG_IOCTRL_SD1_CMD  0x9c
+#define  FMUX_GPIO_REG_IOCTRL_SD1_CLK  0xa0
+#define  FMUX_GPIO_REG_IOCTRL_PWM0_BUCK  0xa4
+#define  FMUX_GPIO_REG_IOCTRL_ADC1  0xa8
+#define  FMUX_GPIO_REG_IOCTRL_USB_VBUS_DET  0xac
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MISO  0xb0
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_MOSI  0xb4
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_CS  0xb8
+#define  FMUX_GPIO_REG_IOCTRL_MUX_SPI1_SCK  0xbc
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXP  0xc0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_TXM  0xc4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXP  0xc8
+#define  FMUX_GPIO_REG_IOCTRL_PAD_ETH_RXM  0xcc
+#define  FMUX_GPIO_REG_IOCTRL_GPIO_RTX  0xd0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4N  0xd4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX4P  0xd8
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3N  0xdc
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX3P  0xe0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2N  0xe4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX2P  0xe8
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1N  0xec
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX1P  0xf0
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0N  0xf4
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPIRX0P  0xf8
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM2  0xfc
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP2  0x100
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM1  0x104
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP1  0x108
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXM0  0x10c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_MIPI_TXP0  0x110
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE0  0x114
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE1  0x118
+#define  FMUX_GPIO_REG_IOCTRL_PKG_TYPE2  0x11c
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINL_MIC  0x120
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AINR_MIC  0x124
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTL  0x128
+#define  FMUX_GPIO_REG_IOCTRL_PAD_AUD_AOUTR  0x12c
+#define  FMUX_GPIO_REG_DEVMATRIX_UART0_IP_SEL  0x1d4
+#define  FMUX_GPIO_REG_DEVMATRIX_UART1_IP_SEL  0x1d8
+#define  FMUX_GPIO_REG_DEVMATRIX_UART2_IP_SEL  0x1dc
+#define  FMUX_GPIO_REG_DEVMATRIX_UART3_IP_SEL  0x1e0
+#define  FMUX_GPIO_REG_DEVMATRIX_UART4_IP_SEL  0x1e4
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK   0x0
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD   0x4
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CMD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D0   0x8
+#define  FMUX_GPIO_FUNCSEL_SD0_D0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D1   0xc
+#define  FMUX_GPIO_FUNCSEL_SD0_D1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D2   0x10
+#define  FMUX_GPIO_FUNCSEL_SD0_D2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_D3   0x14
+#define  FMUX_GPIO_FUNCSEL_SD0_D3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_D3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_CD   0x18
+#define  FMUX_GPIO_FUNCSEL_SD0_CD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_CD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN   0x1c
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD0_PWR_EN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPK_EN   0x20
+#define  FMUX_GPIO_FUNCSEL_SPK_EN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPK_EN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART0_TX   0x24
+#define  FMUX_GPIO_FUNCSEL_UART0_TX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART0_TX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_UART0_RX   0x28
+#define  FMUX_GPIO_FUNCSEL_UART0_RX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_UART0_RX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X   0x2c
+#define  FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPINOR_HOLD_X_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPINOR_SCK   0x30
+#define  FMUX_GPIO_FUNCSEL_SPINOR_SCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPINOR_SCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPINOR_MOSI   0x34
+#define  FMUX_GPIO_FUNCSEL_SPINOR_MOSI_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPINOR_MOSI_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPINOR_WP_X   0x38
+#define  FMUX_GPIO_FUNCSEL_SPINOR_WP_X_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPINOR_WP_X_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPINOR_MISO   0x3c
+#define  FMUX_GPIO_FUNCSEL_SPINOR_MISO_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPINOR_MISO_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SPINOR_CS_X   0x40
+#define  FMUX_GPIO_FUNCSEL_SPINOR_CS_X_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SPINOR_CS_X_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS   0x44
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TMS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK   0x48
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_JTAG_CPU_TCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL   0x4c
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC0_SCL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA   0x50
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_IIC0_SDA_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_AUX0   0x54
+#define  FMUX_GPIO_FUNCSEL_AUX0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_AUX0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ   0x58
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_GPIO_ZQ_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET   0x5c
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_VBAT_DET_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN   0x60
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_RSTN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1   0x64
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2   0x68
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_SEQ2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0   0x6c
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_WAKEUP0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1   0x70
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_BUTTON1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN   0x74
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_XTAL_XIN_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0   0x78
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1   0x7c
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2   0x80
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWR_GPIO2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_GPIO1   0x84
+#define  FMUX_GPIO_FUNCSEL_SD1_GPIO1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_GPIO1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_GPIO0   0x88
+#define  FMUX_GPIO_FUNCSEL_SD1_GPIO0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_GPIO0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D3   0x8c
+#define  FMUX_GPIO_FUNCSEL_SD1_D3_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D3_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D2   0x90
+#define  FMUX_GPIO_FUNCSEL_SD1_D2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D1   0x94
+#define  FMUX_GPIO_FUNCSEL_SD1_D1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_D0   0x98
+#define  FMUX_GPIO_FUNCSEL_SD1_D0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_D0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD   0x9c
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_CMD_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK   0xa0
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_SD1_CLK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK   0xa4
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PWM0_BUCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_ADC1   0xa8
+#define  FMUX_GPIO_FUNCSEL_ADC1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_ADC1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET   0xac
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_USB_VBUS_DET_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO   0xb0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MISO_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI   0xb4
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_MOSI_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS   0xb8
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_CS_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK   0xbc
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_MUX_SPI1_SCK_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP   0xc0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXP_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM   0xc4
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_TXM_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP   0xc8
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXP_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM   0xcc
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_ETH_RXM_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX   0xd0
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_GPIO_RTX_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N   0xd4
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P   0xd8
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX4P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N   0xdc
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P   0xe0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX3P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N   0xe4
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P   0xe8
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX2P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N   0xec
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P   0xf0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX1P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N   0xf4
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0N_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P   0xf8
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPIRX0P_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2   0xfc
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2   0x100
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1   0x104
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1   0x108
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0   0x10c
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXM0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0   0x110
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_MIPI_TXP0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0   0x114
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE0_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1   0x118
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE1_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2   0x11c
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PKG_TYPE2_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC   0x120
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINL_MIC_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC   0x124
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AINR_MIC_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL   0x128
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTL_MASK   0x7
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR   0x12c
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_OFFSET 0
+#define  FMUX_GPIO_FUNCSEL_PAD_AUD_AOUTR_MASK   0x7
+#define  FMUX_GPIO_MUX_UART0_IP_SEL   0x1d4
+#define  FMUX_GPIO_MUX_UART0_IP_SEL_OFFSET 0
+#define  FMUX_GPIO_MUX_UART0_IP_SEL_MASK   0x7
+#define  FMUX_GPIO_MUX_UART1_IP_SEL   0x1d8
+#define  FMUX_GPIO_MUX_UART1_IP_SEL_OFFSET 0
+#define  FMUX_GPIO_MUX_UART1_IP_SEL_MASK   0x7
+#define  FMUX_GPIO_MUX_UART2_IP_SEL   0x1dc
+#define  FMUX_GPIO_MUX_UART2_IP_SEL_OFFSET 0
+#define  FMUX_GPIO_MUX_UART2_IP_SEL_MASK   0x7
+#define  FMUX_GPIO_MUX_UART3_IP_SEL   0x1e0
+#define  FMUX_GPIO_MUX_UART3_IP_SEL_OFFSET 0
+#define  FMUX_GPIO_MUX_UART3_IP_SEL_MASK   0x7
+#define  FMUX_GPIO_MUX_UART4_IP_SEL   0x1e4
+#define  FMUX_GPIO_MUX_UART4_IP_SEL_OFFSET 0
+#define  FMUX_GPIO_MUX_UART4_IP_SEL_MASK   0x7
+
+#endif /* __CV180X_REG_FMUX_GPIO_H__ */
--- a/bsp/cvitek/drivers/cv1800b/mmio.h
+++ b/bsp/cvitek/drivers/cv1800b/mmio.h
@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MMIO_H__
+#define __MMIO_H__
+#include <stdint.h>
+#include "types.h"
+
+#define __raw_readb(a)        (*(volatile unsigned char *)(a))
+#define __raw_readw(a)        (*(volatile unsigned short *)(a))
+#define __raw_readl(a)        (*(volatile unsigned int *)(a))
+#define __raw_readq(a)        (*(volatile unsigned long long *)(a))
+
+#define __raw_writeb(v,a)      (*(volatile unsigned char *)(a) = (v))
+#define __raw_writew(v,a)      (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a)      (*(volatile unsigned int *)(a) = (v))
+#define __raw_writeq(v,a)      (*(volatile unsigned long long *)(a) = (v))
+
+/*
+ * I/O memory access primitives. Reads are ordered relative to any
+ * following Normal memory access. Writes are ordered relative to any prior
+ * Normal memory access.  The memory barriers here are necessary as RISC-V
+ * doesn't define any ordering between the memory space and the I/O space.
+ */
+#define __io_br()   do {} while (0)
+#define __io_ar(v)  __asm__ __volatile__ ("fence i,r" : : : "memory")
+#define __io_bw()   __asm__ __volatile__ ("fence w,o" : : : "memory")
+//#define __io_aw()   mmiowb_set_pending()
+#define __io_aw()   do {} while (0)
+
+#define readb(c)    ({ u8  __v; __io_br(); __v = __raw_readb(c); __io_ar(__v); __v; })
+#define readw(c)    ({ u16 __v; __io_br(); __v = __raw_readw(c); __io_ar(__v); __v; })
+#define readl(c)    ({ u32 __v; __io_br(); __v = __raw_readl(c); __io_ar(__v); __v; })
+
+#define writeb(v, c)    ({ __io_bw(); __raw_writeb((v), (c)); __io_aw(); })
+#define writew(v, c)    ({ __io_bw(); __raw_writew((v), (c)); __io_aw(); })
+#define writel(v, c)    ({ __io_bw(); __raw_writel((v), (c)); __io_aw(); })
+
+
+#ifdef CONFIG_64BIT
+#define readq(c)    ({ u64 __v; __io_br(); __v = __raw_readq(c); __io_ar(__v); __v; })
+#define writeq(v, c)    ({ __io_bw(); __raw_writeq((v), (c)); __io_aw(); })
+#endif // CONFIG_64BIT
+
+/*
+#define __raw_readb(a)        (*(volatile unsigned char *)(a))
+#define __raw_readw(a)        (*(volatile unsigned short *)(a))
+#define __raw_readl(a)        (*(volatile unsigned int *)(a))
+#define __raw_readq(a)        (*(volatile unsigned long long *)(a))
+
+#define __raw_writeb(v,a)      (*(volatile unsigned char *)(a) = (v))
+#define __raw_writew(v,a)      (*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a)      (*(volatile unsigned int *)(a) = (v))
+#define __raw_writeq(v,a)      (*(volatile unsigned long long *)(a) = (v))
+
+#define readb(a)        __raw_readb(a)
+#define readw(a)        __raw_readw(a)
+#define readl(a)        __raw_readl(a)
+#define readq(a)        __raw_readq(a)
+
+#define writeb(v, a)        __raw_writeb(v,a)
+#define writew(v, a)        __raw_writew(v,a)
+#define writel(v, a)        __raw_writel(v,a)
+#define writeq(v, a)        __raw_writeq(v,a)
+
+#define cpu_write8(a, v)    writeb(a, v)
+#define cpu_write16(a, v)   writew(a, v)
+#define cpu_write32(a, v)   writel(a, v)
+*/
+
+#define mmio_wr32 mmio_write_32
+#define mmio_rd32 mmio_read_32
+
+static inline void mmio_write_8(uintptr_t addr, uint8_t value)
+{
+    writeb(value, (void *) addr);
+}
+
+static inline uint8_t mmio_read_8(uintptr_t addr)
+{
+    return readb((void *) addr);
+}
+
+static inline void mmio_write_16(uintptr_t addr, uint16_t value)
+{
+    writew(value, (void *) addr);
+}
+
+static inline uint16_t mmio_read_16(uintptr_t addr)
+{
+    return readw((void *) addr);
+}
+
+static inline void mmio_write_32(uintptr_t addr, uint32_t value)
+{
+    writel(value, (void *) addr);
+}
+
+static inline uint32_t mmio_read_32(uintptr_t addr)
+{
+    return readl((void *) addr);
+}
+
+static inline void mmio_write_64(uintptr_t addr, uint64_t value)
+{
+    writeq(value, (void *) addr);
+}
+
+static inline uint64_t mmio_read_64(uintptr_t addr)
+{
+    return readq((void *) addr);
+}
+
+static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear)
+{
+    writel(readl((void *) addr) & ~clear , (void *) addr);
+}
+
+static inline void mmio_setbits_32(uintptr_t addr, uint32_t set)
+{
+    writel(readl((void *) addr) | set , (void *) addr);
+}
+
+static inline void mmio_clrsetbits_32(uintptr_t addr, uint32_t clear,
+                      uint32_t set)
+{
+    writel((readl((void *) addr) & ~clear) | set , (void *) addr);
+}
+
+/* from Linux usage */
+#define ioremap(a, l)       (a)
+
+#define _reg_read(addr)     mmio_read_32((addr))
+#define _reg_write(addr, data)  mmio_write_32((addr), (data))
+#define _reg_write_mask(addr, mask, data) mmio_clrsetbits_32(addr, mask, data)
+
+#define ioread8 readb
+#define ioread16 readw
+#define ioread32 readl
+#define ioread64 readq
+
+#define iowrite8 writeb
+#define iowrite16 writew
+#define iowrite32 writel
+#define iowrite64 writeq
+
+#endif /* __MMIO_H__ */
--- a/bsp/cvitek/drivers/cv1800b/pinctrl.h
+++ b/bsp/cvitek/drivers/cv1800b/pinctrl.h
@ -0,0 +1,34 @@
+/*
+ * Copyright (C) Cvitek Co., Ltd. 2019-2020. All rights reserved.
+ *
+ * File Name: pinctrl.h
+ * Description:
+ */
+
+#ifndef __PINCTRL_CV180X_H__
+#define __PINCTRL_CV180X_H__
+
+#include "cv180x_pinlist_swconfig.h"
+#include "cv180x_reg_fmux_gpio.h"
+
+#define  PAD_MIPI_TXM4__MIPI_TXM4 0
+#define  PAD_MIPI_TXP4__MIPI_TXP4 0
+#define  PAD_MIPI_TXM3__MIPI_TXM3 0
+#define  PAD_MIPI_TXP3__MIPI_TXP3 0
+#define  PAD_MIPI_TXM2__MIPI_TXM2 0
+#define  PAD_MIPI_TXP2__MIPI_TXP2 0
+#define  PAD_MIPI_TXM1__MIPI_TXM1 0
+#define  PAD_MIPI_TXP1__MIPI_TXP1 0
+#define  PAD_MIPI_TXM0__MIPI_TXM0 0
+#define  PAD_MIPI_TXP0__MIPI_TXP0 0
+
+#define PINMUX_BASE 0x03001000
+#define PINMUX_MASK(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK
+#define PINMUX_OFFSET(PIN_NAME) FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET
+#define PINMUX_VALUE(PIN_NAME, FUNC_NAME) PIN_NAME##__##FUNC_NAME
+#define PINMUX_CONFIG(PIN_NAME, FUNC_NAME) \
+        mmio_clrsetbits_32(PINMUX_BASE + FMUX_GPIO_FUNCSEL_##PIN_NAME, \
+            FMUX_GPIO_FUNCSEL_##PIN_NAME##_MASK << FMUX_GPIO_FUNCSEL_##PIN_NAME##_OFFSET, \
+            PIN_NAME##__##FUNC_NAME)
+
+#endif /* __PINCTRL_CV180X_H__ */
--- a/bsp/cvitek/drivers/cv1800b/types.h
+++ b/bsp/cvitek/drivers/cv1800b/types.h
@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_TYPES_H
+#define _LINUX_TYPES_H
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_64BIT
+typedef unsigned long       uintptr_t;
+typedef unsigned long       size_t;
+/* bsd */
+typedef unsigned char       u_char;
+typedef unsigned short      u_short;
+typedef unsigned int        u_int;
+typedef unsigned long       u_long;
+
+/* sysv */
+typedef unsigned char       unchar;
+typedef unsigned short      ushort;
+typedef unsigned int        uint;
+typedef unsigned long       ulong;
+
+typedef signed char         s8;
+typedef signed short        s16;
+typedef signed int          s32;
+typedef signed long         s64;
+
+typedef unsigned char       u8;
+typedef unsigned short      u16;
+typedef unsigned int        u32;
+typedef unsigned long       u64;
+
+typedef signed char         __s8;
+typedef signed short        __s16;
+typedef signed int          __s32;
+typedef signed long         __s64;
+
+typedef unsigned char       __u8;
+typedef unsigned short      __u16;
+typedef unsigned int        __u32;
+typedef unsigned long       __u64;
+
+#endif /*  CONFIG_64BIT */
+#endif /*  __ASSEMBLY__ */
+#endif /* _LINUX_TYPES_H */
--- a/bsp/cv1800b/drivers/drv_gpio.c
+++ b/bsp/cv1800b/drivers/drv_gpio.c
--- a/bsp/cv1800b/drivers/drv_gpio.h
+++ b/bsp/cv1800b/drivers/drv_gpio.h
--- a/bsp/cv1800b/drivers/drv_uart.c
+++ b/bsp/cv1800b/drivers/drv_uart.c
@ -1,12 +1,11 @@
 /*
- * Copyright (c) 2006-2023, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2023/06/25     flyingcys    first version
- * 2023/10/25     flyingcys    update uart configure
 */
 #include <rthw.h>
 #include <rtthread.h>
@ -250,20 +249,34 @@ int rt_hw_uart_init(void)
    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial##no, "uart" #no);

 #ifdef RT_USING_UART0
+    PINMUX_CONFIG(UART0_RX, UART0_RX);
+    PINMUX_CONFIG(UART0_TX, UART0_TX);
    BSP_INSTALL_UART_DEVICE(0);
 #endif

 #ifdef RT_USING_UART1
+    PINMUX_CONFIG(IIC0_SDA, UART1_RX);
+    PINMUX_CONFIG(IIC0_SCL, UART1_TX);
    BSP_INSTALL_UART_DEVICE(1);
 #endif

 #ifdef RT_USING_UART2
+    PINMUX_CONFIG(SD1_D1, UART2_RX);
+    PINMUX_CONFIG(SD1_D2, UART2_TX);
    BSP_INSTALL_UART_DEVICE(2);
 #endif

 #ifdef RT_USING_UART3
+    PINMUX_CONFIG(SD1_D1, UART3_RX);
+    PINMUX_CONFIG(SD1_D2, UART3_TX);
    BSP_INSTALL_UART_DEVICE(3);
 #endif

+#ifdef RT_USING_UART4
+    PINMUX_CONFIG(SD1_GP0, UART4_RX);
+    PINMUX_CONFIG(SD1_GP1, UART4_TX);
+    BSP_INSTALL_UART_DEVICE(4);
+#endif
+
    return 0;
 }
--- a/bsp/cv1800b/drivers/drv_uart.h
+++ b/bsp/cv1800b/drivers/drv_uart.h
@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2023, RT-Thread Development Team
+ * Copyright (c) 2006-2024, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@ -14,6 +14,9 @@
 #include "rtdevice.h"
 #include <rthw.h>

+#include "pinctrl.h"
+#include "mmio.h"
+
 #define UART_REG_SHIFT      0x2     /* Register Shift*/
 #define UART_INPUT_CLK      25000000

@ -23,7 +26,6 @@
 #define UART3_BASE          0x04170000
 #define UART4_BASE          0x041C0000

-#define UART_IRQ_BASE       (44)
 #define UART0_IRQ           (UART_IRQ_BASE + 0)
 #define UART1_IRQ           (UART_IRQ_BASE + 1)
 #define UART2_IRQ           (UART_IRQ_BASE + 2)
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin
+++ b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/bl2.bin
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin
+++ b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.bin
@ -0,0 +1 @@
+<EFBFBD>ｭﾞ
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env
+++ b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/blmacros.env
@ -0,0 +1,2 @@
+MONITOR_RUNADDR=0x0000000080000000
+BLCP_2ND_RUNADDR=0x0000000083f40000
--- a/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin
+++ b/bsp/cvitek/pre-build/fsbl/build/cv1800b_milkv_duo_sd/chip_conf.bin
--- a/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h
+++ b/bsp/cvitek/pre-build/fsbl/build/cvi_board_memmap.h
@ -0,0 +1,35 @@
+#ifndef __BOARD_MMAP__83494f74__
+#define __BOARD_MMAP__83494f74__
+
+#define CONFIG_SYS_TEXT_BASE 0x80200000  /* offset 2.0MiB */
+#define CVIMMAP_ATF_SIZE 0x80000  /* 512.0KiB */
+#define CVIMMAP_BOOTLOGO_ADDR 0x82473000  /* offset 36.44921875MiB */
+#define CVIMMAP_BOOTLOGO_SIZE 0x0  /* 0.0KiB */
+#define CVIMMAP_CONFIG_SYS_INIT_SP_ADDR 0x82300000  /* offset 35.0MiB */
+#define CVIMMAP_CVI_UPDATE_HEADER_ADDR 0x813ffc00  /* offset 19.9990234375MiB */
+#define CVIMMAP_CVI_UPDATE_HEADER_SIZE 0x400  /* 1.0KiB */
+#define CVIMMAP_DRAM_BASE 0x80000000  /* offset 0.0KiB */
+#define CVIMMAP_DRAM_SIZE 0x4000000  /* 64.0MiB */
+#define CVIMMAP_FREERTOS_ADDR 0x83f40000  /* offset 63.25MiB */
+#define CVIMMAP_FREERTOS_RESERVED_ION_SIZE 0x0  /* 0.0KiB */
+#define CVIMMAP_FREERTOS_SIZE 0xc0000  /* 768.0KiB */
+#define CVIMMAP_FSBL_C906L_START_ADDR 0x83f40000  /* offset 63.25MiB */
+#define CVIMMAP_FSBL_UNZIP_ADDR 0x81400000  /* offset 20.0MiB */
+#define CVIMMAP_FSBL_UNZIP_SIZE 0xf00000  /* 15.0MiB */
+#define CVIMMAP_H26X_BITSTREAM_ADDR 0x82473000  /* offset 36.44921875MiB */
+#define CVIMMAP_H26X_BITSTREAM_SIZE 0x0  /* 0.0KiB */
+#define CVIMMAP_H26X_ENC_BUFF_ADDR 0x82473000  /* offset 36.44921875MiB */
+#define CVIMMAP_H26X_ENC_BUFF_SIZE 0x0  /* 0.0KiB */
+#define CVIMMAP_ION_ADDR 0x82473000  /* offset 36.44921875MiB */
+#define CVIMMAP_ION_SIZE 0x1acd000  /* 26.80078125MiB */
+#define CVIMMAP_ISP_MEM_BASE_ADDR 0x82473000  /* offset 36.44921875MiB */
+#define CVIMMAP_ISP_MEM_BASE_SIZE 0x0  /* 0.0KiB */
+#define CVIMMAP_KERNEL_MEMORY_ADDR 0x80000000  /* offset 0.0KiB */
+#define CVIMMAP_KERNEL_MEMORY_SIZE 0x3f40000  /* 63.25MiB */
+#define CVIMMAP_MONITOR_ADDR 0x80000000  /* offset 0.0KiB */
+#define CVIMMAP_OPENSBI_FDT_ADDR 0x80080000  /* offset 512.0KiB */
+#define CVIMMAP_OPENSBI_SIZE 0x80000  /* 512.0KiB */
+#define CVIMMAP_UIMAG_ADDR 0x81400000  /* offset 20.0MiB */
+#define CVIMMAP_UIMAG_SIZE 0xf00000  /* 15.0MiB */
+
+#endif /* __BOARD_MMAP__83494f74__ */
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py
+++ b/bsp/cvitek/pre-build/fsbl/plat/cv180x/chip_conf.py
@ -0,0 +1,38 @@
+#!/usr/bin/env python3
+
+import logging
+import struct
+import argparse
+
+CHIP_CONF_CMD_DELAY_MS = 0xFFFFFFFD
+CHIP_CONF_CMD_DELAY_US = 0xFFFFFFFE
+
+CHIP_CONF_SCAN_START_1 = 0xFFFFFFA0
+
+
+def gen_chip_conf(args):
+    logging.info("gen_chip_conf")
+    regs = [
+        (0x0E00000C, 0xA0000001),  # ATF_DBG_REG = 0x0E00000C
+        (0x0E00000C, 0xA0000002),
+        # (CHIP_CONF_CMD_DELAY_MS, 100),
+        # (CHIP_CONF_CMD_DELAY_US, 100),
+        (CHIP_CONF_SCAN_START_1, 0xFFFFFFFF),
+    ]
+
+    chip_conf = b"".join(struct.pack("<II", a, v) for a, v in regs)
+    logging.info("chip_conf=%d bytes", len(chip_conf))
+
+    with open(args.CHIP_CONF, "wb") as fp:
+        fp.write(chip_conf)
+
+
+def main():
+    parser = argparse.ArgumentParser(description="generate test cases")
+    parser.add_argument("CHIP_CONF", type=str)
+    args = parser.parse_args()
+    gen_chip_conf(args)
+
+
+if __name__ == "__main__":
+    main()
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/fipsign.py
+++ b/bsp/cvitek/pre-build/fsbl/plat/cv180x/fipsign.py
@ -0,0 +1,252 @@
+#!/usr/bin/env python3
+# PYTHON_ARGCOMPLETE_OK
+
+import logging
+import argparse
+from struct import unpack
+
+from Crypto.Cipher import AES
+from Crypto.Hash import SHA256
+from Crypto.PublicKey import RSA
+from Crypto.Signature import pkcs1_15
+
+try:
+    import argcomplete
+except ImportError:
+    argcomplete = None
+
+from fiptool import FIP, IMAGE_ALIGN, init_logging
+
+ENCRYPTION_KEY_SIZE = 16
+ENCRYPTION_BLOCK_SIZE = 16
+IV_ZERO = b"\0" * ENCRYPTION_BLOCK_SIZE
+
+
+class SignedFIP(FIP):
+    def __init__(self, root_priv_path, bl_priv_path):
+        super().__init__()
+
+        with open(root_priv_path, "rb") as fp:
+            din = fp.read()
+            self.root_priv = RSA.import_key(din)
+
+        with open(bl_priv_path, "rb") as fp:
+            din = fp.read()
+            self.bl_priv = RSA.import_key(din)
+
+    def read_fip(self, path):
+        super().read_fip(path)
+
+        # Verity the reading of fip.bin
+        with open(path, "rb") as fp:
+            assert fp.read() == self.make()
+
+    def rsa_to_n(self, rsa):
+        return rsa.n.to_bytes(rsa.size_in_bytes(), byteorder="big")
+
+    def print_kpub_hash(self, bytes):
+        bytes_str = ['{:02x}'.format(int(i)) for i in bytes]
+        logging.info("KPUB_HASH:" + "".join(bytes_str))
+
+    def sign_bl_pk(self):
+        self.param1["ROOT_PK"].content = self.rsa_to_n(self.root_priv)
+        kpub_hash = SHA256.new(self.param1["ROOT_PK"].content[:256])
+        self.print_kpub_hash(kpub_hash.digest())
+
+        self.param1["BL_PK"].content = self.rsa_to_n(self.bl_priv)
+
+        digest = SHA256.new(self.rsa_to_n(self.bl_priv))
+
+        sig = pkcs1_15.new(self.root_priv).sign(digest)
+        self.param1["BL_PK_SIG"].content = sig
+
+    def sign_by_bl_priv(self, image):
+        digest = SHA256.new(image)
+        return pkcs1_15.new(self.bl_priv).sign(digest)
+
+    def sign(self):
+        logging.info("sign fip.bin")
+
+        self.param1["FIP_FLAGS"].content = self.FIP_FLAGS_SCS_MASK | self.param1["FIP_FLAGS"].toint()
+
+        self.sign_bl_pk()
+
+        cc = self.param1["CHIP_CONF"].content
+        cc_size = unpack("<I", self.param1["CHIP_CONF_SIZE"].content)[0]
+        logging.debug("CHIP_CONF_SIZE=%#x", cc_size)
+        cc = cc[:cc_size]
+
+        self.param1["CHIP_CONF_SIG"].content = self.sign_by_bl_priv(cc)
+        self.param1["BL2_IMG_SIG"].content = self.sign_by_bl_priv(self.body1["BL2"].content)
+
+        if self.body1["BLCP"].content:
+            logging.debug("sign blcp")
+            self.param1["BLCP_IMG_SIG"].content = self.sign_by_bl_priv(self.body1["BLCP"].content)
+
+        self.sign_fip2()
+
+    def sign_fip2(self):
+        logging.debug("sign_fip2:")
+
+        sig_size = len(self.rsa_to_n(self.bl_priv))
+
+        for name in ["BLCP_2ND", "MONITOR"]:
+            e = self.body2[name]
+            if not e.content:
+                continue
+
+            logging.info("sign %s: len=%#x", name, len(e.content))
+
+            image = bytearray(self.pad(e.content + b"\xCE" * sig_size, IMAGE_ALIGN))
+            sig = self.sign_by_bl_priv(image[:-sig_size])
+            assert sig_size == len(sig)
+            image[-sig_size:] = sig
+
+            e.content = image
+
+        loader_2nd_loadaddr = self.param2["LOADER_2ND_LOADADDR"].toint()
+        if loader_2nd_loadaddr:
+            logging.info("sign %s at %#x", "LOADER_2ND_LOADADDR", loader_2nd_loadaddr)
+
+            # Only data after CKSUM field are signed.
+            # The value CKSUM include signature and is updated later.
+            e = self.body2["LOADER_2ND"]
+            e.content = self.pad(e.content + b"\xCE" * sig_size, IMAGE_ALIGN)
+            # SIZE is after CKSUM, update it before signing
+            self._update_ldr_2nd_hdr()
+
+            image = bytearray(e.content)
+            sig = self.sign_by_bl_priv(image[self.ldr_2nd_hdr["CKSUM"].end : -sig_size])
+            assert sig_size == len(sig)
+            image[-sig_size:] = sig
+
+            e.content = image
+
+
+class EncryptedFIP(SignedFIP):
+    def __init__(self, root_priv_path, bl_priv_path, ldr_ek_path, bl_ek_path):
+        super().__init__(root_priv_path, bl_priv_path)
+
+        with open(ldr_ek_path, "rb") as fp:
+            self.ldr_ek = fp.read()
+
+        with open(bl_ek_path, "rb") as fp:
+            self.bl_ek = fp.read()
+
+    def _aes_encrypt(self, key, plain):
+        return AES.new(key, iv=IV_ZERO, mode=AES.MODE_CBC).encrypt(plain)
+
+    def encrypt(self):
+        logging.debug("encrypt:")
+
+        self.param1["FIP_FLAGS"].content = self.FIP_FLAGS_ENCRYPTED_MASK | self.param1["FIP_FLAGS"].toint()
+
+        self.param1["BL_EK"].content = self._aes_encrypt(self.ldr_ek, self.bl_ek)
+        self.body1["BL2"].content = self._aes_encrypt(self.bl_ek, self.body1["BL2"].content)
+
+        for name in ["BLCP_2ND", "MONITOR"]:
+            e = self.body2[name]
+            if not e.content:
+                continue
+
+            logging.info("encrypt %s: len=%#x", name, len(e.content))
+            e.content = self._aes_encrypt(self.bl_ek, e.content)
+
+        loader_2nd_loadaddr = self.param2["LOADER_2ND_LOADADDR"].toint()
+        if loader_2nd_loadaddr:
+            logging.info("encrypt %s at %#x", "LOADER_2ND_LOADADDR", loader_2nd_loadaddr)
+
+            # Only data after header are encrypted
+            e = self.body2["LOADER_2ND"]
+
+            hdr_size = self._param_size(self.ldr_2nd_hdr)
+            hdr, body = e.content[:hdr_size], e.content[hdr_size:]
+
+            body = self._aes_encrypt(self.bl_ek, body)
+            e.content = hdr + body
+
+
+def sign_fip(args):
+    logging.debug("sign_fip:")
+
+    fip = SignedFIP(args.root_priv, args.bl_priv)
+    fip.read_fip(args.SRC_FIP)
+
+    fip.sign()
+
+    fip_bin = fip.make()
+    fip.print_fip_params()
+    with open(args.DEST_FIP, "wb") as fp:
+        fp.write(fip_bin)
+
+
+def encrypt_fip(args):
+    logging.debug("encrypt_fip:")
+
+    fip = EncryptedFIP(args.root_priv, args.bl_priv, args.ldr_ek, args.bl_ek)
+    fip.read_fip(args.SRC_FIP)
+
+    fip.sign()
+    fip.encrypt()
+
+    fip_bin = fip.make()
+    fip.print_fip_params()
+    with open(args.DEST_FIP, "wb") as fp:
+        fp.write(fip_bin)
+
+
+def parse_args():
+    parser = argparse.ArgumentParser(description="FIP tools")
+
+    parser.add_argument(
+        "-v",
+        "--verbose",
+        help="Increase output verbosity",
+        action="store_const",
+        const=logging.DEBUG,
+        default=logging.INFO,
+    )
+
+    def auto_int(x):
+        return int(x, 0)
+
+    subparsers = parser.add_subparsers(dest="subcmd", help="Sub-command help")
+
+    pr_encrypt = subparsers.add_parser("sign-enc")
+    pr_encrypt.set_defaults(func=encrypt_fip)
+    pr_encrypt.add_argument("--ldr-ek", type=str)
+    pr_encrypt.add_argument("--bl-ek", type=str)
+
+    pr_sign = subparsers.add_parser("sign")
+    pr_sign.set_defaults(func=sign_fip)
+
+    for pr in [pr_sign, pr_encrypt]:
+        pr.add_argument("--root-priv", type=str)
+        pr.add_argument("--bl-priv", type=str)
+        pr.add_argument("SRC_FIP", type=str, help="Source fip.bin")
+        pr.add_argument("DEST_FIP", type=str, help="Signed fip.bin")
+
+    if argcomplete:
+        argcomplete.autocomplete(parser)
+
+    args = parser.parse_args()
+    init_logging(stdout_level=args.verbose)
+    logging.info("PROG: %s", parser.prog)
+
+    if not args.subcmd:
+        parser.print_help()
+        raise SystemExit(1)
+
+    for a, v in sorted(vars(args).items()):
+        logging.debug("%s=%r", a, v)
+
+    return args
+
+
+def main():
+    args = parse_args()
+    args.func(args)
+
+
+if __name__ == "__main__":
+    main()
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/fiptool.py
+++ b/bsp/cvitek/pre-build/fsbl/plat/cv180x/fiptool.py
@ -0,0 +1,802 @@
+#!/usr/bin/env python3
+# PYTHON_ARGCOMPLETE_OK
+
+import sys
+import logging
+import os
+import os.path
+import argparse
+from collections import OrderedDict
+import binascii
+from struct import pack, unpack
+import lzma
+import pprint
+
+
+PYTHON_MIN_VERSION = (3, 5, 2)  # Ubuntu 16.04 LTS contains Python v3.5.2 by default
+
+
+if sys.version_info < PYTHON_MIN_VERSION:
+    print("Python >= %r is required" % (PYTHON_MIN_VERSION,))
+    sys.exit(-1)
+
+
+try:
+    import coloredlogs
+except ImportError:
+    coloredlogs = None
+
+try:
+    import argcomplete
+except ImportError:
+    argcomplete = None
+
+
+LOADER_2ND_MAGIC_ORIG = b"BL33"
+LOADER_2ND_MAGIC_LZMA = b"B3MA"
+LOADER_2ND_MAGIC_LZ4 = b"B3Z4"
+
+LOADER_2ND_MAGIC_LIST = [
+    LOADER_2ND_MAGIC_ORIG,
+    LOADER_2ND_MAGIC_LZMA,
+    LOADER_2ND_MAGIC_LZ4,
+]
+
+IMAGE_ALIGN = 512
+PARAM1_SIZE = 0x1000
+PARAM1_SIZE_WO_SIG = 0x800
+PARAM2_SIZE = 0x1000
+
+
+def round_up(divident, divisor):
+    return ((divident + divisor - 1) // divisor) * divisor
+
+
+def lzma_compress(body):
+    z = lzma.LZMACompressor(lzma.FORMAT_ALONE, preset=lzma.PRESET_EXTREME)
+    compressed = z.compress(body)
+    compressed += z.flush()
+
+    return compressed
+
+
+def lz4_compress(body):
+    try:
+        import lz4.frame
+    except ImportError:
+        logging.error("lz4 is not installed. Run 'pip install lz4'.")
+        raise
+
+    compressed = lz4.frame.compress(body)
+    return compressed
+
+
+class Entry:
+    __slots__ = "name", "type", "addr", "_content", "entry_size"
+
+    def __init__(self):
+        self.addr = None
+        self._content = None
+
+    @property
+    def end(self):
+        return self.addr + self.entry_size
+
+    @property
+    def content(self):
+        return self._content
+
+    @content.setter
+    def content(self, value):
+        if type(value) == int:
+            value = value.to_bytes(self.entry_size, "little")
+
+        if self.entry_size is not None:
+            if len(value) > self.entry_size:
+                raise ValueError("%s (%d bytes) must <= %#r" % (self.name, len(value), self.entry_size))
+            value = value + b"\0" * (self.entry_size - len(value))
+
+        self._content = value
+
+    @classmethod
+    def make(cls, name, entry_size, _type, init=None):
+        entry = Entry()
+        entry.name = name
+        entry.type = _type
+        entry.entry_size = entry_size
+
+        if type(init) in (bytes, bytearray):
+            entry.content = bytes(init)
+        elif entry_size is not None:
+            entry.content = b"\0" * entry.entry_size
+        else:
+            entry.content = b""
+
+        return (name, entry)
+
+    def toint(self):
+        if self.type != int:
+            raise TypeError("%s is not int type" % self.name)
+
+        return int.from_bytes(self.content, "little")
+
+    def tostr(self):
+        v = self.content
+        if self.type == int:
+            v = "%#08x" % self.toint()
+        elif type(self.content) in [bytes, bytearray]:
+            v = v.hex()
+            if len(v) > 32:
+                v = v[:32] + "..."
+
+        return v
+
+    def __str__(self):
+        v = self.tostr()
+        return "<%s=%s (%dbytes)>" % (self.name, v, self.entry_size)
+
+    def __repr__(self):
+        v = self.tostr()
+        return "<%s: a=%#x s=%#x c=%s %r>" % (self.name, self.addr, self.entry_size, v, self.type)
+
+
+class FIP:
+    param1 = OrderedDict(
+        [
+            Entry.make("MAGIC1", 8, int, b"CVBL01\n\0"),
+            Entry.make("MAGIC2", 4, int),
+            Entry.make("PARAM_CKSUM", 4, int),
+            Entry.make("NAND_INFO", 128, int),
+            Entry.make("NOR_INFO", 36, int),
+            Entry.make("FIP_FLAGS", 8, int),
+            Entry.make("CHIP_CONF_SIZE", 4, int),
+            Entry.make("BLCP_IMG_CKSUM", 4, int),
+            Entry.make("BLCP_IMG_SIZE", 4, int),
+            Entry.make("BLCP_IMG_RUNADDR", 4, int),
+            Entry.make("BLCP_PARAM_LOADADDR", 4, int),
+            Entry.make("BLCP_PARAM_SIZE", 4, int),
+            Entry.make("BL2_IMG_CKSUM", 4, int),
+            Entry.make("BL2_IMG_SIZE", 4, int),
+            Entry.make("BLD_IMG_SIZE", 4, int),
+            Entry.make("PARAM2_LOADADDR", 4, int),
+            Entry.make("RESERVED1", 4, int),
+            Entry.make("CHIP_CONF", 760, bytes),
+            Entry.make("BL_EK", 32, bytes),
+            Entry.make("ROOT_PK", 512, bytes),
+            Entry.make("BL_PK", 512, bytes),
+            Entry.make("BL_PK_SIG", 512, bytes),
+            Entry.make("CHIP_CONF_SIG", 512, bytes),
+            Entry.make("BL2_IMG_SIG", 512, bytes),
+            Entry.make("BLCP_IMG_SIG", 512, bytes),
+        ]
+    )
+
+    body1 = OrderedDict(
+        [
+            Entry.make("BLCP", None, bytes),
+            Entry.make("BL2", None, bytes),
+        ]
+    )
+
+    param2 = OrderedDict(
+        [
+            Entry.make("MAGIC1", 8, int, b"CVLD02\n\0"),
+            Entry.make("PARAM2_CKSUM", 4, int),
+            Entry.make("RESERVED1", 4, bytes),
+            # DDR param
+            Entry.make("DDR_PARAM_CKSUM", 4, int),
+            Entry.make("DDR_PARAM_LOADADDR", 4, int),
+            Entry.make("DDR_PARAM_SIZE", 4, int),
+            Entry.make("DDR_PARAM_RESERVED", 4, int),
+            # BLCP_2ND
+            Entry.make("BLCP_2ND_CKSUM", 4, int),
+            Entry.make("BLCP_2ND_LOADADDR", 4, int),
+            Entry.make("BLCP_2ND_SIZE", 4, int),
+            Entry.make("BLCP_2ND_RUNADDR", 4, int),
+            # ATF-BL31 or OpenSBI
+            Entry.make("MONITOR_CKSUM", 4, int),
+            Entry.make("MONITOR_LOADADDR", 4, int),
+            Entry.make("MONITOR_SIZE", 4, int),
+            Entry.make("MONITOR_RUNADDR", 4, int),
+            # u-boot
+            Entry.make("LOADER_2ND_RESERVED0", 4, int),
+            Entry.make("LOADER_2ND_LOADADDR", 4, int),
+            Entry.make("LOADER_2ND_RESERVED1", 4, int),
+            Entry.make("LOADER_2ND_RESERVED2", 4, int),
+            # Reserved
+            Entry.make("RESERVED_LAST", 4096 - 16 * 5, bytes),
+        ]
+    )
+
+    body2 = OrderedDict(
+        [
+            Entry.make("DDR_PARAM", None, bytes),
+            Entry.make("BLCP_2ND", None, bytes),
+            Entry.make("MONITOR", None, bytes),
+            Entry.make("LOADER_2ND", None, bytes),
+        ]
+    )
+
+    ldr_2nd_hdr = OrderedDict(
+        [
+            Entry.make("JUMP0", 4, int),
+            Entry.make("MAGIC", 4, int),
+            Entry.make("CKSUM", 4, int),
+            Entry.make("SIZE", 4, int),
+            Entry.make("RUNADDR", 8, int),
+            Entry.make("RESERVED1", 4, int),
+            Entry.make("RESERVED2", 4, int),
+        ]
+    )
+
+    FIP_FLAGS_SCS_MASK = 0x000c
+    FIP_FLAGS_ENCRYPTED_MASK = 0x0030
+
+    def _param_size(self, param):
+        return max((e.end for e in param.values()))
+
+    def _gen_param(self):
+        addr = 0
+        for entry in self.param1.values():
+            entry.addr = addr
+            addr += entry.entry_size
+
+        assert PARAM1_SIZE_WO_SIG == self.param1["BL_PK_SIG"].addr
+
+        addr = 0
+        for entry in self.param2.values():
+            entry.addr = addr
+            addr += entry.entry_size
+
+        assert PARAM2_SIZE == self.param2["RESERVED_LAST"].addr + self.param2["RESERVED_LAST"].entry_size
+
+        addr = 0
+        for entry in self.ldr_2nd_hdr.values():
+            entry.addr = addr
+            addr += entry.entry_size
+
+    def __init__(self):
+        self.compress_algo = None
+        self._gen_param()
+
+    def image_crc(self, image):
+        crc = binascii.crc_hqx(image, 0)
+        crc = pack("<H", crc) + b"\xFE\xCA"
+        return crc
+
+    def pad(self, data, block_size):
+        if type(data) not in [bytearray, bytes]:
+            raise TypeError("Need bytearray or bytes")
+
+        r = len(data) % block_size
+        if r:
+            data += b"\0" * (block_size - r)
+
+        return data
+
+    def _pprint_attr(self, name):
+        v = getattr(self, name)
+
+        if type(v) == OrderedDict:
+            v = list(v.values())
+        logging.info("print(%s):\n" % name + pprint.pformat(v, 4, 140))
+
+    def print_fip_params(self):
+        self._pprint_attr("param1")
+        self._pprint_attr("param2")
+        self._pprint_attr("ldr_2nd_hdr")
+
+    def read_fip(self, path):
+        logging.debug("read_fip:")
+
+        with open(path, "rb") as fp:
+            fip_bin = fp.read()
+
+        fip_bin = bytearray(fip_bin)
+
+        e = self.param1["MAGIC1"]
+        if fip_bin[e.addr : e.end] != e.content:
+            raise ValueError("Unknown magic %r" % fip_bin[e.addr : e.end])
+
+        # Read param1 from fip.bin
+        for e in self.param1.values():
+            e.content = fip_bin[e.addr : e.end]
+
+        self.read_end = PARAM1_SIZE
+
+        # Read BLCP
+        e = self.param1["BLCP_IMG_SIZE"]
+        blcp_img_size = unpack("<I", fip_bin[e.addr : e.end])[0]
+        if blcp_img_size:
+            start = self.read_end
+            self.read_end = start + blcp_img_size
+            self.body1["BLCP"].content = fip_bin[start : self.read_end]
+
+        # Read FSBL as BL2
+        e = self.param1["BL2_IMG_SIZE"]
+        bl2_img_size = unpack("<I", fip_bin[e.addr : e.end])[0]
+        if bl2_img_size:
+            start = self.read_end
+            self.read_end = start + bl2_img_size
+            self.body1["BL2"].content = fip_bin[start : self.read_end]
+
+        logging.info("read_fip end=%#x", self.read_end)
+        self.rest_fip = fip_bin[self.read_end :]
+
+        self.read_fip2(fip_bin)
+
+    def read_fip2(self, fip_bin):
+        param2_loadaddr = self.param1["PARAM2_LOADADDR"].toint()
+        param2_bin = fip_bin[param2_loadaddr : param2_loadaddr + PARAM2_SIZE]
+
+        for e in self.param2.values():
+            e.content = param2_bin[e.addr : e.end]
+
+        self.read_end = param2_loadaddr + PARAM2_SIZE
+
+        # Read DDR_PARAM, BLCP_2ND, and MONITOR
+        for name in ["DDR_PARAM", "BLCP_2ND", "MONITOR"]:
+            size = self.param2[name + "_SIZE"].toint()
+            loadaddr = self.param2[name + "_LOADADDR"].toint()
+            self.body2[name].content = fip_bin[loadaddr : loadaddr + size]
+            self.read_end = loadaddr + size
+
+        # Read LOADER_2ND
+        loader_2nd_loadaddr = self.param2["LOADER_2ND_LOADADDR"].toint()
+        if loader_2nd_loadaddr:
+            self.read_loader_2nd(fip_bin)
+
+        logging.info("read_fip2 end=%#x", self.read_end)
+        self.rest_fip = fip_bin[self.read_end :]
+
+    def read_loader_2nd(self, fip_bin):
+        loader_2nd_loadaddr = self.param2["LOADER_2ND_LOADADDR"].toint()
+
+        self._parse_ldr_2nd_hdr(fip_bin[loader_2nd_loadaddr:])
+
+        if self.ldr_2nd_hdr["MAGIC"].content not in LOADER_2ND_MAGIC_LIST:
+            raise ValueError("%r" % self.ldr_2nd_hdr["MAGIC"].content)
+
+        ldr_2nd_size = self.ldr_2nd_hdr["SIZE"].toint()
+
+        self.body2["LOADER_2ND"].content = fip_bin[loader_2nd_loadaddr : loader_2nd_loadaddr + ldr_2nd_size]
+
+        self.read_end = loader_2nd_loadaddr + ldr_2nd_size
+        self.rest_fip = fip_bin[self.read_end :]
+
+    def add_chip_conf(self, args):
+        logging.debug("add_chip_conf:")
+
+        with open(args.CHIP_CONF, "rb") as fp:
+            image = fp.read()
+
+        if image.startswith(b"APLB"):
+            image = image[8:]  # strip old BLP header
+
+        self.param1["CHIP_CONF"].content = image
+
+    def add_blcp(self, args):
+        logging.debug("add_blcp:")
+
+        with open(args.BLCP, "rb") as fp:
+            image = fp.read()
+
+        image = self.pad(image, IMAGE_ALIGN)
+
+        self.param1["BLCP_IMG_RUNADDR"].content = args.BLCP_IMG_RUNADDR
+        self.body1["BLCP"].content = image
+
+    def add_bl2(self, args):
+        logging.debug("add_bl2:")
+
+        with open(args.BL2, "rb") as fp:
+            image = fp.read()
+
+        bl2_fill = 0
+        if args.BL2_FILL:
+            bl2_fill = args.BL2_FILL
+
+        image += b"\xA9" * (bl2_fill - len(image))
+        image = self.pad(image, IMAGE_ALIGN)
+
+        self.body1["BL2"].content = image
+
+    def add_nor_info(self, args):
+        logging.debug("add_nor_info:")
+        self.param1["NOR_INFO"].content = args.NOR_INFO
+
+    def add_nand_info(self, args):
+        logging.debug("add_nand_info:")
+        self.param1["NAND_INFO"].content = args.NAND_INFO
+
+    def update_param1_cksum(self, image):
+        image = bytearray(image)
+        crc = self.image_crc(image[self.param1["NAND_INFO"].addr : PARAM1_SIZE_WO_SIG])
+
+        param_cksum = self.param1["PARAM_CKSUM"]
+        param_cksum.content = crc
+        image[param_cksum.addr : param_cksum.end] = crc
+        return image
+
+    def make_fip1(self):
+        logging.debug("make_fip1:")
+
+        chip_conf = self.param1["CHIP_CONF"].content
+        self.param1["CHIP_CONF_SIZE"].content = len(chip_conf)
+
+        blcp = self.body1["BLCP"].content
+        self.param1["BLCP_IMG_CKSUM"].content = self.image_crc(blcp)
+        self.param1["BLCP_IMG_SIZE"].content = len(blcp)
+
+        bl2 = self.body1["BL2"].content
+        self.param1["BL2_IMG_CKSUM"].content = self.image_crc(bl2)
+        self.param1["BL2_IMG_SIZE"].content = len(bl2)
+
+        # Pack body1
+        body1_bin = b""
+        for entry in self.body1.values():
+            if len(entry.content) % IMAGE_ALIGN:
+                raise ValueError("%s (%d) is not align to %d" % (entry.name, len(entry.content), IMAGE_ALIGN))
+
+            logging.info("add %s (%#x)", entry.name, len(entry.content))
+            body1_bin += entry.content
+
+        logging.debug("len(body1_bin) is %d", len(body1_bin))
+
+        # Param1 cksum
+        param1_bin = b"".join((entry.content for entry in self.param1.values()))
+        param1_bin = self.update_param1_cksum(param1_bin)
+
+        if len(param1_bin) != PARAM1_SIZE:
+            raise ValueError("param1_bin is %d bytes" % len(param1_bin))
+
+        fip1_bin = param1_bin + body1_bin
+        logging.debug("len(fip1_bin) is %d", len(fip1_bin))
+
+        return fip1_bin
+
+    def add_ddr_param(self, args):
+        with open(args.DDR_PARAM, "rb") as fp:
+            ddr_param = fp.read()
+
+        logging.debug("ddr_param=%#x bytes", len(ddr_param))
+        self.body2["DDR_PARAM"].content = ddr_param
+
+    def add_blcp_2nd(self, args):
+        with open(args.BLCP_2ND, "rb") as fp:
+            blcp_2nd = fp.read()
+
+        logging.debug("blcp_2nd=%#x bytes", len(blcp_2nd))
+        self.body2["BLCP_2ND"].content = blcp_2nd
+
+    def add_monitor(self, args):
+        with open(args.MONITOR, "rb") as fp:
+            monitor = fp.read()
+
+        logging.debug("monitor=%#x bytes", len(monitor))
+        self.body2["MONITOR"].content = monitor
+
+    def add_loader_2nd(self, args):
+        with open(args.LOADER_2ND, "rb") as fp:
+            loader_2nd = fp.read()
+
+        logging.debug("loader_2nd=%#x bytes", len(loader_2nd))
+
+        e = self.ldr_2nd_hdr["MAGIC"]
+        magic = loader_2nd[e.addr : e.end]
+        if magic != LOADER_2ND_MAGIC_ORIG:
+            raise ValueError("loader_2nd's magic should be %r, but %r" % (LOADER_2ND_MAGIC_ORIG, magic))
+
+        self.compress_algo = args.compress
+        self.body2["LOADER_2ND"].content = loader_2nd
+
+    def pack_ddr_param(self, fip_bin):
+        if not len(self.body2["DDR_PARAM"].content):
+            return
+
+        fip_bin = self.pad(fip_bin, IMAGE_ALIGN)
+
+        # Pack DDR_PARAM to body2
+        ddr_param = self.pad(self.body2["DDR_PARAM"].content, IMAGE_ALIGN)
+
+        self.param2["DDR_PARAM_CKSUM"].content = self.image_crc(ddr_param)
+        self.param2["DDR_PARAM_SIZE"].content = len(ddr_param)
+        self.param2["DDR_PARAM_LOADADDR"].content = len(fip_bin)
+
+        return fip_bin + ddr_param
+
+    def pack_blcp_2nd(self, fip_bin, blcp_2nd_runaddr):
+        logging.debug("pack_blcp_2nd:")
+        if not len(self.body2["BLCP_2ND"].content):
+            return
+
+        runaddr = int(blcp_2nd_runaddr)
+
+        fip_bin = self.pad(fip_bin, IMAGE_ALIGN)
+
+        # Pack MONITOR to body2
+        body = self.pad(self.body2["BLCP_2ND"].content, IMAGE_ALIGN)
+
+        self.param2["BLCP_2ND_CKSUM"].content = self.image_crc(body)
+        self.param2["BLCP_2ND_SIZE"].content = len(body)
+        self.param2["BLCP_2ND_LOADADDR"].content = len(fip_bin)
+        self.param2["BLCP_2ND_RUNADDR"].content = runaddr
+
+        return fip_bin + body
+
+    def pack_monitor(self, fip_bin, monitor_runaddr):
+        logging.debug("pack_monitor:")
+        if not len(self.body2["MONITOR"].content):
+            return
+
+        monitor_runaddr = int(monitor_runaddr)
+
+        fip_bin = self.pad(fip_bin, IMAGE_ALIGN)
+
+        # Pack MONITOR to body2
+        monitor = self.pad(self.body2["MONITOR"].content, IMAGE_ALIGN)
+
+        self.param2["MONITOR_CKSUM"].content = self.image_crc(monitor)
+        self.param2["MONITOR_SIZE"].content = len(monitor)
+        self.param2["MONITOR_LOADADDR"].content = len(fip_bin)
+        self.param2["MONITOR_RUNADDR"].content = monitor_runaddr
+
+        return fip_bin + monitor
+
+    def _parse_ldr_2nd_hdr(self, image):
+        for e in self.ldr_2nd_hdr.values():
+            e.content = image[e.addr : e.end]
+
+    def _update_ldr_2nd_hdr(self):
+        image = self.body2["LOADER_2ND"].content
+        hdr_size = self._param_size(self.ldr_2nd_hdr)
+        hdr, body = image[:hdr_size], image[hdr_size:]
+
+        # Update SIZE
+        self.ldr_2nd_hdr["SIZE"].content = len(image)
+
+        # Update CKSUM
+        hdr = bytearray(b"".join((e.content for e in self.ldr_2nd_hdr.values())))
+        # CKSUM is calculated after "CKSUM" field
+        hdr_cksum = self.ldr_2nd_hdr["CKSUM"]
+        crc = self.image_crc((hdr + body)[hdr_cksum.end :])
+        hdr_cksum.content = crc
+        hdr = bytearray(b"".join((e.content for e in self.ldr_2nd_hdr.values())))
+
+        self.body2["LOADER_2ND"].content = hdr + body
+
+    def _compress_ldr_2nd(self):
+        image = self.body2["LOADER_2ND"].content
+        hdr_size = self._param_size(self.ldr_2nd_hdr)
+        hdr, body = image[:hdr_size], image[hdr_size:]
+
+        magic = self.ldr_2nd_hdr["MAGIC"].content
+        if magic == LOADER_2ND_MAGIC_ORIG:
+            # if image is uncompressed, compress it.
+            if self.compress_algo is None:
+                pass
+            elif self.compress_algo == "lzma":
+                self.ldr_2nd_hdr["MAGIC"].content = LOADER_2ND_MAGIC_LZMA
+                body = lzma_compress(body)
+                logging.info("lzma loader_2nd=%#x bytes wo header", len(body))
+            elif self.compress_algo == "lz4":
+                self.ldr_2nd_hdr["MAGIC"].content = LOADER_2ND_MAGIC_LZ4
+                body = lz4_compress(body)
+                logging.info("lz4 loader_2nd=%#x bytes wo header", len(body))
+            else:
+                raise NotImplementedError("'%r' is not supported." % self.compress_algo)
+        elif magic in LOADER_2ND_MAGIC_LIST:
+            logging.info("loader_2nd is already compressed")
+        else:
+            raise ValueError("unknown loader_2nd magic (%r)", magic)
+
+        self.body2["LOADER_2ND"].content = self.pad(hdr + body, IMAGE_ALIGN)
+
+    def pack_loader_2nd(self, fip_bin):
+        logging.debug("pack_loader_2nd:")
+        if not len(self.body2["LOADER_2ND"].content):
+            return
+
+        fip_bin = self.pad(fip_bin, IMAGE_ALIGN)
+        self.param2["LOADER_2ND_LOADADDR"].content = len(fip_bin)
+
+        self._parse_ldr_2nd_hdr(self.body2["LOADER_2ND"].content)
+        self._compress_ldr_2nd()
+        self._update_ldr_2nd_hdr()
+
+        # Append LOADER_2ND to body2
+        return fip_bin + self.body2["LOADER_2ND"].content
+
+    def insert_param1(self, fip_bin, name, value):
+        fip_bin = bytearray(fip_bin)
+        e = self.param1[name]
+        e.content = value
+        fip_bin[e.addr : e.end] = value
+        return self.update_param1_cksum(fip_bin)
+
+    def append_fip2(self, fip1_bin, args):
+        logging.debug("make_fip2:")
+        fip_bin = bytearray(fip1_bin)
+
+        # Update PARAM2_LOADADDR
+        param2_loadaddr = len(fip1_bin)
+        fip_bin = self.insert_param1(fip_bin, "PARAM2_LOADADDR", pack("<I", param2_loadaddr))
+
+        # Add an empty PARAM2
+        fip_bin += b"\0" * PARAM2_SIZE
+
+        # Pack body
+        fip_bin = self.pack_ddr_param(fip_bin)
+
+        if len(self.body2["BLCP_2ND"].content):
+            runaddr = self.param2["BLCP_2ND_RUNADDR"].toint()
+            if not runaddr:
+                runaddr = int(args.BLCP_2ND_RUNADDR)
+            fip_bin = self.pack_blcp_2nd(fip_bin, runaddr)
+
+        if len(self.body2["MONITOR"].content):
+            runaddr = self.param2["MONITOR_RUNADDR"].toint()
+            if not runaddr:
+                runaddr = int(args.MONITOR_RUNADDR)
+            fip_bin = self.pack_monitor(fip_bin, runaddr)
+
+        if len(self.body2["LOADER_2ND"].content):
+            fip_bin = self.pack_loader_2nd(fip_bin)
+
+        # Pack param2_bin
+        param2_bin = b"".join((entry.content for entry in self.param2.values()))
+        self.param2["PARAM2_CKSUM"].content = self.image_crc(param2_bin[self.param2["PARAM2_CKSUM"].end :])
+        param2_bin = b"".join((entry.content for entry in self.param2.values()))  # update cksum
+
+        logging.debug("len(param2_bin) is %d", len(param2_bin))
+        assert len(param2_bin) == PARAM2_SIZE
+
+        fip_bin[param2_loadaddr : param2_loadaddr + PARAM2_SIZE] = param2_bin
+
+        return fip_bin
+
+    def make(self, args=None):
+        fip_bin = self.make_fip1()
+        if len(self.body2["DDR_PARAM"].content):
+            fip_bin = self.append_fip2(fip_bin, args)
+
+        logging.info("generated fip_bin is %d bytes", len(fip_bin))
+
+        if getattr(self, "rest_fip", None):
+            logging.error("the rest of fip is not used: %#x bytes ", len(self.rest_fip))
+
+        return fip_bin
+
+
+METHODS = {
+    "NOR_INFO": FIP.add_nor_info,
+    "NAND_INFO": FIP.add_nand_info,
+    "CHIP_CONF": FIP.add_chip_conf,
+    "BLCP": FIP.add_blcp,
+    "BL2": FIP.add_bl2,
+    "DDR_PARAM": FIP.add_ddr_param,
+    "BLCP_2ND": FIP.add_blcp_2nd,
+    "MONITOR": FIP.add_monitor,
+    "LOADER_2ND": FIP.add_loader_2nd,
+}
+
+
+def generate_fip(args):
+    logging.debug("generate_fip:")
+    fip = FIP()
+
+    if args.OLD_FIP:
+        fip.read_fip(args.OLD_FIP)
+
+    for m, f in METHODS.items():
+        if getattr(args, m):
+            f(fip, args)
+
+    fip_bin = fip.make(args)
+    fip.print_fip_params()
+
+    if args.output:
+        with open(args.output, "wb") as fp:
+            fp.write(fip_bin)
+
+
+def parse_args():
+    parser = argparse.ArgumentParser(description="FIP tools")
+
+    parser.add_argument(
+        "-v",
+        "--verbose",
+        help="Increase output verbosity",
+        action="store_const",
+        const=logging.DEBUG,
+        default=logging.INFO,
+    )
+
+    subparsers = parser.add_subparsers(dest="subcmd", help="Sub-command help")
+    pr_gen = subparsers.add_parser("genfip", help="Generate keys")
+
+    for name in list(METHODS):
+        if name in ["NOR_INFO", "NAND_INFO"]:
+            pr_gen.add_argument("--" + name, type=bytes.fromhex)
+        else:
+            pr_gen.add_argument("--" + name, dest=name, type=str, help="Add %s into FIP" % name)
+
+    def auto_int(x):
+        return int(x, 0)
+
+    pr_gen.add_argument("--BLCP_IMG_RUNADDR", type=auto_int)
+    pr_gen.add_argument("--BLCP_PARAM_LOADADDR", type=auto_int)
+
+    pr_gen.add_argument("--BLCP_2ND_RUNADDR", type=auto_int)
+
+    pr_gen.add_argument("--MONITOR_RUNADDR", type=auto_int)
+
+    pr_gen.add_argument("--compress", choices=["lzma", "lz4", ""])
+
+    pr_gen.add_argument("--OLD_FIP", type=str)
+    pr_gen.add_argument("--BLOCK_SIZE", type=auto_int)
+    pr_gen.add_argument("--BL2_FILL", type=auto_int)
+
+    pr_gen.add_argument("output", type=str, help="Output filename")
+
+    pr_gen.set_defaults(func=generate_fip)
+
+    if argcomplete:
+        argcomplete.autocomplete(parser)
+
+    args = parser.parse_args()
+    init_logging(stdout_level=args.verbose)
+    logging.info("PROG: %s", parser.prog)
+
+    if not args.subcmd:
+        parser.print_help()
+        raise SystemExit(1)
+
+    for a, v in sorted(vars(args).items()):
+        logging.debug("  %s=%r", a, v)
+
+    return args
+
+
+def main():
+    args = parse_args()
+    args.func(args)
+
+
+def init_logging(log_file=None, file_level="DEBUG", stdout_level="WARNING"):
+    root_logger = logging.getLogger()
+    root_logger.setLevel(logging.NOTSET)
+
+    fmt = "%(asctime)s %(levelname)8s:%(name)s:%(message)s"
+
+    if log_file is not None:
+        file_handler = logging.FileHandler(log_file, encoding="utf-8")
+        file_handler.setFormatter(logging.Formatter(fmt))
+        file_handler.setLevel(file_level)
+        root_logger.addHandler(file_handler)
+
+    if coloredlogs:
+        os.environ["COLOREDLOGS_DATE_FORMAT"] = "%H:%M:%S"
+
+        field_styles = {
+            "asctime": {"color": "green"},
+            "hostname": {"color": "magenta"},
+            "levelname": {"color": "black", "bold": True},
+            "name": {"color": "blue"},
+            "programname": {"color": "cyan"},
+        }
+
+        level_styles = coloredlogs.DEFAULT_LEVEL_STYLES
+        level_styles["debug"]["color"] = "cyan"
+
+        coloredlogs.install(
+            level=stdout_level,
+            fmt=fmt,
+            field_styles=field_styles,
+            level_styles=level_styles,
+            milliseconds=True,
+        )
+
+
+if __name__ == "__main__":
+    main()
--- a/bsp/cvitek/pre-build/fsbl/plat/cv180x/platform.mk
+++ b/bsp/cvitek/pre-build/fsbl/plat/cv180x/platform.mk
@ -0,0 +1,85 @@
+#
+# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Enable workarounds for selected Cortex-A53 errata
+ERRATA_A53_835769	:=	1
+ERRATA_A53_843419	:=	1
+ERRATA_A53_855873	:=	1
+
+PAGE_SIZE_64KB := 1
+TEST_FROM_SPINOR1 := 0
+
+DEFINES += -DLZ4_USER_MEMORY_FUNCTIONS=1
+
+# ifeq ($(FSBL_SECURE_BOOT_SUPPORT),1)
+DEFINES += \
+	-DNO_ALLOCS \
+	-DARGTYPE=3 \
+	-DLTC_NO_FILE \
+	-DLTM_NO_FILE \
+	-DLTM_DESC \
+	-DLTC_SOURCE
+
+CRYPT_INCLUDES := \
+	-Ilib/libtommath \
+	-Ilib/libtomcrypt/src/headers \
+	-Ilib/BigDigits
+
+CRYPT_SOURCES := \
+	lib/BigDigits/bigdigits.c \
+	lib/libtomcrypt/src/hashes/sha2/sha256.c
+# endif
+
+INCLUDES += \
+	-Iinclude \
+	${CPU_INCLUDES} \
+	-Iplat/ \
+	-Iplat/${CHIP_ARCH}/include/uart \
+	-Iplat/${CHIP_ARCH}/include/usb \
+	-Iplat/${CHIP_ARCH}/include \
+	-Iplat/${CHIP_ARCH}/include/${BOOT_CPU} \
+	-Ilib/utils \
+	-Ilib/lzma \
+	-Ilib/lz4 \
+	-Ilib/crc \
+	${STDLIB_INCLUDES} \
+	${CRYPT_INCLUDES}
+
+#BL_COMMON_SOURCES = \
+	${CPU_SOURCES} \
+	lib/tf_printf/tf_printf.c \
+	plat/${CHIP_ARCH}/platform.c \
+	plat/${CHIP_ARCH}/security/security.c \
+	${STDLIB_SRCS} \
+	${CRYPT_SOURCES}
+
+#DECOMPRESSION_SOURCES = \
+	lib/lzma/LzmaDec.c \
+	lib/lz4/lz4_all.c \
+	lib/lz4/xxhash.c
+
+#BL2_SRCS = \
+	${BL_COMMON_SOURCES} \
+	plat/${CHIP_ARCH}/platform_device.c \
+	plat/${CHIP_ARCH}/bl2/bl2_opt.c \
+	lib/utils/decompress.c \
+	plat/${CHIP_ARCH}/usb/cps_cvi.c  \
+	plat/${CHIP_ARCH}/usb/usb_tty.c  \
+	plat/${CHIP_ARCH}/usb/dwc2_udc_otg.c  \
+	plat/${CHIP_ARCH}/usb/dwc2_udc_otg_xfer_dma.c  \
+	plat/${CHIP_ARCH}/usb/cv_usb.c  \
+	lib/crc/crc16.c \
+	${DECOMPRESSION_SOURCES}
+
+BL2_SOURCES = \
+	${BL2_CPU_SOURCES} \
+	${BL2_SRCS} \
+	plat/${CHIP_ARCH}/bl2/bl2_main.c
+
+#include plat/${CHIP_ARCH}/ddr/ddr.mk
+
+BL2_LINKERFILE := plat/${CHIP_ARCH}/bl2/bl2.ld.S
+BL2_RLS_OBJS := plat/${CHIP_ARCH}/bl2_objs/${PROJECT_FULLNAME}/bl2/*.o
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/blcp.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/blcp.bin
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/blcp_param.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/blcp_param.bin
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_clear_rom.cmm
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_clear_rom.cmm
@ -0,0 +1,16 @@
+sys.up
+
+; Reset
+break;
+WAIT !ISRUN() ;wait until target stop
+
+; MWriteS32 PM:0x0C000000++0x3ffff 0x14000000
+MWriteS32 PM:0x4400000++0xf 0x14000000
+MWriteS32 0x4400000++0xf 0x14000000
+Register.Set pc 0x04400000
+
+; MWriteS32 PM:0x03000008 0x4 // wdt reset enable
+; MWriteS32 PM:0x03010004 0x1 // Set timeout range reigster
+; MWriteS32 PM:0x0301000c 0x76 // Counter restart register
+; MWriteS32 PM:0x03010000 0x13
+print "CLEAR ROM"
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_c906.cmm
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_c906.cmm
@ -0,0 +1,14 @@
+DO up.cmm
+
+MWriteS32 PM:0x4400000++0xf 0x14000000
+MWriteS32 PM:0x4418000++0xf 0x6F
+Register.Set pc 0x04400000
+print "clear ROM"
+
+LoadBINARY ..\cv181x_c906b_bl1.bin 0x04418000 %S32
+print "C906B BL1 loaded"
+
+Data.Set PM:0x3003024 %LONG Data.Long(PM:0x3003024)|(1<<5)
+print "Release C906B"
+
+END
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_ca53.cmm
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/cv181x_fpga_bl1_ca53.cmm
@ -0,0 +1,13 @@
+DO up.cmm
+
+MWriteS32 PM:0x4400000++0xf 0x14000000
+Register.Set pc 0x04400000
+print "clear ROM"
+
+LoadBINARY ..\cv181x_ca53_bl1.bin 0x04400000 %S32
+print "CA53 BL1 loaded"
+
+Register.Set r0 0
+Register.Set pc 0x04400000
+
+END
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/up.cmm
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cmm/up.cmm
@ -0,0 +1,40 @@
+
+;winclear
+system.reset
+translation.reset
+
+system.cpu cortexa53
+system.config debugaccessport 0
+system.config apbaccessport 0
+system.config axiaccessport 1
+system.config memoryaccessport 1
+; set corenumber first
+sys.config corenumber 1
+; then set corebase and ctibase
+sys.config corebase 0x81010000
+sys.config ctibase  0x81020000
+sys.jc 5mhz
+
+Wait 10.ms
+system.option enreset on
+system.option trst on
+system.option resetbreak on
+system.option waitreset 500.ms
+OPTION.SerialWire ON
+
+sys.down
+Wait 50.ms
+sys.up
+
+if system.up()
+(
+	; data.list
+)
+else
+(
+	dialog.ok "system.up failed"
+)
+
+; Reset
+break;
+WAIT !ISRUN() ;wait until target stop
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_c906b_bl1.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_c906b_bl1.bin
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_ca53_bl1.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/cv181x_ca53_bl1.bin
--- a/bsp/cvitek/pre-build/fsbl/test/cv181x/ddr_param.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/cv181x/ddr_param.bin
--- a/bsp/cvitek/pre-build/fsbl/test/empty.bin
+++ b/bsp/cvitek/pre-build/fsbl/test/empty.bin
--- a/bsp/cvitek/pre-build/fw_dynamic.bin
+++ b/bsp/cvitek/pre-build/fw_dynamic.bin
--- a/bsp/cvitek/pre-build/u-boot-raw.bin
+++ b/bsp/cvitek/pre-build/u-boot-raw.bin