Fix hardfault bug for gcc port
for 2013-02-20 aozima commmit "port for gcc", but the commit is not tested,and the kernel is breakdown in context_gcc.S, the file is a copy from cortex-m3,but not port for cortex-m0, so i complete this port for aozima, test it in stm32f0discovery board , and it works fine.
This commit is contained in:
Bright Pan
parent
0701b57eaa
commit
06987e72e5
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@ -14,20 +14,20 @@
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* 2012-08-17 aozima fixed bug: store r8 - r11.
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* 2013-02-20 aozima port to gcc.
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* 2013-06-18 aozima add restore MSP feature.
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* 2013-11-04 bright fixed hardfault bug for gcc.
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*/
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.cpu cortex-m3
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.cpu cortex-m0
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.fpu softvfp
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.syntax unified
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.thumb
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.text
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.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
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.equ ICSR, 0xE000ED04 /* interrupt control state register */
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.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
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.equ SHPR3, 0xE000ED20 /* system priority register (3) */
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.equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */
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.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
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.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
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.equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */
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.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
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.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
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/*
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* rt_base_t rt_hw_interrupt_disable();
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@ -64,7 +64,7 @@ rt_hw_context_switch:
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LDR R3, [R2]
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CMP R3, #1
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BEQ _reswitch
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MOV R3, #1
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MOVS R3, #1
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STR R3, [R2]
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LDR R2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
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@ -74,8 +74,8 @@ _reswitch:
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LDR R2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
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STR R1, [R2]
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LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
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LDR R1, =PENDSVSET_BIT
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LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
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LDR R1, =NVIC_PENDSVSET
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STR R1, [R0]
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BX LR
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@ -93,36 +93,56 @@ PendSV_Handler:
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/* get rt_thread_switch_interrupt_flag */
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LDR R0, =rt_thread_switch_interrupt_flag
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LDR R1, [R0]
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CBZ R1, pendsv_exit /* pendsv aLReady handled */
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CMP R1, #0x00
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BEQ pendsv_exit /* pendsv aLReady handled */
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/* clear rt_thread_switch_interrupt_flag to 0 */
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MOV R1, #0
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MOVS R1, #0
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STR R1, [R0]
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LDR R0, =rt_interrupt_from_thread
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LDR R1, [R0]
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CBZ R1, swtich_to_thread /* skip register save at the first time */
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CMP R1, #0x00
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BEQ swtich_to_thread /* skip register save at the first time */
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MRS R1, PSP /* get from thread stack pointer */
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STMFD R1!, {R4 - R11} /* push R4 - R11 register */
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MRS R1, PSP /* get from thread stack pointer */
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SUBS R1, R1, #0x20 /* space for {R4 - R7} and {R8 - R11} */
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LDR R0, [R0]
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STR R1, [R0] /* update from thread stack pointer */
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STMIA R1!, {R4 - R7} /* push thread {R4 - R7} register to thread stack */
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MOV R4, R8 /* mov thread {R8 - R11} to {R4 - R7} */
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MOV R5, R9
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MOV R6, R10
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MOV R7, R11
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STMIA R1!, {R4 - R7} /* push thread {R8 - R11} high register to thread stack */
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swtich_to_thread:
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LDR R1, =rt_interrupt_to_thread
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LDR R1, [R1]
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LDR R1, [R1] /* load thread stack pointer */
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LDMFD R1!, {R4 - R11} /* pop R4 - R11 register */
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LDMIA R1!, {R4 - R7} /* pop thread {R4 - R7} register from thread stack */
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PUSH {R4 - R7} /* push {R4 - R7} to MSP for copy {R8 - R11} */
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LDMIA R1!, {R4 - R7} /* pop thread {R8 - R11} high register from thread stack to {R4 - R7} */
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MOV R8, R4 /* mov {R4 - R7} to {R8 - R11} */
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MOV R9, R5
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MOV R10, R6
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MOV R11, R7
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POP {R4 - R7} /* pop {R4 - R7} from MSP */
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MSR PSP, R1 /* update stack pointer */
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pendsv_exit:
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/* restore interrupt */
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MSR PRIMASK, R2
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ORR LR, LR, #0x04
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BX LR
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MOVS R0, #0x04
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RSBS R0, R0, #0x00
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BX R0
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* R0 --> to
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@ -135,31 +155,31 @@ rt_hw_context_switch_to:
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/* set from thread to 0 */
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LDR R1, =rt_interrupt_from_thread
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MOV R0, #0
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MOVS R0, #0
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STR R0, [R1]
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/* set interrupt flag to 1 */
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LDR R1, =rt_thread_switch_interrupt_flag
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MOV R0, #1
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MOVS R0, #1
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STR R0, [R1]
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/* set the PendSV exception priority */
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LDR R0, =SHPR3
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LDR R1, =PENDSV_PRI_LOWEST
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LDR.W R2, [R0,#0] /* read */
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ORR R1, R1, R2 /* modify */
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STR R1, [R0] /* write-back */
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LDR R0, =NVIC_SHPR3
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LDR R1, =NVIC_PENDSV_PRI
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LDR R2, [R0,#0x00] /* read */
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ORRS R1, R1, R2 /* modify */
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STR R1, [R0] /* write-back */
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LDR R0, =ICSR /* trigger the PendSV exception (causes context switch) */
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LDR R1, =PENDSVSET_BIT
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LDR R0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
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LDR R1, =NVIC_PENDSVSET
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STR R1, [R0]
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/* restore MSP */
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LDR r0, =SCB_VTOR
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LDR r0, [r0]
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LDR r0, [r0]
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NOP
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MSR msp, r0
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/* restore MSP */
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LDR R0, =SCB_VTOR
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LDR R0, [R0]
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LDR R0, [R0]
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NOP
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MSR MSP, R0
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CPSIE I /* enable interrupts at processor level */
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@ -179,10 +199,8 @@ HardFault_Handler:
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MRS R0, PSP /* get fault thread stack pointer */
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PUSH {LR}
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BL rt_hw_hard_fault_exception
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POP {LR}
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POP {PC}
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ORR LR, LR, #0x04
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BX LR
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/*
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* rt_uint32_t rt_hw_interrupt_check(void);
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