From a74a2a25a852a795cf353dd8719eec25d4a63c5f Mon Sep 17 00:00:00 2001
From: zchong-cht <zchongnari@126.com>
Date: Mon, 6 Feb 2017 21:57:15 +0800
Subject: [PATCH] Add libcpu/arm/am335x/context_iar.S file

---
 libcpu/arm/am335x/context_iar.S | 96 +++++++++++++++++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 libcpu/arm/am335x/context_iar.S

diff --git a/libcpu/arm/am335x/context_iar.S b/libcpu/arm/am335x/context_iar.S
new file mode 100644
index 0000000000..c53e15a23a
--- /dev/null
+++ b/libcpu/arm/am335x/context_iar.S
@@ -0,0 +1,96 @@
+;/*
+; * File      : context_iar.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; *
+; *  This program is free software; you can redistribute it and/or modify
+; *  it under the terms of the GNU General Public License as published by
+; *  the Free Software Foundation; either version 2 of the License, or
+; *  (at your option) any later version.
+; *
+; *  This program is distributed in the hope that it will be useful,
+; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; *  GNU General Public License for more details.
+; *
+; *  You should have received a copy of the GNU General Public License along
+; *  with this program; if not, write to the Free Software Foundation, Inc.,
+; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2011-08-14     weety      copy from mini2440
+; * 2015-04-15     ArdaFu     convert from context_gcc.s
+; */
+
+#define NOINT            0xc0
+
+    SECTION    .text:CODE(6)
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+    PUBLIC rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    MRS     R0, CPSR
+    ORR     R1, R0, #NOINT
+    MSR     CPSR_C, R1
+    MOV     PC, LR
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+    PUBLIC rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    MSR     CPSR_CXSF, R0
+    MOV     PC, LR
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+    PUBLIC rt_hw_context_switch
+rt_hw_context_switch:
+    STMFD   SP!, {LR}               ; push pc (lr should be pushed in place of PC)
+    STMFD   SP!, {R0-R12, LR}       ; push lr & register file
+    MRS     R4, CPSR
+    STMFD   SP!, {R4}               ; push cpsr
+    STR     SP, [R0]                ; store sp in preempted tasks TCB
+    LDR     SP, [R1]                ; get new task stack pointer
+    LDMFD   SP!, {R4}               ; pop new task spsr
+    MSR     SPSR_cxsf, R4
+    LDMFD   SP!, {R0-R12, LR, PC}^  ; pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+    PUBLIC rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    LDR     SP, [R0]                ; get new task stack pointer
+    LDMFD   SP!, {R4}               ; pop new task spsr
+    MSR     SPSR_cxsf, R4
+    LDMFD   SP!, {R0-R12, LR, PC}^  ; pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+    IMPORT rt_thread_switch_interrupt_flag
+    IMPORT rt_interrupt_from_thread
+    IMPORT rt_interrupt_to_thread
+    PUBLIC rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    LDR     R2, =rt_thread_switch_interrupt_flag
+    LDR     R3, [R2]
+    CMP     R3, #1
+    BEQ     _reswitch
+    MOV     R3, #1                          ; set flag to 1
+    STR     R3, [R2]
+    LDR     R2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
+    STR     R0, [R2]
+_reswitch:
+    LDR     R2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
+    STR     R1, [R2]
+    MOV     PC, LR
+    END
+