[add] stm32mp1 drivers
This commit is contained in:
parent
4ef02cd8e3
commit
0606261b97
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@ -30,7 +30,7 @@ config BSP_USING_CRC
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select RT_HWCRYPTO_USING_CRC
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# "Crypto device frame dose not support above 8-bits granularity"
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# "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
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depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7)
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depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
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default n
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config BSP_USING_RNG
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@ -38,7 +38,7 @@ config BSP_USING_RNG
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select RT_USING_HWCRYPTO
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select RT_HWCRYPTO_USING_RNG
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depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
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SOC_SERIES_STM32H7)
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SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
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default n
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config BSP_USING_UDID
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@ -0,0 +1,117 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-01-02 zylx first version
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* 2019-01-08 SummerGift clean up the code
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA2 stream0 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI1_RX_DMA_CHANNEL DMA_REQUEST_SPI1_RX
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#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
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#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
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#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define SPI4_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI4_RX_DMA_CHANNEL DMA_REQUEST_SPI4_RX
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#define SPI4_RX_DMA_IRQ DMA2_Stream0_IRQn
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#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
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#define UART5_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define UART5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define UART5_RX_DMA_INSTANCE DMA2_Stream0
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#define UART5_RX_DMA_CHANNEL DMA_REQUEST_UART5_RX
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#define UART5_RX_DMA_IRQ DMA2_Stream0_IRQn
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#endif
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/* DMA2 stream1 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream1
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#define SPI1_TX_DMA_CHANNEL DMA_REQUEST_SPI1_RX
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#define SPI1_TX_DMA_IRQ DMA2_Stream1_IRQn
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#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#define SPI4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
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#define SPI4_TX_DMA_CHANNEL DMA_REQUEST_SPI4_TX
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#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
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#endif
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/* DMA2 stream2 */
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#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA2_Stream2_IRQHandler
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#define QSPI_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define QSPI_DMA_INSTANCE DMA2_Stream2
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#define QSPI_DMA_CHANNEL DMA_CHANNEL_11
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#define QSPI_DMA_IRQ DMA2_Stream2_IRQn
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#endif
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/* DMA2 stream3 */
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#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
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#define SPI5_RX_DMA_CHANNEL DMA_REQUEST_SPI5_RX
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#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
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#endif
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/* DMA2 stream4 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
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#define SPI5_TX_DMA_CHANNEL DMA_REQUEST_SPI5_TX
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#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
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#endif
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/* DMA2 stream5 */
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#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
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#define UART4_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
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#define UART4_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define UART4_TX_DMA_INSTANCE DMA2_Stream5
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#define UART4_TX_DMA_CHANNEL DMA_REQUEST_UART4_TX
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#define UART4_TX_DMA_IRQ DMA2_Stream5_IRQn
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#endif
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/* DMA2 stream6 */
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#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
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#define UART4_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler
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#define UART4_RX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define UART4_RX_DMA_INSTANCE DMA2_Stream6
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#define UART4_RX_DMA_CHANNEL DMA_REQUEST_UART4_RX
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#define UART4_RX_DMA_IRQ DMA2_Stream6_IRQn
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#endif
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/* DMA2 stream7 */
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#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
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#define UART5_DMA_TX_IRQHandler DMA2_Stream7_IRQHandler
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#define UART5_TX_DMA_RCC RCC_MC_AHB2ENSETR_DMA2EN
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#define UART5_TX_DMA_INSTANCE DMA2_Stream7
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#define UART5_TX_DMA_CHANNEL DMA_REQUEST_UART5_TX
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#define UART5_TX_DMA_IRQ DMA2_Stream7_IRQn
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */
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@ -0,0 +1,235 @@
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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-10-30 SummerGift first version
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* 2019-01-03 zylx modify dma support
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*/
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#ifndef __UART_CONFIG_H__
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#define __UART_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(BSP_USING_UART1)
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#ifndef UART1_CONFIG
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#define UART1_CONFIG \
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{ \
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.name = "uart1", \
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.Instance = USART1, \
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.irq_type = USART1_IRQn, \
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}
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#endif /* UART1_CONFIG */
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#if defined(BSP_UART1_RX_USING_DMA)
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#ifndef UART1_DMA_RX_CONFIG
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#define UART1_DMA_RX_CONFIG \
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{ \
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.Instance = UART1_RX_DMA_INSTANCE, \
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.request = UART1_RX_DMA_CHANNEL, \
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.dma_rcc = UART1_RX_DMA_RCC, \
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.dma_irq = UART1_RX_DMA_IRQ, \
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}
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#endif /* UART1_DMA_RX_CONFIG */
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#endif /* BSP_UART1_RX_USING_DMA */
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#if defined(BSP_UART1_TX_USING_DMA)
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#ifndef UART1_DMA_TX_CONFIG
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#define UART1_DMA_TX_CONFIG \
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{ \
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.Instance = UART1_TX_DMA_INSTANCE, \
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.request = UART1_TX_DMA_CHANNEL, \
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.dma_rcc = UART1_TX_DMA_RCC, \
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.dma_irq = UART1_TX_DMA_IRQ, \
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}
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#endif /* UART1_DMA_TX_CONFIG */
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#endif /* BSP_UART1_TX_USING_DMA */
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#endif /* BSP_USING_UART1 */
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#if defined(BSP_USING_UART2)
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#ifndef UART2_CONFIG
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#define UART2_CONFIG \
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{ \
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.name = "uart2", \
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.Instance = USART2, \
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.irq_type = USART2_IRQn, \
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}
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#endif /* UART2_CONFIG */
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#if defined(BSP_UART2_RX_USING_DMA)
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#ifndef UART2_DMA_RX_CONFIG
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#define UART2_DMA_RX_CONFIG \
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{ \
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.Instance = UART2_RX_DMA_INSTANCE, \
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.request = UART2_RX_DMA_CHANNEL, \
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.dma_rcc = UART2_RX_DMA_RCC, \
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.dma_irq = UART2_RX_DMA_IRQ, \
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}
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#endif /* UART2_DMA_RX_CONFIG */
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#endif /* BSP_UART2_RX_USING_DMA */
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#if defined(BSP_UART2_TX_USING_DMA)
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#ifndef UART2_DMA_TX_CONFIG
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#define UART2_DMA_TX_CONFIG \
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{ \
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.Instance = UART2_TX_DMA_INSTANCE, \
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.request = UART2_TX_DMA_CHANNEL, \
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.dma_rcc = UART2_TX_DMA_RCC, \
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.dma_irq = UART2_TX_DMA_IRQ, \
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}
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#endif /* UART2_DMA_TX_CONFIG */
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#endif /* BSP_UART2_TX_USING_DMA */
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#endif /* BSP_USING_UART2 */
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#if defined(BSP_USING_UART3)
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#ifndef UART3_CONFIG
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#define UART3_CONFIG \
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{ \
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.name = "uart3", \
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.Instance = USART3, \
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.irq_type = USART3_IRQn, \
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}
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#endif /* UART3_CONFIG */
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#if defined(BSP_UART3_RX_USING_DMA)
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#ifndef UART3_DMA_RX_CONFIG
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#define UART3_DMA_RX_CONFIG \
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{ \
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.Instance = UART3_RX_DMA_INSTANCE, \
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.request = UART3_RX_DMA_CHANNEL, \
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.dma_rcc = UART3_RX_DMA_RCC, \
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.dma_irq = UART3_RX_DMA_IRQ, \
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}
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#endif /* UART3_DMA_RX_CONFIG */
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#endif /* BSP_UART3_RX_USING_DMA */
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#if defined(BSP_UART3_TX_USING_DMA)
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#ifndef UART3_DMA_TX_CONFIG
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#define UART3_DMA_TX_CONFIG \
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{ \
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.Instance = UART3_TX_DMA_INSTANCE, \
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.request = UART3_TX_DMA_CHANNEL, \
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.dma_rcc = UART3_TX_DMA_RCC, \
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.dma_irq = UART3_TX_DMA_IRQ, \
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}
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#endif /* UART3_DMA_TX_CONFIG */
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#endif /* BSP_UART3_TX_USING_DMA */
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#endif /* BSP_USING_UART3 */
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#if defined(BSP_USING_UART4)
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#ifndef UART4_CONFIG
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#define UART4_CONFIG \
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{ \
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.name = "uart4", \
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.Instance = UART4, \
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.irq_type = UART4_IRQn, \
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}
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#endif /* UART4_CONFIG */
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#if defined(BSP_UART4_RX_USING_DMA)
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#ifndef UART4_DMA_RX_CONFIG
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#define UART4_DMA_RX_CONFIG \
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{ \
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.Instance = UART4_RX_DMA_INSTANCE, \
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.request = UART4_RX_DMA_CHANNEL, \
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.dma_rcc = UART4_RX_DMA_RCC, \
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.dma_irq = UART4_RX_DMA_IRQ, \
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}
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#endif /* UART4_DMA_RX_CONFIG */
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#endif /* BSP_UART4_RX_USING_DMA */
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#if defined(BSP_UART4_TX_USING_DMA)
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#ifndef UART4_DMA_TX_CONFIG
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#define UART4_DMA_TX_CONFIG \
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{ \
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.Instance = UART4_TX_DMA_INSTANCE, \
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.request = UART4_TX_DMA_CHANNEL, \
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.dma_rcc = UART4_TX_DMA_RCC, \
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.dma_irq = UART4_TX_DMA_IRQ, \
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}
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#endif /* UART4_DMA_TX_CONFIG */
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#endif /* BSP_UART4_RX_USING_DMA */
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#endif /* BSP_USING_UART4 */
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#if defined(BSP_USING_UART5)
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#ifndef UART5_CONFIG
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#define UART5_CONFIG \
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{ \
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.name = "uart5", \
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.Instance = UART5, \
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.irq_type = UART5_IRQn, \
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}
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#endif /* UART5_CONFIG */
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#if defined(BSP_UART5_RX_USING_DMA)
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#ifndef UART5_DMA_RX_CONFIG
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#define UART5_DMA_RX_CONFIG \
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{ \
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.Instance = UART5_RX_DMA_INSTANCE, \
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.request = UART5_RX_DMA_CHANNEL, \
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.dma_rcc = UART5_RX_DMA_RCC, \
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.dma_irq = UART5_RX_DMA_IRQ, \
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}
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#endif /* UART5_DMA_RX_CONFIG */
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#endif /* BSP_UART5_RX_USING_DMA */
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#if defined(BSP_UART5_TX_USING_DMA)
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#ifndef UART5_DMA_TX_CONFIG
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#define UART5_DMA_TX_CONFIG \
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{ \
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.Instance = UART5_TX_DMA_INSTANCE, \
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.request = UART5_TX_DMA_CHANNEL, \
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.dma_rcc = UART5_TX_DMA_RCC, \
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.dma_irq = UART5_TX_DMA_IRQ, \
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}
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#endif /* UART5_DMA_TX_CONFIG */
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#endif /* BSP_UART5_TX_USING_DMA */
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#endif /* BSP_USING_UART5 */
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#if defined(BSP_USING_UART6)
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#ifndef UART6_CONFIG
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#define UART6_CONFIG \
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{ \
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.name = "uart6", \
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.Instance = USART6, \
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.irq_type = USART6_IRQn, \
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}
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#endif /* UART6_CONFIG */
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#if defined(BSP_UART6_RX_USING_DMA)
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#ifndef UART6_DMA_RX_CONFIG
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#define UART6_DMA_RX_CONFIG \
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{ \
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.Instance = UART6_RX_DMA_INSTANCE, \
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.request = UART6_RX_DMA_CHANNEL, \
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.dma_rcc = UART6_RX_DMA_RCC, \
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.dma_irq = UART6_RX_DMA_IRQ, \
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}
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#endif /* UART6_DMA_RX_CONFIG */
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#endif /* BSP_UART6_RX_USING_DMA */
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#if defined(BSP_UART6_TX_USING_DMA)
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#ifndef UART6_DMA_TX_CONFIG
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#define UART6_DMA_TX_CONFIG \
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{ \
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.Instance = UART6_TX_DMA_INSTANCE, \
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.request = UART6_TX_DMA_CHANNEL, \
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.dma_rcc = UART6_TX_DMA_RCC, \
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.dma_irq = UART6_TX_DMA_IRQ, \
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}
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#endif /* UART6_DMA_TX_CONFIG */
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#endif /* BSP_UART6_TX_USING_DMA */
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#endif /* BSP_USING_UART6 */
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -29,10 +29,14 @@ void rt_hw_systick_init(void)
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{
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#if defined (SOC_SERIES_STM32H7)
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HAL_SYSTICK_Config((HAL_RCCEx_GetD1SysClockFreq()) / RT_TICK_PER_SECOND);
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#elif defined (SOC_SERIES_STM32MP1)
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HAL_SYSTICK_Config(HAL_RCC_GetSystemCoreClockFreq() / RT_TICK_PER_SECOND);
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#else
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HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / RT_TICK_PER_SECOND);
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#endif
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#if !defined (SOC_SERIES_STM32MP1)
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HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
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#endif
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NVIC_SetPriority(SysTick_IRQn, 0xFF);
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}
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#include "h7/sdio_config.h"
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#include "h7/pwm_config.h"
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#include "h7/usbd_config.h"
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#elif defined(SOC_SERIES_STM32MP1)
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#include "mp1/dma_config.h"
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#include "mp1/uart_config.h"
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#endif
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#ifdef __cplusplus
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@ -22,7 +22,7 @@ extern "C" {
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|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
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#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
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#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
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|| defined(SOC_SERIES_STM32H7)
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|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
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||||
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
|
||||
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
|
||||
|
||||
|
@ -36,7 +36,7 @@ struct dma_config {
|
|||
#endif
|
||||
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
|
||||
|| defined(SOC_SERIES_STM32H7)
|
||||
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|
||||
rt_uint32_t request;
|
||||
#endif
|
||||
};
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
* Date Author Notes
|
||||
* 2018-11-06 balanceTWK first version
|
||||
* 2019-04-23 WillianChan Fix GPIO serial number disorder
|
||||
* 2020-06-16 thread-liu add STM32MP1
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
|
@ -235,6 +236,23 @@ static const struct pin_irq_map pin_irq_map[] =
|
|||
{GPIO_PIN_13, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_14, EXTI4_15_IRQn},
|
||||
{GPIO_PIN_15, EXTI4_15_IRQn},
|
||||
#elif defined(SOC_SERIES_STM32MP1)
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
{GPIO_PIN_2, EXTI2_IRQn},
|
||||
{GPIO_PIN_3, EXTI3_IRQn},
|
||||
{GPIO_PIN_4, EXTI4_IRQn},
|
||||
{GPIO_PIN_5, EXTI5_IRQn},
|
||||
{GPIO_PIN_6, EXTI6_IRQn},
|
||||
{GPIO_PIN_7, EXTI7_IRQn},
|
||||
{GPIO_PIN_8, EXTI8_IRQn},
|
||||
{GPIO_PIN_9, EXTI9_IRQn},
|
||||
{GPIO_PIN_10, EXTI10_IRQn},
|
||||
{GPIO_PIN_11, EXTI11_IRQn},
|
||||
{GPIO_PIN_12, EXTI12_IRQn},
|
||||
{GPIO_PIN_13, EXTI13_IRQn},
|
||||
{GPIO_PIN_14, EXTI14_IRQn},
|
||||
{GPIO_PIN_15, EXTI15_IRQn},
|
||||
#else
|
||||
{GPIO_PIN_0, EXTI0_IRQn},
|
||||
{GPIO_PIN_1, EXTI1_IRQn},
|
||||
|
@ -619,7 +637,7 @@ rt_inline void pin_irq_hdr(int irqno)
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(SOC_SERIES_STM32G0)
|
||||
#if defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1)
|
||||
void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
pin_irq_hdr(bit2bitno(GPIO_Pin));
|
||||
|
@ -670,6 +688,103 @@ void EXTI4_15_IRQHandler(void)
|
|||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
#elif defined(SOC_STM32MP157A)
|
||||
void EXTI0_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_0);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI1_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI2_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_2);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI3_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_3);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI4_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_4);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI5_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI6_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI7_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI8_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_8);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI9_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_9);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI10_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_10);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI11_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_11);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI12_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_12);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI13_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_13);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI14_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_14);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void EXTI15_IRQHandler(void) {
|
||||
rt_interrupt_enter();
|
||||
HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_15);
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
void EXTI0_IRQHandler(void)
|
||||
|
|
|
@ -6,6 +6,7 @@
|
|||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2018-11-06 balanceTWK first version
|
||||
* 2020-06-16 thread-liu add stm32mp1
|
||||
*/
|
||||
|
||||
#ifndef __DRV_GPIO_H__
|
||||
|
@ -16,7 +17,11 @@
|
|||
|
||||
#define __STM32_PORT(port) GPIO##port##_BASE
|
||||
|
||||
#if defined(SOC_SERIES_STM32MP1)
|
||||
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x1000UL) )) + PIN)
|
||||
#else
|
||||
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__STM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
|
||||
#endif
|
||||
|
||||
#define __STM32_PIN(index, gpio, gpio_index) \
|
||||
{ \
|
||||
|
|
|
@ -243,7 +243,7 @@ static int stm32_putc(struct rt_serial_device *serial, char c)
|
|||
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_TC);
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|
||||
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
|
||||
|| defined(SOC_SERIES_STM32G4)
|
||||
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1)
|
||||
uart->handle.Instance->TDR = c;
|
||||
#else
|
||||
uart->handle.Instance->DR = c;
|
||||
|
@ -264,7 +264,7 @@ static int stm32_getc(struct rt_serial_device *serial)
|
|||
{
|
||||
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) \
|
||||
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32H7) \
|
||||
|| defined(SOC_SERIES_STM32G4)
|
||||
|| defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32MP1)
|
||||
ch = uart->handle.Instance->RDR & 0xff;
|
||||
#else
|
||||
ch = uart->handle.Instance->DR & 0xff;
|
||||
|
@ -367,7 +367,7 @@ static void uart_isr(struct rt_serial_device *serial)
|
|||
}
|
||||
#if !defined(SOC_SERIES_STM32L4) && !defined(SOC_SERIES_STM32F7) && !defined(SOC_SERIES_STM32F0) \
|
||||
&& !defined(SOC_SERIES_STM32L0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7) \
|
||||
&& !defined(SOC_SERIES_STM32G4)
|
||||
&& !defined(SOC_SERIES_STM32G4) && !defined(SOC_SERIES_STM32MP1)
|
||||
if (__HAL_UART_GET_FLAG(&(uart->handle), UART_FLAG_LBD) != RESET)
|
||||
{
|
||||
UART_INSTANCE_CLEAR_FUNCTION(&(uart->handle), UART_FLAG_LBD);
|
||||
|
@ -873,7 +873,10 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
|||
|
||||
#if (defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G4)) && defined(DMAMUX1)
|
||||
/* enable DMAMUX clock for L4+ and G4 */
|
||||
__HAL_RCC_DMAMUX1_CLK_ENABLE();
|
||||
__HAL_RCC_DMAMUX1_CLK_ENABLE();
|
||||
#elif defined(SOC_SERIES_STM32MP1)
|
||||
__HAL_RCC_DMAMUX_CLK_ENABLE();
|
||||
__HAL_RCC_DMA2_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
@ -895,7 +898,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
|||
DMA_Handle->Instance = dma_config->Instance;
|
||||
DMA_Handle->Init.Channel = dma_config->channel;
|
||||
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
|
||||
|| defined(SOC_SERIES_STM32H7)
|
||||
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|
||||
DMA_Handle->Instance = dma_config->Instance;
|
||||
DMA_Handle->Init.Request = dma_config->request;
|
||||
#endif
|
||||
|
@ -916,7 +919,7 @@ static void stm32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
|
|||
}
|
||||
|
||||
DMA_Handle->Init.Priority = DMA_PRIORITY_MEDIUM;
|
||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7)
|
||||
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|
||||
DMA_Handle->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
|
||||
#endif
|
||||
if (HAL_DMA_DeInit(DMA_Handle) != HAL_OK)
|
||||
|
|
|
@ -23,7 +23,8 @@ int rt_hw_usart_init(void);
|
|||
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) \
|
||||
|| defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)
|
||||
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
|
||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32H7)
|
||||
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
|
||||
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
|
||||
#define DMA_INSTANCE_TYPE DMA_Stream_TypeDef
|
||||
#endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) */
|
||||
|
||||
|
@ -31,7 +32,8 @@ int rt_hw_usart_init(void);
|
|||
|| defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L0) || defined(SOC_SERIES_STM32G0) \
|
||||
|| defined(SOC_SERIES_STM32G4)
|
||||
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
|
||||
#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7)
|
||||
#elif defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32H7) \
|
||||
|| defined(SOC_SERIES_STM32MP1)
|
||||
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_IT
|
||||
#endif
|
||||
|
||||
|
|
Loading…
Reference in New Issue