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[BSP]Add sct and fix some drivers bug

This commit is contained in:
lin 2018-09-21 16:10:44 +08:00
parent b611f317fe
commit 05cc8415ad
101 changed files with 3751 additions and 1459 deletions
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87
bsp/apollo2/board/adc.c
View File

@ -19,46 +19,57 @@
*
* Change Logs:
* Date Author Notes
* 2017-12-04 Haley the first version
* 2017-09-18 Haley the first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#include "am_mcu_apollo.h"
#include "board.h"
#ifdef RT_USING_ADC
/* sem define */
rt_sem_t adcsem = RT_NULL;
/* messagequeue define */
struct rt_messagequeue adcbat_mq;
#define BATTERY_GPIO 29 /* Battery */
#define BATTERY_ADC_PIN AM_HAL_PIN_29_ADCSE1
#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE1 /* BATTERY ADC采集通道 */
#define BATTERY_ADC_CHANNELNUM 1 /* BATTERY ADC采集通道号 */
#define BATTERY_GPIO 35 /* Battery */
#define BATTERY_ADC_PIN AM_HAL_PIN_35_ADCSE7
#define BATTERY_ADC_CHANNEL AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */
#define BATTERY_ADC_CHANNELNUM 7 /* BATTERY ADC采集通道号 */
#define ADC_CTIMER_NUM 3 /* ADC使用定时器 */
#define ADC_CTIMER_COUNT (2048/512 - 1)
#define ADC_CHANNEL_NUM 1 /* ADC采集通道个数 */
#define ADC_SAMPLE_NUM 8 /* ADC采样个数, NE_OF_OUTPUT */
#define ADC_SAMPLE_NUM 8 /* ADC采样个数 */
rt_uint8_t bat_adc_cnt = (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM;
rt_int16_t am_adc_buffer_pool[64];
rt_uint8_t bat_adc_cnt = 0;
static rt_uint8_t am_adcbat_buffer_pool[256];
static rt_int16_t am_adcbat_buffertemp[32];
rt_uint8_t am_adc_data_get(rt_int16_t *buff, rt_uint16_t size)
rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t size)
{
/* wait adc interrupt release sem forever */
rt_sem_take(adcsem, RT_WAITING_FOREVER);
rt_uint8_t adc_bufftemp[32];
if (channel == BATTERY_ADC_CHANNELNUM)
{
/* wait adc message forever */
rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER);
}
/* copy the data */
rt_memcpy(buff, am_adc_buffer_pool, size*sizeof(rt_int16_t));
rt_memcpy(buff, adc_bufftemp, size*sizeof(rt_int16_t));
return 0;
}
void am_adc_start(void)
void am_adc_start(rt_uint8_t channel)
{
/* adcsem create */
adcsem = rt_sem_create("adcsem", 0, RT_IPC_FLAG_FIFO);
/* messagequeue init */
rt_mq_init(&adcbat_mq, "mq_adcbat",
&am_adcbat_buffer_pool[0],
32 - sizeof(void*),
sizeof(am_adcbat_buffer_pool),
RT_IPC_FLAG_FIFO);
/* Start the ctimer */
am_hal_ctimer_start(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA);
@ -67,13 +78,16 @@ void am_adc_start(void)
am_hal_adc_trigger();
}
void am_adc_stop(void)
void am_adc_stop(rt_uint8_t channel)
{
/* Stop the ctimer */
am_hal_ctimer_stop(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA);
/* adcsem delete */
rt_sem_delete(adcsem);
/* messagequeue delete */
rt_mq_delete(&adceeg_mq);
/* messagequeue delete */
rt_mq_delete(&adcbat_mq);
}
/**
@ -87,6 +101,9 @@ void am_adc_isr(void)
{
uint32_t ui32Status, ui32FifoData;
/* enter interrupt */
rt_interrupt_enter();
/* Read the interrupt status */
ui32Status = am_hal_adc_int_status_get(true);
@ -101,20 +118,23 @@ void am_adc_isr(void)
/* Read the value from the FIFO into the circular buffer */
ui32FifoData = am_hal_adc_fifo_pop();
if(AM_HAL_ADC_FIFO_SLOT(ui32FifoData) == BATTERY_ADC_CHANNELNUM)
am_adc_buffer_pool[bat_adc_cnt++] = AM_HAL_ADC_FIFO_SAMPLE(ui32FifoData);
if(bat_adc_cnt > (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM - 1)
if (AM_HAL_ADC_FIFO_SLOT(ui32FifoData) == BATTERY_ADC_CHANNELNUM)
{
/* shift data */
rt_memmove(am_adc_buffer_pool, am_adc_buffer_pool + ADC_CHANNEL_NUM*ADC_SAMPLE_NUM, ADC_CHANNEL_NUM*ADC_SAMPLE_NUM*sizeof(rt_int16_t));
bat_adc_cnt = (ADC_CHANNEL_NUM + 1)*ADC_SAMPLE_NUM;
am_adcbat_buffertemp[bat_adc_cnt++] = AM_HAL_ADC_FIFO_SAMPLE(ui32FifoData);
}
/* release adcsem */
rt_sem_release(adcsem);
if ((bat_adc_cnt > ADC_SAMPLE_NUM + 2 - 1))
{
bat_adc_cnt = 0;
/* send the message */
rt_mq_send(&adcbat_mq, am_adcbat_buffertemp, ADC_SAMPLE_NUM*sizeof(rt_int16_t));
}
} while (AM_HAL_ADC_FIFO_COUNT(ui32FifoData) > 0);
}
/* leave interrupt */
rt_interrupt_leave();
}
static void timerA3_for_adc_init(void)
@ -129,7 +149,7 @@ static void timerA3_for_adc_init(void)
am_hal_ctimer_int_enable(AM_HAL_CTIMER_INT_TIMERA3);
/* Set 512 sample rate */
am_hal_ctimer_period_set(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA, 3, 1);
am_hal_ctimer_period_set(ADC_CTIMER_NUM, AM_HAL_CTIMER_TIMERA, ADC_CTIMER_COUNT, 1);
/* Enable the timer A3 to trigger the ADC directly */
am_hal_ctimer_adc_trigger_enable();
@ -184,7 +204,10 @@ int rt_hw_adc_init(void)
/* Enable the ADC */
am_hal_adc_enable();
rt_kprintf("adc_init!\n");
/* Trigger the ADC once */
//am_hal_adc_trigger();
//rt_kprintf("adc_init!\n");
return 0;
}

6
bsp/apollo2/board/adc.h
View File

@ -32,8 +32,8 @@
*
*/
int rt_hw_adc_init(void);
rt_uint8_t am_adc_data_get(rt_int16_t *buff, rt_uint16_t size);
void am_adc_start(void);
void am_adc_stop(void);
rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t size);
void am_adc_start(rt_uint8_t channel);
void am_adc_stop(rt_uint8_t channel);
#endif // __ADC_H_

6
bsp/apollo2/board/board.c
View File

@ -104,15 +104,17 @@ void am_low_power_init(void)
/* Turn off the voltage comparator as this is enabled on reset */
am_hal_vcomp_disable();
#ifndef RT_USING_RTC
/* Run the RTC off the LFRC */
am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC);
/* Stop the XT and LFRC */
am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_XT);
am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_LFRC);
//am_hal_clkgen_osc_stop(AM_HAL_CLKGEN_OSC_LFRC);
/* Disable the RTC */
am_hal_rtc_osc_disable();
#endif
}
/**
@ -159,7 +161,7 @@ void rt_hw_board_init(void)
/* Turn off unused Flash & SRAM */
am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_FLASH512K);
am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_SRAM32K);
//am_hal_pwrctrl_memory_enable(AM_HAL_PWRCTRL_MEMEN_SRAM32K);
#endif

2
bsp/apollo2/board/flash.c
View File

@ -140,7 +140,7 @@ int rt_hw_rom_init(void)
/* register the device */
rt_device_register(&device, "rom", RT_DEVICE_FLAG_RDWR);
rt_kprintf("register device rom!\r\n");
//rt_kprintf("register device rom!\r\n");
return 0;
}

146
bsp/apollo2/board/gpio.c
View File

@ -24,10 +24,14 @@
#include <rtthread.h>
#include <rtdevice.h>
#include <rthw.h>
#include "am_mcu_apollo.h"
#ifdef RT_USING_PIN
#define APLLO2_PIN_NUMBERS 64 //[34, 64]
struct rt_pin_irq_hdr am_pin_irq_hdr_tab[64];
void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
{
if (mode == PIN_MODE_OUTPUT)
@ -43,12 +47,17 @@ void am_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
else if (mode == PIN_MODE_INPUT_PULLUP)
{
/* input setting: pull up. */
am_hal_gpio_pin_config(pin, AM_HAL_GPIO_INPUT);
}
else if (mode == PIN_MODE_INPUT_PULLDOWN)
{
/* input setting: pull down. */
am_hal_gpio_pin_config(pin, AM_HAL_GPIO_OPENDRAIN);
}
else
{
/* input setting:default. */
am_hal_gpio_pin_config(pin, AM_HAL_GPIO_INPUT);
am_hal_gpio_pin_config(pin, AM_HAL_GPIO_3STATE);
}
}
@ -58,40 +67,159 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
{
am_hal_gpio_out_bit_clear(pin);
}
else
else if (value == PIN_HIGH)
{
am_hal_gpio_out_bit_set(pin);
}
}
}
int am_pin_read(rt_device_t dev, rt_base_t pin)
{
int value = PIN_LOW;
if (am_hal_gpio_input_bit_read(pin) == 0)
if (am_hal_gpio_pin_config_read(pin) == AM_HAL_GPIO_OUTPUT)
{
value = PIN_LOW;
if (am_hal_gpio_out_bit_read(pin) == 0)
{
value = PIN_LOW;
}
else
{
value = PIN_HIGH;
}
}
else
{
value = PIN_HIGH;
if (am_hal_gpio_input_bit_read(pin) == 0)
{
value = PIN_LOW;
}
else
{
value = PIN_HIGH;
}
}
return value;
}
const static struct rt_pin_ops _am_pin_ops =
rt_err_t am_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
rt_uint32_t mode, void (*hdr)(void *args), void *args)
{
rt_base_t level;
rt_int32_t irqindex = -1;
irqindex = pin;
level = rt_hw_interrupt_disable();
if(am_pin_irq_hdr_tab[irqindex].pin == pin &&
am_pin_irq_hdr_tab[irqindex].hdr == hdr &&
am_pin_irq_hdr_tab[irqindex].mode == mode &&
am_pin_irq_hdr_tab[irqindex].args == args
)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
if(am_pin_irq_hdr_tab[irqindex].pin != -1)
{
rt_hw_interrupt_enable(level);
return -RT_EBUSY;
}
am_pin_irq_hdr_tab[irqindex].pin = pin;
am_pin_irq_hdr_tab[irqindex].hdr = hdr;
am_pin_irq_hdr_tab[irqindex].mode = mode;
am_pin_irq_hdr_tab[irqindex].args = args;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t am_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
{
rt_base_t level;
rt_int32_t irqindex = -1;
irqindex = pin;
level = rt_hw_interrupt_disable();
if(am_pin_irq_hdr_tab[irqindex].pin == -1)
{
rt_hw_interrupt_enable(level);
return RT_EOK;
}
am_pin_irq_hdr_tab[irqindex].pin = -1;
am_pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
am_pin_irq_hdr_tab[irqindex].mode = 0;
am_pin_irq_hdr_tab[irqindex].args = RT_NULL;
rt_hw_interrupt_enable(level);
return RT_EOK;
}
rt_err_t am_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
{
rt_base_t level;
rt_int32_t irqindex = -1;
irqindex = pin;
if (enabled == PIN_IRQ_ENABLE)
{
level = rt_hw_interrupt_disable();
/* Configure the GPIO/button interrupt polarity */
if (am_pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_RISING)
{
am_hal_gpio_int_polarity_bit_set(am_pin_irq_hdr_tab[irqindex].pin, AM_HAL_GPIO_RISING);
}
else if (am_pin_irq_hdr_tab[irqindex].mode == PIN_IRQ_MODE_FALLING)
{
am_hal_gpio_int_polarity_bit_set(am_pin_irq_hdr_tab[irqindex].pin, AM_HAL_GPIO_FALLING);
}
/* Clear the GPIO Interrupt (write to clear) */
am_hal_gpio_int_clear(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin));
/* Enable the GPIO/button interrupt */
am_hal_gpio_int_enable(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin));
rt_hw_interrupt_enable(level);
}
else if (enabled == PIN_IRQ_DISABLE)
{
if (am_hal_gpio_int_enable_get() != AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin))
{
return RT_ENOSYS;
}
/* Disable the GPIO/button interrupt */
am_hal_gpio_int_disable(AM_HAL_GPIO_BIT(am_pin_irq_hdr_tab[irqindex].pin));
}
else
{
return RT_ENOSYS;
}
return RT_EOK;
}
const static struct rt_pin_ops am_pin_ops =
{
am_pin_mode,
am_pin_write,
am_pin_read,
am_pin_attach_irq,
am_pin_dettach_irq,
am_pin_irq_enable,
};
int rt_hw_pin_init(void)
{
rt_device_pin_register("pin", &_am_pin_ops, RT_NULL);
rt_device_pin_register("pin", &am_pin_ops, RT_NULL);
rt_kprintf("pin_init!\n");
//rt_device_pin_irq_register("pin", &am_pin_ops, RT_NULL);
//rt_kprintf("pin_init!\n");
return 0;
}

44
bsp/apollo2/board/i2c.c
View File

@ -25,7 +25,6 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "am_mcu_apollo.h"
#include "board.h"
/* I2C0 */
#define AM_I2C0_IOM_INST 0
@ -43,6 +42,14 @@
#define I2C2_GPIO_SDA 25
#define I2C2_GPIO_CFG_SDA AM_HAL_PIN_25_M2SDA
/* I2C3 */
#define AM_I2C3_IOM_INST 3
#define I2C3_GPIO_SCL 42
#define I2C3_GPIO_CFG_SCK AM_HAL_PIN_42_M3SCL
#define I2C3_GPIO_SDA 43
#define I2C3_GPIO_CFG_SDA AM_HAL_PIN_43_M3SDA
/* I2C4 */
#define AM_I2C4_IOM_INST 4
@ -76,7 +83,7 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus,
struct am_i2c_bus * am_i2c_bus = (struct am_i2c_bus *)bus;
struct rt_i2c_msg *msg;
int i;
rt_int32_t ret = RT_EOK;
rt_uint32_t msg_len = 0;
for (i = 0; i < num; i++)
{
@ -84,16 +91,16 @@ rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus,
if (msg->flags == RT_I2C_RD)
{
am_hal_iom_i2c_read(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW);
msg_len += msg->len;
}
else if(msg->flags == RT_I2C_WR)
{
am_hal_iom_i2c_write(am_i2c_bus->u32Module, msg->addr, (uint32_t *)msg->buf, msg->len, AM_HAL_IOM_RAW);
msg_len += (msg->len - 1);
}
ret++;
}
return ret;
return msg_len;
}
rt_err_t rt_i2c_bus_control(struct rt_i2c_bus_device *bus,
@ -136,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_0 =
#ifdef RT_USING_I2C1
static struct am_i2c_bus am_i2c_bus_1 =
{
{0},
{1},
AM_I2C1_IOM_INST
};
#endif
@ -144,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_1 =
#ifdef RT_USING_I2C2
static struct am_i2c_bus am_i2c_bus_2 =
{
{1},
{2},
AM_I2C2_IOM_INST
};
#endif
@ -152,7 +159,7 @@ static struct am_i2c_bus am_i2c_bus_2 =
#ifdef RT_USING_I2C3
static struct am_i2c_bus am_i2c_bus_3 =
{
{2},
{3},
AM_I2C3_IOM_INST
};
#endif
@ -160,7 +167,7 @@ static struct am_i2c_bus am_i2c_bus_3 =
#ifdef RT_USING_I2C4
static struct am_i2c_bus am_i2c_bus_4 =
{
{3},
{4},
AM_I2C4_IOM_INST
};
#endif
@ -203,6 +210,23 @@ int rt_i2c_init(void)
rt_i2c_bus_device_register(&am_i2c->parent, "i2c2");
#endif
#ifdef RT_USING_I2C3
/* init i2c gpio */
am_hal_gpio_pin_config(I2C3_GPIO_SCL, I2C3_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
am_hal_gpio_pin_config(I2C3_GPIO_SDA, I2C3_GPIO_CFG_SDA | AM_HAL_GPIO_PULL6K);
/* Initialize IOM 3 in I2C mode at 400KHz */
am_hal_iom_pwrctrl_enable(AM_I2C3_IOM_INST);
g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ;
am_hal_iom_config(AM_I2C3_IOM_INST, &g_sIOMConfig);
am_hal_iom_enable(AM_I2C3_IOM_INST);
/* init i2c bus device */
am_i2c = &am_i2c_bus_3;
am_i2c->parent.ops = &am_i2c_ops;
rt_i2c_bus_device_register(&am_i2c->parent, "i2c3");
#endif
#ifdef RT_USING_I2C4
/* init i2c gpio */
am_hal_gpio_pin_config(I2C4_GPIO_SCL, I2C4_GPIO_CFG_SCK | AM_HAL_GPIO_PULL6K);
@ -220,7 +244,7 @@ int rt_i2c_init(void)
rt_i2c_bus_device_register(&am_i2c->parent, "i2c4");
#endif
rt_kprintf("i2c_init!\n");
//rt_kprintf("i2c_init!\n");
return 0;
}

101
bsp/apollo2/board/pdm.c
View File

@ -25,15 +25,15 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "am_mcu_apollo.h"
#include "board.h"
#ifdef RT_USING_PDM
/* sem define */
rt_sem_t pdmsem = RT_NULL;
/* messagequeue define */
struct rt_messagequeue pdm_mq;
#define NWA_FRAME_MS 10
#define NWA_FRAME_SAMPLES (16*NWA_FRAME_MS) /* 16k, 16bit, mono audio data */
static rt_uint8_t am_pdm_buffer_pool[1024];
#define NWA_FRAME_SAMPLES 160 /* 8k, 16bit, mono audio data */
#define PDM_FIFO_THRESHOLD NWA_FRAME_SAMPLES
#define PDM_GPIO_CLK 22
@ -41,23 +41,16 @@ rt_sem_t pdmsem = RT_NULL;
#define PDM_GPIO_DATA 23
#define PDM_GPIO_CFG_DATA AM_HAL_PIN_23_PDM_DATA
#define PING_PONG_BUF_SIZE 8000*NWA_FRAME_MS
static rt_uint16_t am_pdm_buffer_pool[PING_PONG_BUF_SIZE];
static rt_uint8_t pdm_flag = 0;
static rt_uint16_t pdm_cnt = 0;
static am_hal_pdm_config_t g_sPDMConfig =
{
AM_HAL_PDM_PCFG_LRSWAP_DISABLE | AM_HAL_PDM_PCFG_RIGHT_PGA_P105DB | AM_HAL_PDM_PCFG_LEFT_PGA_P105DB
| AM_HAL_PDM_PCFG_MCLKDIV_DIV1 | AM_HAL_PDM_PCFG_SINC_RATE(48) | AM_HAL_PDM_PCFG_ADCHPD_ENABLE
| AM_HAL_PDM_PCFG_HPCUTOFF(0xB) | AM_HAL_PDM_PCFG_CYCLES(0x1) | AM_HAL_PDM_PCFG_SOFTMUTE_DISABLE
| AM_HAL_PDM_PCFG_PDMCORE_ENABLE, /* Set the PDM configuration */
AM_REG_PDM_VCFG_IOCLKEN_EN | AM_HAL_PDM_VCFG_RSTB_NORMAL | AM_REG_PDM_VCFG_PDMCLKSEL_750KHz
| AM_HAL_PDM_VCFG_PDMCLK_ENABLE | AM_HAL_PDM_VCFG_I2SMODE_DISABLE | AM_HAL_PDM_VCFG_BCLKINV_DISABLE
| AM_HAL_PDM_VCFG_DMICDEL_DISABLE | AM_HAL_PDM_VCFG_SELAP_INTERNAL | AM_HAL_PDM_VCFG_PACK_DISABLE
| AM_HAL_PDM_VCFG_CHANNEL_RIGHT, /* Set the Voice Configuration */
PDM_FIFO_THRESHOLD, /* Select the FIFO PCM sample threshold */
AM_HAL_PDM_PCFG_LRSWAP_DISABLE | AM_HAL_PDM_PCFG_RIGHT_PGA_0DB | AM_HAL_PDM_PCFG_LEFT_PGA_0DB
| AM_HAL_PDM_PCFG_MCLKDIV_DIV1 | AM_HAL_PDM_PCFG_SINC_RATE(48) | AM_HAL_PDM_PCFG_ADCHPD_ENABLE
| AM_HAL_PDM_PCFG_HPCUTOFF(0x1) | AM_HAL_PDM_PCFG_CYCLES(0x1) | AM_HAL_PDM_PCFG_SOFTMUTE_DISABLE
| AM_HAL_PDM_PCFG_PDMCORE_ENABLE, /* Set the PDM configuration */
AM_HAL_PDM_IOCLK_750KHZ | AM_HAL_PDM_VCFG_RSTB_NORMAL | AM_HAL_PDM_VCFG_PDMCLK_ENABLE
| AM_HAL_PDM_VCFG_I2SMODE_DISABLE | AM_HAL_PDM_VCFG_BCLKINV_DISABLE | AM_HAL_PDM_VCFG_DMICDEL_DISABLE
| AM_HAL_PDM_VCFG_SELAP_INTERNAL | AM_HAL_PDM_VCFG_PACK_DISABLE | AM_HAL_PDM_VCFG_CHANNEL_LEFT, /* Set the Voice Configuration */
PDM_FIFO_THRESHOLD, /* Select the FIFO PCM sample threshold 0~256 */
};
/**
@ -71,28 +64,13 @@ static am_hal_pdm_config_t g_sPDMConfig =
*/
rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size)
{
uint8_t temp;
int i;
rt_uint8_t pdm_rbufftemp[340];
/* wait adc interrupt release sem forever */
rt_sem_take(pdmsem, RT_WAITING_FOREVER);
/* wait pdm message forever */
rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER);
for(i = 0; i < PING_PONG_BUF_SIZE; i++)
{
temp = (uint8_t)(am_pdm_buffer_pool[i] & 0xFF);
/* lower byte */
while ( AM_BFRn(UART, 0, FR, TXFF) );
AM_REGn(UART, 0, DR) = temp;
temp = (uint8_t)((am_pdm_buffer_pool[i] & 0xFF00)>>8);
/* higher byte */
while ( AM_BFRn(UART, 0, FR, TXFF) );
AM_REGn(UART, 0, DR) = temp;
}
/* copy the data */
//rt_memcpy(buff, am_pdm_buffer_pool, size*sizeof(rt_uint16_t));
pdm_flag = 0;
rt_memcpy(buff, (char *)pdm_rbufftemp, size);
return 0;
}
@ -108,12 +86,9 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size)
*/
void am_pdm_start(void)
{
/* adcsem create */
pdmsem = rt_sem_create("pdmsem", 0, RT_IPC_FLAG_FIFO);
/* Enable PDM */
am_hal_pdm_enable();
am_hal_interrupt_enable(AM_HAL_INTERRUPT_PDM);
am_hal_pdm_enable();
}
/**
@ -128,11 +103,8 @@ void am_pdm_start(void)
void am_pdm_stop(void)
{
/* Disable PDM */
am_hal_pdm_disable();
am_hal_interrupt_disable(AM_HAL_INTERRUPT_PDM);
/* adcsem delete */
rt_sem_delete(pdmsem);
am_hal_pdm_disable();
}
/**
@ -153,7 +125,7 @@ uint8_t am_pdm_left_gain_get(void)
/**
* @brief Set the pdm left gain.
*
* @param None.
* @param gain_val.
*
* This function Set the pdm left gain.
*
@ -183,7 +155,7 @@ uint8_t am_pdm_right_gain_get(void)
/**
* @brief Set the pdm right gain.
*
* @param None.
* @param gain_val.
*
* This function Set the pdm right gain.
*
@ -204,33 +176,19 @@ void am_pdm_right_gain_set(uint8_t gain_val)
*/
void am_pdm_isr (void)
{
uint32_t ui32FifoData;
int i;
rt_int16_t pdm_sbufftemp[160];
/* Clear the PDM interrupt */
am_hal_pdm_int_clear(AM_HAL_PDM_INT_UNDFL | AM_HAL_PDM_INT_OVF | AM_HAL_PDM_INT_FIFO);
for (i = 0; i < PDM_FIFO_THRESHOLD; i++) /* adjust as needed */
{
ui32FifoData = am_hal_pdm_fifo_data_read();
if(pdm_flag == 0)
{
am_pdm_buffer_pool[pdm_cnt * PDM_FIFO_THRESHOLD + i] = (uint16_t)ui32FifoData;
}
pdm_sbufftemp[i] = (rt_int16_t)am_hal_pdm_fifo_data_read();
}
if(pdm_flag == 0)
pdm_cnt ++;
if(pdm_cnt == PING_PONG_BUF_SIZE/PDM_FIFO_THRESHOLD) /* 500 means 10 second logging under 8k sampling rate */
{
pdm_cnt = 0;
pdm_flag = 1;
/* release pdmsem */
rt_sem_release(pdmsem);
}
/* send the message */
rt_mq_send(&pdm_mq, pdm_sbufftemp, PDM_FIFO_THRESHOLD*sizeof(rt_int16_t));
}
/**
@ -258,7 +216,14 @@ int rt_hw_pdm_init(void)
/* Clear PDM interrupts */
am_hal_pdm_int_clear(AM_HAL_PDM_INT_UNDFL | AM_HAL_PDM_INT_OVF | AM_HAL_PDM_INT_FIFO);
rt_kprintf("pdm_init!\n");
/* messagequeue init */
rt_mq_init(&pdm_mq, "mq_pdm",
&am_pdm_buffer_pool[0],
340 - sizeof(void*),
sizeof(am_pdm_buffer_pool),
RT_IPC_FLAG_FIFO);
//rt_kprintf("pdm_init!\n");
return 0;
}

2
bsp/apollo2/board/pdm.h
View File

@ -31,7 +31,7 @@
* @brief External function definitions
*
*/
int rt_hw_pdm_init(void);
int rt_pdm_init(void);
rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size);
void am_pdm_start(void);
void am_pdm_stop(void);

2
bsp/apollo2/board/pwm.h
View File

@ -32,5 +32,7 @@
*
*/
int rt_hw_pwm_init(void);
void am_pwm_start(int led);
void am_pwm_stop(int led);
#endif // __PWM_H_

1
bsp/apollo2/board/rtc.c
View File

@ -118,7 +118,6 @@ int rt_hw_rtc_init(void)
#if RTC_CLK_SRC == XT
/* Enable the XT for the RTC */
//am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_LFRC);
am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT);
/* Select XT for RTC clock source */

17
bsp/apollo2/board/smbus.c
View File

@ -25,23 +25,22 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "am_mcu_apollo.h"
#include "board.h"
#ifdef RT_USING_SMBUS
#define SMBUS_GPIO_SDA 5
#define SMBUS_GPIO_SCL 6
#define mSDA_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SCL) /* Clear SDA line */
#define mSDA_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SCL) /* Set SDA line */
#define mSCL_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SDA) /* Clear SCL line */
#define mSCL_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SDA) /* Set SCL line */
#define mSDA_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SDA) /* Clear SDA line */
#define mSDA_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SDA) /* Set SDA line */
#define mSCL_LOW() am_hal_gpio_out_bit_clear(SMBUS_GPIO_SCL) /* Clear SCL line */
#define mSCL_HIGH() am_hal_gpio_out_bit_set(SMBUS_GPIO_SCL) /* Set SCL line */
#define mSDA_READ() am_hal_gpio_input_bit_read(SMBUS_GPIO_SCL) /* Read SCL line */
#define mSDA_READ() am_hal_gpio_input_bit_read(SMBUS_GPIO_SDA) /* Read SDA line */
#define mSDA_IN() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_INPUT | AM_HAL_GPIO_PULL6K) /* Set SDA as Input */
#define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */
#define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */
#define mSDA_IN() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_INPUT | AM_HAL_GPIO_PULL6K) /* Set SDA as Input */
#define mSDA_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT) /* Set SDA as Output */
#define mSCL_OUT() am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT) /* Set SCL as Output */
#define ACK 0
#define NACK 1

92
bsp/apollo2/board/spi.c
View File

@ -25,10 +25,9 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "am_mcu_apollo.h"
#include "board.h"
#include "spi.h"
/* SPI1 */
/* SPI0 */
#define AM_SPI0_IOM_INST 0
#define SPI0_GPIO_SCK 5
@ -38,17 +37,17 @@
#define SPI0_GPIO_MOSI 7
#define SPI0_GPIO_CFG_MOSI AM_HAL_PIN_7_M0MOSI
/* SPI2 */
/* SPI1 */
#define AM_SPI1_IOM_INST 1
static am_hal_iom_config_t g_sIOMConfig =
{
AM_HAL_IOM_SPIMODE, // ui32InterfaceMode
AM_HAL_IOM_8MHZ, // ui32ClockFrequency
AM_HAL_IOM_400KHZ, // ui32ClockFrequency
0, // bSPHA
0, // bSPOL
4, // ui8WriteThreshold
60, // ui8ReadThreshold
80, // ui8WriteThreshold
80, // ui8ReadThreshold
};
/* AM spi driver */
@ -64,7 +63,19 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
struct am_spi_bus * am_spi_bus = (struct am_spi_bus *)device->bus;
rt_uint32_t max_hz = configuration->max_hz;
if(max_hz >= 8000000)
if(max_hz >= 24000000)
{
g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_24MHZ;
}
else if(max_hz >= 16000000)
{
g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_16MHZ;
}
else if(max_hz >= 12000000)
{
g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_12MHZ;
}
else if(max_hz >= 8000000)
{
g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_8MHZ;
}
@ -147,7 +158,6 @@ static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configurat
/* init SPI */
am_hal_iom_disable(am_spi_bus->u32Module);
am_hal_iom_pwrctrl_enable(am_spi_bus->u32Module);
am_hal_iom_config(am_spi_bus->u32Module, &g_sIOMConfig);
am_hal_iom_enable(am_spi_bus->u32Module);
@ -167,14 +177,12 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
/* take CS */
if (message->cs_take)
{
;
am_hal_gpio_out_bit_clear(am_spi_cs->chip_select);
}
// ¶ÁÊý¾Ý
if (recv_ptr != RT_NULL)
{
u32TransferSize = u32BytesRemaining;
while (u32BytesRemaining)
{
/* Set the transfer size to either 64, or the number of remaining
@ -182,22 +190,21 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
if (u32BytesRemaining > 64)
{
u32TransferSize = 64;
am_hal_gpio_pin_config(SPI0_GPIO_MOSI, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_PULL6K);
am_hal_gpio_out_bit_set(SPI0_GPIO_MOSI);
am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select,
(uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW);
(uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_RAW);
am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K);
}
else
{
u32TransferSize = u32BytesRemaining;
/* release CS */
if(message->cs_release)
{
am_hal_gpio_pin_config(SPI0_GPIO_MOSI, AM_HAL_GPIO_OUTPUT | AM_HAL_GPIO_PULL6K);
am_hal_gpio_out_bit_set(SPI0_GPIO_MOSI);
am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select,
(uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_RAW);
}
else
{
am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select,
(uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW);
am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K);
}
}
@ -207,33 +214,26 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
}
// дÊý¾Ý
else if (send_ptr != RT_NULL)
else
{
while (u32BytesRemaining)
{
/* Set the transfer size to either 32, or the number of remaining
bytes, whichever is smaller */
if (u32BytesRemaining > 32)
if (u32BytesRemaining > 64)
{
u32TransferSize = 32;
u32TransferSize = 64;
am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
(uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW);
(uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW);
}
else
{
u32TransferSize = u32BytesRemaining;
/* release CS */
if (message->cs_release)
{
am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
(uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW);
}
else
{
am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
(uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW);
}
}
u32BytesRemaining -= u32TransferSize;
@ -241,6 +241,12 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
}
}
/* release CS */
if(message->cs_release)
{
am_hal_gpio_out_bit_set(am_spi_cs->chip_select);
}
return message->length;
}
@ -250,31 +256,31 @@ static const struct rt_spi_ops am_spi_ops =
xfer
};
#ifdef RT_USING_SPI1
static struct am_spi_bus am_spi_bus_1 =
#ifdef RT_USING_SPI0
static struct am_spi_bus am_spi_bus_0 =
{
{0},
AM_SPI0_IOM_INST
};
#endif /* #ifdef RT_USING_SPI1 */
#endif /* #ifdef RT_USING_SPI0 */
#ifdef RT_USING_SPI2
static struct ambiq_spi_bus ambiq_spi_bus_2 =
#ifdef RT_USING_SPI1
static struct am_spi_bus am_spi_bus_1 =
{
{1},
{0},
AM_SPI1_IOM_INST
};
#endif /* #ifdef RT_USING_SPI2 */
#endif /* #ifdef RT_USING_SPI1 */
int yr_hw_spi_init(void)
{
struct am_spi_bus* am_spi;
#ifdef RT_USING_SPI1
#ifdef RT_USING_SPI0
/* init spi gpio */
am_hal_gpio_pin_config(SPI0_GPIO_SCK, SPI0_GPIO_CFG_SCK);
am_hal_gpio_pin_config(SPI0_GPIO_MISO, SPI0_GPIO_CFG_MISO);
am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI);
am_hal_gpio_pin_config(SPI0_GPIO_MISO, SPI0_GPIO_CFG_MISO | AM_HAL_GPIO_PULL6K);
am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI | AM_HAL_GPIO_PULL6K);
/* Initialize IOM 0 in SPI mode at 100KHz */
am_hal_iom_pwrctrl_enable(AM_SPI0_IOM_INST);
@ -282,11 +288,11 @@ int yr_hw_spi_init(void)
am_hal_iom_enable(AM_SPI0_IOM_INST);
//init spi bus device
am_spi = &am_spi_bus_1;
rt_spi_bus_register(&am_spi->parent, "spi1", &am_spi_ops);
am_spi = &am_spi_bus_0;
rt_spi_bus_register(&am_spi->parent, "spi0", &am_spi_ops);
#endif
rt_kprintf("spi init!\n");
//rt_kprintf("spi init!\n");
return 0;
}

21
bsp/apollo2/board/uart.c
View File

@ -25,7 +25,6 @@
#include <rtthread.h>
#include <rtdevice.h>
#include "am_mcu_apollo.h"
#include "board.h"
/* USART0 */
#define AM_UART0_INST 0
@ -165,8 +164,14 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf
else if (cfg->stop_bits == STOP_BITS_2)
uart_cfg.bTwoStopBits = true;
uart_cfg.ui32Parity = cfg->parity;
uart_cfg.ui32FlowCtrl = AM_HAL_UART_PARITY_NONE;
if (cfg->parity == PARITY_NONE)
uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE;
else if (cfg->parity == PARITY_ODD)
uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD;
else if (cfg->parity == PARITY_EVEN)
uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN;
uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE;
/* UART Config */
am_hal_uart_config(uart->uart_device, &uart_cfg);
@ -181,7 +186,7 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf
am_hal_uart_enable(uart->uart_device);
/* Enable interrupts */
am_hal_uart_int_enable(uart->uart_device, AM_HAL_UART_INT_RX_TMOUT | AM_HAL_UART_INT_RX | AM_HAL_UART_INT_TX);
am_hal_uart_int_enable(uart->uart_device, AM_HAL_UART_INT_RX_TMOUT | AM_HAL_UART_INT_RX);
/* Enable the uart interrupt in the NVIC */
am_hal_interrupt_enable(uart->uart_interrupt);
@ -231,7 +236,7 @@ static int am_putc(struct rt_serial_device *serial, char c)
//if (txsize > 0)
{
am_hal_uart_char_transmit_buffered(uart->uart_device, c);
}
}
/* Wait until busy bit clears to make sure UART fully transmitted last byte */
while ( am_hal_uart_flags_get(uart->uart_device) & AM_HAL_UART_FR_BUSY );
@ -400,9 +405,6 @@ int rt_hw_uart_init(void)
#if defined(RT_USING_UART0)
uart = &uart0;
config.baud_rate = BAUD_RATE_115200;
config.data_bits = DATA_BITS_8;
config.stop_bits = STOP_BITS_1;
config.parity = PARITY_NONE;
RCC_Configuration(uart);
@ -418,9 +420,6 @@ int rt_hw_uart_init(void)
#if defined(RT_USING_UART1)
uart = &uart1;
config.baud_rate = BAUD_RATE_115200;
config.data_bits = DATA_BITS_8;
config.stop_bits = STOP_BITS_1;
config.parity = PARITY_NONE;
RCC_Configuration(uart);

1
bsp/apollo2/libraries/drivers/SConscript
View File

@ -10,6 +10,7 @@ hal/am_hal_clkgen.c
hal/am_hal_debug.c
hal/am_hal_cachectrl.c
hal/am_hal_pwrctrl.c
hal/am_hal_mcuctrl.c
hal/am_hal_sysctrl.c
hal/am_hal_reset.c
hal/am_hal_stimer.c

2
bsp/apollo2/libraries/drivers/am_mcu_apollo.h
View File

@ -44,7 +44,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_MCU_APOLLO_H

2
bsp/apollo2/libraries/drivers/hal/am_hal_adc.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_adc.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_ADC_H
#define AM_HAL_ADC_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! @name Clock Selection
@ -309,6 +304,11 @@ am_hal_adc_config_t;
(((value) & AM_REG_ADC_FIFO_COUNT_M) >> AM_REG_ADC_FIFO_COUNT_S)
//! @}
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

2
bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_cachectrl.h
View File

@ -38,17 +38,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_CACHECTRL_H
#define AM_HAL_CACHECTRL_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Cache configuration structure
@ -186,6 +181,11 @@ extern const am_hal_cachectrl_config_t am_hal_cachectrl_defaults;
AM_HAL_CACHECTRL_CACHECFG_DATA_CLKGATE_ENABLE | \
AM_HAL_CACHECTRL_CACHECFG_CONFIG_2WAY_512)
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

28
bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -287,16 +287,20 @@ am_hal_clkgen_int_clear(uint32_t ui32Interrupt)
//! AM_HAL_CLKGEN_OSC_LFRC
//! AM_HAL_CLKGEN_OSC_XT
//!
//! @return 0 None.
//! @return None.
//
//*****************************************************************************
void
am_hal_clkgen_osc_start(uint32_t ui32OscFlags)
{
//
// Start the oscillator(s).
//
AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags;
if ( ui32OscFlags & (AM_HAL_CLKGEN_OSC_LFRC | AM_HAL_CLKGEN_OSC_XT) )
{
//
// Start the oscillator(s).
// Note that these bits are cleared in order to enable the oscillator.
//
AM_REG(CLKGEN, OCTRL) &= ~ui32OscFlags;
}
}
//*****************************************************************************
@ -318,10 +322,14 @@ am_hal_clkgen_osc_start(uint32_t ui32OscFlags)
void
am_hal_clkgen_osc_stop(uint32_t ui32OscFlags)
{
//
// Stop the oscillator(s).
//
AM_REG(CLKGEN, OCTRL) |= ui32OscFlags;
if ( ui32OscFlags & (AM_HAL_CLKGEN_OSC_LFRC | AM_HAL_CLKGEN_OSC_XT) )
{
//
// Stop the oscillator(s).
// Note that these bits are set in order to stop the oscillator.
//
AM_REG(CLKGEN, OCTRL) |= ui32OscFlags;
}
}
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_clkgen.h
View File

@ -38,17 +38,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_CLKGEN_H
#define AM_HAL_CLKGEN_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! @name System Clock max frequency
@ -178,6 +173,11 @@ extern "C"
(AM_REG_CLKGEN_UARTEN_UART0EN_##entype << \
AM_HAL_CLKGEN_UARTEN_UARTENn_S(module))
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

21
bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -68,11 +68,12 @@
// still pass in the event of a timer rollover.
//
//*****************************************************************************
//! Timer read workaround: Do count values differ by one tick or less.
#define adjacent(A, B) (((A) == (B)) || (((A) + 1) == (B)) || ((B) == 0))
//*****************************************************************************
//
// Array of function pointers for handling CTimer interrupts.
//! Array of function pointers for handling CTimer interrupts.
//
//*****************************************************************************
am_hal_ctimer_handler_t am_hal_ctimer_ppfnHandlers[16];
@ -162,10 +163,10 @@ back2back_reads( uint32_t u32TimerAddr, uint32_t u32Data[])
//*****************************************************************************
//
// @brief Check to see if the given CTimer is using the HFRC
//
// Note - Calls to this function should be from inside a critical section.
//
//! @brief Check to see if the given CTimer is using the HFRC
//!
//! @note Calls to this function should be from inside a critical section.
//!
//! @return None.
//
//*****************************************************************************
@ -501,7 +502,7 @@ am_hal_ctimer_config(uint32_t ui32TimerNumber,
//! @param ui32TimerSegment specifies which segment of the timer should be
//! enabled.
//!
//! @param ui32Configval specifies the configuration options for the selected
//! @param ui32ConfigVal specifies the configuration options for the selected
//! timer.
//!
//! This function should be used to perform the initial set-up of the
@ -823,7 +824,7 @@ uint32_t
am_hal_ctimer_read(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
{
volatile uint32_t ui32Value = 0;
uint32_t ui32Values[3] = {0};
uint32_t ui32Values[4] = {0, };
uint32_t ui32TimerAddrTbl[4] =
{
REG_CTIMER_BASEADDR + AM_REG_CTIMER_TMR0_O,
@ -1023,7 +1024,7 @@ am_hal_ctimer_pin_disable(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment)
//!
//! @param ui32TimerSegment specifies which segment of the timer to use.
//!
//! @param bInvertOutpt determines whether the output should be inverted. If
//! @param bInvertOutput determines whether the output should be inverted. If
//! true, the timer output pin for the selected timer segment will be
//! inverted.
//!
@ -1131,7 +1132,7 @@ am_hal_ctimer_compare_set(uint32_t ui32TimerNumber, uint32_t ui32TimerSegment,
pui32CmprRegA = (uint32_t *)(AM_REG_CTIMERn(0) +
AM_REG_CTIMER_CMPRA0_O +
(ui32TimerNumber * TIMER_OFFSET));
pui32CmprRegB = pui32CmprRegA + CTIMER_CMPR_OFFSET;
pui32CmprRegB = pui32CmprRegA + CTIMER_CMPR_OFFSET / 4;
//
// Write the compare register with the selected value.

14
bsp/apollo2/libraries/drivers/hal/am_hal_ctimer.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_CTIMER_H
#define AM_HAL_CTIMER_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! Number of timers
@ -114,7 +109,7 @@ extern "C"
//!
//! These options are to be used with the \e am_hal_ctimer_config_t structure
//! used by \e am_hal_ctimer_config
//! @{
//! @{
//
//*****************************************************************************
#define AM_HAL_CTIMER_CLK_PIN AM_REG_CTIMER_CTRL0_TMRA0CLK(0x0)
@ -208,6 +203,11 @@ am_hal_ctimer_config_t;
//*****************************************************************************
typedef void (*am_hal_ctimer_handler_t)(void);
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

2
bsp/apollo2/libraries/drivers/hal/am_hal_debug.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_debug.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_DEBUG_H
#define AM_HAL_DEBUG_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Debug assert macros.
@ -73,6 +68,11 @@ extern "C"
#endif // AM_DEBUG_ASSERT
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function prototypes.

43
bsp/apollo2/libraries/drivers/hal/am_hal_flash.c
View File

@ -54,7 +54,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -428,6 +428,47 @@ am_hal_flash_delay(uint32_t ui32Iterations)
g_am_hal_flash.delay_cycles(ui32Iterations);
}
//*****************************************************************************
//
//! @brief Delays for a desired amount of cycles while also waiting for a
//! status change.
//!
//! @param ui32usMaxDelay - Maximum number of ~1uS delay loops.
//! @param ui32Address - Address of the register for the status change.
//! @param ui32Mask - Mask for the status change.
//! @param ui32Value - Target value for the status change.
//!
//! This function will delay for approximately the given number of microseconds
//! while checking for a status change, exiting when either the given time has
//! expired or the status change is detected.
//!
//! @returns 0 = timeout.
//! 1 = status change detected.
//
//*****************************************************************************
uint32_t
am_hal_flash_delay_status_change(uint32_t ui32usMaxDelay, uint32_t ui32Address,
uint32_t ui32Mask, uint32_t ui32Value)
{
while ( ui32usMaxDelay-- )
{
//
// Check the status
//
if ( ( AM_REGVAL(ui32Address) & ui32Mask ) == ui32Value )
{
return 1;
}
//
// Call the BOOTROM cycle function to delay for about 1 microsecond.
//
am_hal_flash_delay( FLASH_CYCLES_US(1) );
}
return 0;
} // am_hal_flash_delay_status_change()
//*****************************************************************************
//
//! @brief Static Helper Function to check customer info valid bits erasure.

28
bsp/apollo2/libraries/drivers/hal/am_hal_flash.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_FLASH_H
#define AM_HAL_FLASH_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
#include <stdbool.h>
@ -94,13 +89,19 @@ extern "C"
//
#define AM_HAL_FLASH_ADDR2ABSPAGE(addr) ( addr >> 13 )
//*****************************************************************************
//
// Given an integer number of microseconds, convert to a value representing the
// number of am_hal_flash_delay() cycles that will provide that amount of delay.
// This macro is designed to take into account some of the call overhead.
//
// Given a number of microseconds, convert to a value representing the number of
// cycles that will give that delay. This macro is basically taking into account
// some of the call overhead.
// e.g. To provide a 2us delay:
// am_hal_flash_delay( FLASH_CYCLES_US(2) );
//
// IMPORTANT - Apollo2 is spec'ed for only 48MHz operation, so this macro
// assumes that.
//
//*****************************************************************************
#define FLASH_CYCLES_US(n) ((n * (AM_HAL_CLKGEN_FREQ_MAX_MHZ / 3)) - 4)
//
@ -223,6 +224,11 @@ extern g_am_hal_flash_t g_am_hal_flash;
#define AM_HAL_FLASH_INFO_CHUNK2INST(n) ((n >> 5) & 1
#define AM_HAL_FLASH_INFO_ADDR2CHUNK(n) ((n) >> 14)
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Function prototypes for the helper functions
@ -254,6 +260,10 @@ extern void am_hal_flash_recovery(uint32_t ui32RecoveryKey);
extern uint32_t am_hal_flash_load_ui32(uint32_t ui32Address);
extern void am_hal_flash_store_ui32(uint32_t ui32Address, uint32_t ui32Data);
extern void am_hal_flash_delay(uint32_t ui32Iterations);
extern uint32_t am_hal_flash_delay_status_change(uint32_t ui32Iterations,
uint32_t ui32Address,
uint32_t ui32Mask,
uint32_t ui32Value);
//
// These functions update security/protection bits in the customer INFO blOCK.

2
bsp/apollo2/libraries/drivers/hal/am_hal_global.c
View File

@ -43,7 +43,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_global.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_GLOBAL_H
#define AM_HAL_GLOBAL_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macro definitions
@ -107,6 +102,11 @@ extern "C"
//*****************************************************************************
extern volatile uint32_t g_ui32HALflags;
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif

4
bsp/apollo2/libraries/drivers/hal/am_hal_gpio.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -479,7 +479,7 @@ am_hal_gpio_int_register(uint32_t ui32GPIONumber,
//!
//! This function gets the state of one GPIO polarity bit.
//!
//! @note When the bit is a one the interrupt polarity is rising edge.
//! @note When the bit is a zero the interrupt polarity is rising edge.
//!
//! @return the current polarity.
//

19
bsp/apollo2/libraries/drivers/hal/am_hal_gpio.h
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -119,7 +119,7 @@
//*****************************************************************************
//
// Output options
// Output options (OUTCFG)
//
//*****************************************************************************
#define AM_HAL_GPIO_OUT_DISABLE ((0x0 << 1) << CFGVAL_GPIOCFG_S)
@ -127,6 +127,15 @@
#define AM_HAL_GPIO_OUT_OPENDRAIN ((0x2 << 1) << CFGVAL_GPIOCFG_S)
#define AM_HAL_GPIO_OUT_3STATE ((0x3 << 1) << CFGVAL_GPIOCFG_S)
//*****************************************************************************
//
// Special options for IOM0 and IOM4 clocks.
// For 24MHz operation, a special enable must be selected. The 24MHZ select is
// selected via bit0 of OUTCFG (which is, in a way,an alias of OUT_PUSHPULL).
//
//*****************************************************************************
#define AM_HAL_GPIO_24MHZ_ENABLE ((0x1 << 1) << CFGVAL_GPIOCFG_S)
//*****************************************************************************
//
// Pad configuration options.
@ -498,13 +507,13 @@
//! @return None.
//
//*****************************************************************************
#define am_hal_gpio_int_polarity_bit_set(ui32PinNumber, ui32Polarity) \
if ( (uint32_t)(ui32PinNumber) < AM_HAL_GPIO_MAX_PADS ) \
#define am_hal_gpio_int_polarity_bit_set(ui32BitNum, ui32Polarity) \
if ( (uint32_t)(ui32BitNum) < AM_HAL_GPIO_MAX_PADS ) \
{ \
AM_CRITICAL_BEGIN_ASM \
\
AM_REGn(GPIO, 0, PADKEY) = AM_REG_GPIO_PADKEY_KEYVAL; \
AM_HAL_GPIO_POL_W(ui32PinNumber, ui32Polarity); \
AM_HAL_GPIO_POL_W(ui32BitNum, ui32Polarity); \
AM_REGn(GPIO, 0, PADKEY) = 0; \
\
AM_CRITICAL_END_ASM \

22
bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.c
View File

@ -41,7 +41,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -133,7 +133,7 @@ static am_hal_i2c_bit_bang_priv_t am_hal_i2c_bit_bang_priv;
// Wait for any stretched clock to go high
// If it times out - return failure
//
static bool
static __inline bool
i2c_pull_and_wait_scl_hi(void)
{
// Maximum time to wait for clock stretching
@ -165,7 +165,7 @@ i2c_pull_and_wait_scl_hi(void)
//! returns None.
//
//*****************************************************************************
am_hal_i2c_bit_bang_enum_t
am_hal_i2c_bit_bang_enum_e
am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
uint32_t sda_gpio_number)
{
@ -192,7 +192,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
//
// Set up SCK GPIO configuration bi-direction, input
//
am_hal_gpio_pin_config(sck_gpio_number, AM_HAL_PIN_OPENDRAIN);
am_hal_gpio_pin_config(sck_gpio_number, AM_HAL_PIN_OPENDRAIN | AM_HAL_GPIO_INPEN);
//
// Set SDA GPIO data bit high so we aren't pulling down the data line
@ -201,7 +201,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
//
// Set up SDA GPIO configuration bi-direction, input
//
am_hal_gpio_pin_config(sda_gpio_number, AM_HAL_PIN_OPENDRAIN);
am_hal_gpio_pin_config(sda_gpio_number, AM_HAL_PIN_OPENDRAIN | AM_HAL_GPIO_INPEN);
// Now make sure we have control of the clock line
//
@ -284,7 +284,7 @@ am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
//! returns the byte received
//
//*****************************************************************************
static am_hal_i2c_bit_bang_enum_t
static __inline am_hal_i2c_bit_bang_enum_e
i2c_receive_byte(uint8_t *pRxByte, bool bNack)
{
int i;
@ -389,7 +389,7 @@ i2c_receive_byte(uint8_t *pRxByte, bool bNack)
//! }
//
//*****************************************************************************
static am_hal_i2c_bit_bang_enum_t
static __inline am_hal_i2c_bit_bang_enum_e
i2c_send_byte(uint8_t one_byte)
{
int i;
@ -478,13 +478,13 @@ i2c_send_byte(uint8_t one_byte)
//! returns ENUM{AM_HAL_I2C_BIT_BANG_SUCCESS,AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED}
//
//*****************************************************************************
am_hal_i2c_bit_bang_enum_t
am_hal_i2c_bit_bang_enum_e
am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes,
uint8_t *pData, uint8_t ui8Offset,
bool bUseOffset, bool bNoStop)
{
uint32_t ui32I;
am_hal_i2c_bit_bang_enum_t status = AM_HAL_I2C_BIT_BANG_SUCCESS;
am_hal_i2c_bit_bang_enum_e status = AM_HAL_I2C_BIT_BANG_SUCCESS;
if (i2c_pull_and_wait_scl_hi())
@ -617,13 +617,13 @@ am_hal_i2c_bit_bang_receive(uint8_t address, uint32_t number_of_bytes,
//! AM_HAL_I2C_BIT_BANG_ADDRESS_NAKED}
//
//*****************************************************************************
am_hal_i2c_bit_bang_enum_t
am_hal_i2c_bit_bang_enum_e
am_hal_i2c_bit_bang_send(uint8_t address, uint32_t number_of_bytes,
uint8_t *pData, uint8_t ui8Offset,
bool bUseOffset, bool bNoStop)
{
uint32_t ui32I;
am_hal_i2c_bit_bang_enum_t status;
am_hal_i2c_bit_bang_enum_e status;
bool data_naked = false;
if (i2c_pull_and_wait_scl_hi())

21
bsp/apollo2/libraries/drivers/hal/am_hal_i2c_bit_bang.h
View File

@ -40,17 +40,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_I2C_BIT_BANG_H
#define AM_HAL_I2C_BIT_BANG_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Enumerated return constants
@ -63,24 +58,30 @@ typedef enum
AM_HAL_I2C_BIT_BANG_DATA_NAKED,
AM_HAL_I2C_BIT_BANG_CLOCK_TIMEOUT,
AM_HAL_I2C_BIT_BANG_DATA_TIMEOUT,
}am_hal_i2c_bit_bang_enum_t;
AM_HAL_I2C_BIT_BANG_STATUS_MAX,
}am_hal_i2c_bit_bang_enum_e;
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions
//
//*****************************************************************************
extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_init(uint32_t sck_gpio_number,
uint32_t sda_gpio_number);
extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_send(uint8_t address,
extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_send(uint8_t address,
uint32_t number_of_bytes,
uint8_t *pData,
uint8_t ui8Offset,
bool bUseOffset,
bool bNoStop);
extern am_hal_i2c_bit_bang_enum_t am_hal_i2c_bit_bang_receive(uint8_t address,
extern am_hal_i2c_bit_bang_enum_e am_hal_i2c_bit_bang_receive(uint8_t address,
uint32_t number_of_bytes,
uint8_t *pData,
uint8_t ui8Offset,

8
bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.c
View File

@ -44,7 +44,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -190,7 +190,7 @@ am_hal_interrupt_priority_set(uint32_t ui32Interrupt, uint32_t ui32Priority)
//
// OR in the new priority.
//
*pui32PriorityReg |= (ui32Priority << ui32Shift);
*pui32PriorityReg = ui32OldPriority | (ui32Priority << ui32Shift);
}
//*****************************************************************************
@ -210,7 +210,7 @@ void am_hal_interrupt_pend_set(uint32_t ui32Interrupt)
//
// Check to see if the specified interrupt is valid for this MCU
//
if ( ui32Interrupt > 47 )
if ( ui32Interrupt > AM_HAL_INTERRUPT_MAX )
{
return;
}
@ -247,7 +247,7 @@ void am_hal_interrupt_pend_clear(uint32_t ui32Interrupt)
//
// Check to see if the specified interrupt is valid for this MCU
//
if ( ui32Interrupt > 47 )
if ( ui32Interrupt > AM_HAL_INTERRUPT_MAX )
{
return;
}

11
bsp/apollo2/libraries/drivers/hal/am_hal_interrupt.h
View File

@ -44,16 +44,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_INTERRUPT_H
#define AM_HAL_INTERRUPT_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! @name ISR number macros.
@ -66,6 +62,7 @@ extern "C"
//
// Hardware interrupts
//
#define AM_HAL_INTERRUPT_MAX (47) //AM_HAL_INTERRUPT_SOFTWARE3
#define AM_HAL_INTERRUPT_RESET 1
#define AM_HAL_INTERRUPT_NMI 2
#define AM_HAL_INTERRUPT_HARDFAULT 3
@ -130,6 +127,10 @@ extern "C"
//*****************************************************************************
#define AM_HAL_INTERRUPT_PRIORITY(n) (((uint32_t)(n) & 0x7) << 5)
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

1633
bsp/apollo2/libraries/drivers/hal/am_hal_iom.c
View File

File diff suppressed because it is too large Load Diff

120
bsp/apollo2/libraries/drivers/hal/am_hal_iom.h
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -79,11 +79,13 @@
#define AM_HAL_IOM_2MHZ 2000000
#define AM_HAL_IOM_1_5MHZ 1500000
#define AM_HAL_IOM_1MHZ 1000000
#define AM_HAL_IOM_800KHZ 800000
#define AM_HAL_IOM_750KHZ 750000
#define AM_HAL_IOM_500KHZ 500000
#define AM_HAL_IOM_400KHZ 400000
#define AM_HAL_IOM_375KHZ 375000
#define AM_HAL_IOM_250KHZ 250000
#define AM_HAL_IOM_200KHZ 200000
#define AM_HAL_IOM_125KHZ 125000
#define AM_HAL_IOM_100KHZ 100000
#define AM_HAL_IOM_50KHZ 50000
@ -176,18 +178,30 @@
#define AM_HAL_IOM_INT_FUNDFL AM_REG_IOMSTR_INTEN_FUNDFL_M
#define AM_HAL_IOM_INT_THR AM_REG_IOMSTR_INTEN_THR_M
#define AM_HAL_IOM_INT_CMDCMP AM_REG_IOMSTR_INTEN_CMDCMP_M
//! @}
//*****************************************************************************
//
//! @name IOM function errors
//! @brief Return values for IOM HAL function errors, such as with the function
//! am_hal_iom_error_status_get().
//!
//! @{
//
//*****************************************************************************
#define AM_HAL_IOM_ERR_INVALID_MODULE (1 << 30)
#define AM_HAL_IOM_INT_ALL ( \
AM_HAL_IOM_INT_ARB | \
AM_HAL_IOM_INT_STOP | \
AM_HAL_IOM_INT_START | \
AM_HAL_IOM_INT_ICMD | \
AM_HAL_IOM_INT_IACC | \
AM_HAL_IOM_INT_WTLEN | \
AM_HAL_IOM_INT_NAK | \
AM_HAL_IOM_INT_FOVFL | \
AM_HAL_IOM_INT_FUNDFL | \
AM_HAL_IOM_INT_THR | \
AM_HAL_IOM_INT_CMDCMP)
#define AM_HAL_IOM_INT_SWERR ( \
AM_HAL_IOM_INT_ICMD | \
AM_HAL_IOM_INT_FOVFL | \
AM_HAL_IOM_INT_FUNDFL | \
AM_HAL_IOM_INT_IACC)
#define AM_HAL_IOM_INT_I2CARBERR ( \
AM_HAL_IOM_INT_ARB | \
AM_HAL_IOM_INT_START | \
AM_HAL_IOM_INT_STOP)
//! @}
//*****************************************************************************
@ -204,6 +218,31 @@
#define AM_HAL_IOM_I2CBB_MODULE AM_REG_IOMSTR_NUM_MODULES
//! @}
//*****************************************************************************
//
//! @name IOM Return Codes
//! @brief Enum definitions for defining return values for IOM APIs
//!
//! This enum defines possible values for non-void IOM APIs
//!
//! @{
//
//*****************************************************************************
typedef enum
{
AM_HAL_IOM_SUCCESS = 0,
AM_HAL_IOM_ERR_TIMEOUT,
AM_HAL_IOM_ERR_INVALID_MODULE,
AM_HAL_IOM_ERR_INVALID_PARAM,
AM_HAL_IOM_ERR_INVALID_CFG,
AM_HAL_IOM_ERR_INVALID_OPER,
AM_HAL_IOM_ERR_I2C_NAK,
AM_HAL_IOM_ERR_I2C_ARB,
AM_HAL_IOM_ERR_RESOURCE_ERR,
} am_hal_iom_status_e ;
//! @}
//*****************************************************************************
//
//! @brief Union type for a word-aligned, byte-addressable array.
@ -271,7 +310,7 @@ typedef struct
//! Select the SPI clock polarity (unused in I2C mode).
//
bool bSPOL;
//
//! @brief Select the FIFO write threshold.
//!
@ -404,7 +443,11 @@ am_hal_iom_pwrsave_t;
//
//*****************************************************************************
extern am_hal_iom_pwrsave_t am_hal_iom_pwrsave[AM_REG_IOMSTR_NUM_MODULES];
extern uint32_t g_iom_error_status;
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
@ -420,23 +463,30 @@ extern void am_hal_iom_config(uint32_t ui32Module,
extern uint32_t am_hal_iom_frequency_get(uint32_t ui32Module);
extern void am_hal_iom_enable(uint32_t ui32Module);
extern void am_hal_iom_disable(uint32_t ui32Module);
extern void am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
extern am_hal_iom_status_e am_hal_iom_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options);
extern void am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
extern am_hal_iom_status_e am_hal_iom_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options);
extern uint32_t am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
extern am_hal_iom_status_e am_hal_iom_spi_fullduplex(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32TxData, uint32_t *pui32RxData,
uint32_t ui32NumBytes, uint32_t ui32Options);
extern am_hal_iom_status_e am_hal_iom_spi_write_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options);
extern uint32_t am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
extern am_hal_iom_status_e am_hal_iom_spi_read_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options);
extern void am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
extern am_hal_iom_status_e am_hal_iom_spi_fullduplex_nq(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32TxData, uint32_t *pui32RxData,
uint32_t ui32NumBytes, uint32_t ui32Options);
extern am_hal_iom_status_e am_hal_iom_spi_write_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options,
am_hal_iom_callback_t pfnCallback);
extern uint32_t am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
extern am_hal_iom_status_e am_hal_iom_spi_read_nb(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options,
am_hal_iom_callback_t pfnCallback);
@ -445,39 +495,39 @@ extern void am_hal_iom_spi_cmd_run(uint32_t ui32Operation,
uint32_t ui32ChipSelect,
uint32_t ui32NumBytes,
uint32_t ui32Options);
extern void am_hal_iom_i2c_write(uint32_t ui32Module,
extern am_hal_iom_status_e am_hal_iom_i2c_write(uint32_t ui32Module,
uint32_t ui32BusAddress,
uint32_t *pui32Data,
uint32_t ui32NumBytes,
uint32_t ui32Options);
extern void am_hal_iom_i2c_read(uint32_t ui32Module,
extern am_hal_iom_status_e am_hal_iom_i2c_read(uint32_t ui32Module,
uint32_t ui32BusAddress,
uint32_t *pui32Data,
uint32_t ui32NumBytes,
uint32_t ui32Options);
extern uint32_t am_hal_iom_i2c_write_nq(uint32_t ui32Module,
extern am_hal_iom_status_e am_hal_iom_i2c_write_nq(uint32_t ui32Module,
uint32_t ui32BusAddress,
uint32_t *pui32Data,
uint32_t ui32NumBytes,
uint32_t ui32Options);
extern uint32_t am_hal_iom_i2c_read_nq(uint32_t ui32Module,
extern am_hal_iom_status_e am_hal_iom_i2c_read_nq(uint32_t ui32Module,
uint32_t ui32BusAddress,
uint32_t *pui32Data,
uint32_t ui32NumBytes,
uint32_t ui32Options);
extern void am_hal_iom_i2c_write_nb(uint32_t ui32Module,
extern am_hal_iom_status_e am_hal_iom_i2c_write_nb(uint32_t ui32Module,
uint32_t ui32BusAddress,
uint32_t *pui32Data,
uint32_t ui32NumBytes,
uint32_t ui32Options,
am_hal_iom_callback_t pfnCallback);
extern void am_hal_iom_i2c_read_nb(uint32_t ui32Module,
extern am_hal_iom_status_e am_hal_iom_i2c_read_nb(uint32_t ui32Module,
uint32_t ui32BusAddress,
uint32_t *pui32Data,
uint32_t ui32NumBytes,
uint32_t ui32Options,
am_hal_iom_callback_t pfnCallback);
extern void am_hal_iom_i2c_cmd_run(uint32_t ui32Operation,
extern am_hal_iom_status_e am_hal_iom_i2c_cmd_run(uint32_t ui32Operation,
uint32_t ui32Module,
uint32_t ui32BusAddress,
uint32_t ui32NumBytes,
@ -485,7 +535,7 @@ extern void am_hal_iom_i2c_cmd_run(uint32_t ui32Operation,
extern void am_hal_iom_command_repeat_set(uint32_t ui32Module,
uint32_t ui32CmdCount);
extern uint32_t am_hal_iom_status_get(uint32_t ui32Module);
extern uint32_t am_hal_iom_error_status_get(uint32_t ui32Module);
extern am_hal_iom_status_e am_hal_iom_error_status_get(uint32_t ui32Module);
extern uint32_t am_hal_iom_fifo_write(uint32_t ui32Module, uint32_t *pui32Data,
uint32_t ui32NumBytes);
extern uint32_t am_hal_iom_fifo_read(uint32_t ui32Module, uint32_t *pui32Data,
@ -505,19 +555,19 @@ extern void am_hal_iom_queue_init(uint32_t ui32ModuleNum,
uint32_t ui32QueueMemSize);
extern uint32_t am_hal_iom_queue_length_get(uint32_t ui32Module);
extern void am_hal_iom_sleeping_queue_flush(uint32_t ui32Module);
extern void am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
extern am_hal_iom_status_e am_hal_iom_queue_spi_write(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options,
am_hal_iom_callback_t pfnCallback);
extern void am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
extern am_hal_iom_status_e am_hal_iom_queue_spi_read(uint32_t ui32Module, uint32_t ui32ChipSelect,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options,
am_hal_iom_callback_t pfnCallback);
extern void am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress,
extern am_hal_iom_status_e am_hal_iom_queue_i2c_write(uint32_t ui32Module, uint32_t ui32BusAddress,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options,
am_hal_iom_callback_t pfnCallback);
extern void am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress,
extern am_hal_iom_status_e am_hal_iom_queue_i2c_read(uint32_t ui32Module, uint32_t ui32BusAddress,
uint32_t *pui32Data, uint32_t ui32NumBytes,
uint32_t ui32Options,
am_hal_iom_callback_t pfnCallback);
@ -533,7 +583,6 @@ extern void am_hal_iom_queue_service(uint32_t ui32Module, uint32_t ui32Statu
void am_iomaster##x##_isr(void) \
{ \
uint32_t ui32IntStatus; \
g_iom_error_status = am_hal_iom_error_status_get(x); \
ui32IntStatus = am_hal_iom_int_status_get(x, false); \
am_hal_iom_int_clear(x, ui32IntStatus); \
am_hal_iom_queue_service(x, ui32IntStatus); \
@ -543,12 +592,15 @@ void am_iomaster##x##_isr(void) \
void am_iomaster##x##_isr(void) \
{ \
uint32_t ui32IntStatus; \
g_iom_error_status = am_hal_iom_error_status_get(x); \
ui32IntStatus = am_hal_iom_int_status_get(x, false); \
am_hal_iom_int_clear(x, ui32IntStatus); \
am_hal_iom_int_service(x, ui32IntStatus); \
}
#ifdef __cplusplus
}
#endif
#endif // AM_HAL_IOM_H
//*****************************************************************************

56
bsp/apollo2/libraries/drivers/hal/am_hal_ios.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -61,6 +61,7 @@ typedef struct
volatile uint32_t ui32WriteIndex;
volatile uint32_t ui32ReadIndex;
volatile uint32_t ui32Length;
uint32_t ui32FifoInc;
uint32_t ui32Capacity;
}
am_hal_ios_buffer_t;
@ -103,6 +104,23 @@ uint8_t *g_pui8FIFOPtr = (uint8_t *) REG_IOSLAVE_BASEADDR;
uint8_t g_ui32HwFifoSize = 0;
uint32_t g_ui32FifoBaseOffset = 0;
//*****************************************************************************
//
// Checks to see if this processor is a Rev B2 device.
//
// This is needed to disable SHELBY-1654 workaround.
//
//*****************************************************************************
bool
isRevB2(void)
{
//
// Check to make sure the major rev is B and the minor rev is 2.
//
return ( (AM_REG(MCUCTRL, CHIPREV) & 0xFF) == \
(AM_REG_MCUCTRL_CHIPREV_REVMAJ_B | (AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 + 2)) );
}
//*****************************************************************************
//
//! @brief Enable the IOS in the power control block.
@ -957,7 +975,10 @@ am_hal_ios_fifo_service(uint32_t ui32Status)
}
}
}
resync_fifoSize();
if (!isRevB2())
{
resync_fifoSize();
}
//
// Need to retake the FIFO space, after Threshold interrupt has been reenabled
@ -1041,7 +1062,10 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes)
ui32NumBytes -= ui32FIFOSpace;
pui8Data += ui32FIFOSpace;
};
resync_fifoSize();
if (!isRevB2())
{
resync_fifoSize();
}
}
//
@ -1102,6 +1126,8 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes)
}
}
// Number of bytes written
g_sSRAMBuffer.ui32FifoInc += totalBytes - ui32NumBytes;
return (totalBytes - ui32NumBytes);
}
@ -1114,7 +1140,7 @@ am_hal_ios_fifo_write(uint8_t *pui8Data, uint32_t ui32NumBytes)
//!
//! This function will write data from the caller-provided array to the IOS
//! LRAM FIFO. This simple routine does not use SRAM buffering for large
//! messages.
//! messages. This function also updates the FIFOCTR.
//!
//! The maximum message size for the IO Slave is 128 bytes.
//!
@ -1140,6 +1166,8 @@ am_hal_ios_fifo_write_simple(uint8_t *pui8Data, uint32_t ui32NumBytes)
if ( ui32NumBytes <= ui32FIFOSpace )
{
fifo_write(pui8Data, ui32NumBytes);
// Write FIFOINC
AM_BFW(IOSLAVE, FIFOINC, FIFOINC, ui32NumBytes);
}
else
{
@ -1209,6 +1237,7 @@ am_hal_ios_buffer_init(am_hal_ios_buffer_t *psBuffer, void *pvArray,
psBuffer->ui32ReadIndex = 0;
psBuffer->ui32Length = 0;
psBuffer->ui32Capacity = ui32Bytes;
psBuffer->ui32FifoInc = 0;
psBuffer->pui8Data = (uint8_t *)pvArray;
}
@ -1273,12 +1302,19 @@ am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes)
//! @brief Update the FIFOCTR to inform host of available data to read.
//!
//! This function allows the application to indicate to HAL when it is safe to
//! update the FIFOCTR.
//! update the FIFOCTR. This function needs to be used in conjunction with
//! am_hal_ios_fifo_write(), which itself does not update the FIFOCTR
//!
//! CAUTION:
//! Application needs to implement some sort of
//! synchronization with the host to make sure host is not reading FIFOCTR while
//! it is being updated by the MCU, since the FIFOCTR read over
//! IO is not an atomic operation.
//! IO is not an atomic operation. Otherwise, some other logic could be implemented
//! by the host to detect and disregard transient values of FIFOCTR (e.g. multiple
//! reads till it gets a stable value).
//! For Pre-B2 parts, it is necessary to have this synchronization guarantee that
//! Host is not doing any READ operation - be it for FIFOCTR or FIFO itself when
//! this call is made, as otherwise the FIFOCTR value may get corrupted.
//!
//!
//! @return None.
@ -1287,11 +1323,9 @@ am_hal_ios_fifo_buffer_init(uint8_t *pui8Buffer, uint32_t ui32NumBytes)
void
am_hal_ios_update_fifoctr(void)
{
uint32_t ui32Val;
// Determine the available data
ui32Val = am_hal_ios_fifo_space_used();
// Update FIFOCTR
AM_BFW(IOSLAVE, FIFOCTR, FIFOCTR, ui32Val);
// Write FIFOINC
AM_BFW(IOSLAVE, FIFOINC, FIFOINC, g_sSRAMBuffer.ui32FifoInc);
g_sSRAMBuffer.ui32FifoInc = 0;
return;
}

10
bsp/apollo2/libraries/drivers/hal/am_hal_ios.h
View File

@ -42,16 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_IOS_H
#define AM_HAL_IOS_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
@ -300,6 +296,10 @@ typedef struct
}
am_hal_ios_config_t;
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

31
bsp/apollo2/libraries/drivers/hal/am_hal_itm.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -56,30 +56,6 @@
//
//*****************************************************************************
//*****************************************************************************
//
//! @brief Delays for a desired amount of microseconds.
//!
//! @note - This function is based on the similar function in am_util_delay.c,
//! please see that module for implementation details. It was necessary to
//! duplicate it here to avoid having to update every example to include the
//! am_util_delay.c module in its build.
//!
//! @returns None
//
//*****************************************************************************
void
am_hal_itm_delay_us(uint32_t ui32MicroSeconds)
{
uint32_t ui32Iterations = ui32MicroSeconds *
(am_hal_clkgen_sysclk_get() / 3000000);
//
// Call the BOOTROM cycle delay function
//
am_hal_flash_delay(ui32Iterations);
}
//*****************************************************************************
//
//! @brief Enables the ITM
@ -118,7 +94,7 @@ am_hal_itm_enable(void)
AM_REGVAL(AM_REG_ITM_TER_O) = 0xffffffff;
//
// Write to the ITM control and status register (don't enable yet).
// Write to the ITM control and status register.
//
AM_REGVAL(AM_REG_ITM_TCR_O) =
AM_WRITE_SM(AM_REG_ITM_TCR_ATB_ID, 0x15) |
@ -129,6 +105,7 @@ am_hal_itm_enable(void)
AM_WRITE_SM(AM_REG_ITM_TCR_SYNC_ENABLE, 0) |
AM_WRITE_SM(AM_REG_ITM_TCR_TS_ENABLE, 0) |
AM_WRITE_SM(AM_REG_ITM_TCR_ITM_ENABLE, 1);
}
//*****************************************************************************
@ -203,7 +180,7 @@ am_hal_itm_not_busy(void)
//
// wait for 50us for the data to flush out
//
am_hal_itm_delay_us(50);
am_hal_flash_delay(FLASH_CYCLES_US(50));
}
//*****************************************************************************

13
bsp/apollo2/libraries/drivers/hal/am_hal_itm.h
View File

@ -42,18 +42,13 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_ITM_H
#define AM_HAL_ITM_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Sync Packet Defines
@ -71,12 +66,16 @@ extern "C"
#define AM_HAL_ITM_PRINT_NUM_REGS 1
extern uint32_t am_hal_itm_print_registers[AM_HAL_ITM_PRINT_NUM_REGS];
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions
//
//*****************************************************************************
extern void am_hal_itm_delay_us(uint32_t ui32MicroSeconds);
extern void am_hal_itm_enable(void);
extern void am_hal_itm_disable(void);
extern void am_hal_itm_not_busy(void);

2
bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_mcuctrl.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_MCUCTRL_H
#define AM_HAL_MCUCTRL_H
#ifdef __cplusplus
extern "C"
{
#endif
//
// Deprecate the am_hal_mcuctrl_bucks_enable() and disable() functions.
// This functionality is now handled in pwrctrl.
@ -188,6 +183,11 @@ typedef struct
}
am_hal_mcuctrl_fault_t;
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

2
bsp/apollo2/libraries/drivers/hal/am_hal_otp.c
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include "am_mcu_apollo.h"

12
bsp/apollo2/libraries/drivers/hal/am_hal_otp.h
View File

@ -38,17 +38,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_OTP_H
#define AM_HAL_OTP_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Define some OTP values and macros.
@ -82,6 +77,11 @@ extern "C"
#define AM_OTP_SRAM_LOCKOUT_S (2)
#define AM_OTP_SRAM_LOCKOUT_M (0x1 << AM_OTP_SRAM_LOCKOUT_S)
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Function prototypes

2
bsp/apollo2/libraries/drivers/hal/am_hal_pdm.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

11
bsp/apollo2/libraries/drivers/hal/am_hal_pdm.h
View File

@ -42,13 +42,18 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_PDM_H
#define AM_HAL_PDM_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Macro definitions
@ -655,6 +660,10 @@ extern void am_hal_pdm_disable(void);
extern uint32_t am_hal_pdm_int_status_get(bool bEnabledOnly);
#ifdef __cplusplus
}
#endif
#endif // AM_HAL_PDM_H
//*****************************************************************************

69
bsp/apollo2/libraries/drivers/hal/am_hal_pin.h
View File

@ -41,7 +41,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -55,7 +55,7 @@
//*****************************************************************************
#define AM_HAL_PIN_DIR_INPUT (AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_DIR_OUTPUT (AM_HAL_GPIO_OUT_PUSHPULL)
#define AM_HAL_PIN_DIR_OPENDRAIN (AM_HAL_GPIO_OUT_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_DIR_OPENDRAIN (AM_HAL_GPIO_OUT_OPENDRAIN)
#define AM_HAL_PIN_DIR_3STATE (AM_HAL_GPIO_OUT_3STATE)
//*****************************************************************************
@ -81,25 +81,25 @@
#define AM_HAL_PIN_0_MxSCKLB (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_0_M2SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_0_MxSCLLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_0_M2SCL (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_0_M2SCL (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_1_SLSDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_1_SLSDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_1_SLMISO (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_1_UART0TX (AM_HAL_GPIO_FUNC(2))
#define AM_HAL_PIN_1_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_1_MxMISOLB (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_1_M2MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_1_MxSDALB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_1_M2SDA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_1_M2SDA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_2_SLWIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE)
#define AM_HAL_PIN_2_SLWIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_2_SLMOSI (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_2_UART0RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_2_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_2_MxMOSILB (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_2_M2MOSI (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_2_MxWIR3LB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_2_M2WIR3 (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_3STATE)
#define AM_HAL_PIN_2_M2WIR3 (AM_HAL_GPIO_FUNC(7) | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_3_UART0RTS (AM_HAL_GPIO_FUNC(0))
#define AM_HAL_PIN_3_SLnCE (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
@ -109,7 +109,6 @@
#define AM_HAL_PIN_3_M2nCE0 (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_3_TRIG1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_3_I2S_WCLK (AM_HAL_GPIO_FUNC(7))
#define AM_HAL_PIN_3_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER)
#define AM_HAL_PIN_4_UART0CTS (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_4_SLINT (AM_HAL_GPIO_FUNC(1))
@ -119,17 +118,18 @@
#define AM_HAL_PIN_4_M2nCE5 (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_4_CLKOUT (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_4_32KHZ_XT (AM_HAL_GPIO_FUNC(7))
// PSINK usage: GPIOWT=0 to activate the power switch, GPIOWT=1 to disable
#define AM_HAL_PIN_4_PSINK (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_POWER)
#define AM_HAL_PIN_5_M0SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_5_M0SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_5_M0SCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_5_UART0RTS (AM_HAL_GPIO_FUNC(2))
#define AM_HAL_PIN_5_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_5_M0SCKLB (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_5_EXTHFA (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_5_M0SCLLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_5_M1nCE2 (AM_HAL_GPIO_FUNC(7))
#define AM_HAL_PIN_6_M0SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_6_M0SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_6_M0MISO (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_6_UART0CTS (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_6_GPIO (AM_HAL_GPIO_FUNC(3))
@ -138,7 +138,7 @@
#define AM_HAL_PIN_6_SLSDALB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_6_I2S_DAT (AM_HAL_GPIO_FUNC(7))
#define AM_HAL_PIN_7_M0WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE)
#define AM_HAL_PIN_7_M0WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_7_M0MOSI (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_7_CLKOUT (AM_HAL_GPIO_FUNC(2))
#define AM_HAL_PIN_7_GPIO (AM_HAL_GPIO_FUNC(3))
@ -147,7 +147,7 @@
#define AM_HAL_PIN_7_SLWIR3LB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_7_M1nCE1 (AM_HAL_GPIO_FUNC(7))
#define AM_HAL_PIN_8_M1SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_8_M1SCL (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_8_M1SCK (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_8_M0nCE4 (AM_HAL_GPIO_FUNC(2))
#define AM_HAL_PIN_8_GPIO (AM_HAL_GPIO_FUNC(3))
@ -156,7 +156,7 @@
#define AM_HAL_PIN_8_UART1TX (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_8_M1SCLLB (AM_HAL_GPIO_FUNC(7))
#define AM_HAL_PIN_9_M1SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_9_M1SDA (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_9_M1MISO (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_9_M0nCE5 (AM_HAL_GPIO_FUNC(2))
#define AM_HAL_PIN_9_GPIO (AM_HAL_GPIO_FUNC(3))
@ -165,7 +165,7 @@
#define AM_HAL_PIN_9_UART1RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_9_SLSDALB (AM_HAL_GPIO_FUNC(7))
#define AM_HAL_PIN_10_M1WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_3STATE)
#define AM_HAL_PIN_10_M1WIR3 (AM_HAL_GPIO_FUNC(0) | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_10_M1MOSI (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_10_M0nCE6 (AM_HAL_GPIO_FUNC(2))
#define AM_HAL_PIN_10_GPIO (AM_HAL_GPIO_FUNC(3))
@ -182,7 +182,6 @@
#define AM_HAL_PIN_11_UART1CTS (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_11_UART0RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_11_PDM_DATA (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_11_PSINK (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_12_ADCD0NSE9 (AM_HAL_GPIO_FUNC(0))
#define AM_HAL_PIN_12_M1nCE0 (AM_HAL_GPIO_FUNC(1))
@ -198,7 +197,6 @@
#define AM_HAL_PIN_13_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_13_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_13_M2nCE3 (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_13_EXTHFB (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_13_UART0RTS (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_13_UART1RX (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
@ -207,7 +205,6 @@
#define AM_HAL_PIN_14_UART1TX (AM_HAL_GPIO_FUNC(2))
#define AM_HAL_PIN_14_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_14_M2nCE1 (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_14_EXTHFS (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_14_SWDCK (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_14_32KHZ_XT (AM_HAL_GPIO_FUNC(7))
@ -216,7 +213,6 @@
#define AM_HAL_PIN_15_UART1RX (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_15_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_15_M2nCE2 (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_15_EXTXT (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_15_SWDIO (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_15_SWO (AM_HAL_GPIO_FUNC(7))
@ -234,7 +230,6 @@
#define AM_HAL_PIN_17_TRIG1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_17_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_17_M4nCE3 (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_17_EXTLF (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_17_UART0RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_17_UART1CTS (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
@ -243,7 +238,6 @@
#define AM_HAL_PIN_18_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_18_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_18_M4nCE1 (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_18_ANATEST2 (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_18_UART1TX (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_18_32KHZ_XT (AM_HAL_GPIO_FUNC(7))
@ -252,7 +246,6 @@
#define AM_HAL_PIN_19_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_19_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_19_TCTA1 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_19_ANATEST1 (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_19_UART1RX (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_19_I2S_BCLK (AM_HAL_GPIO_FUNC(7))
@ -277,6 +270,7 @@
#define AM_HAL_PIN_22_PDM_CLK (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_22_TCTB1 (AM_HAL_GPIO_FUNC(6) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_22_SWO (AM_HAL_GPIO_FUNC(7))
// PSOURCE usage in pushpull: GPIOWT=1 to activate the power switch, GPIOWT=0 to disable
#define AM_HAL_PIN_22_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER)
#define AM_HAL_PIN_23_UART0RX (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
@ -299,17 +293,15 @@
#endif // defined (AM_PACKAGE_BGA)
#if defined (AM_PACKAGE_BGA)
#define AM_HAL_PIN_25_EXTXT (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_25_M0nCE2 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_25_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_25_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_25_M2SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_25_M2SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_25_M2MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_25_SLMISOLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_25_SLSDALB (AM_HAL_GPIO_FUNC(7))
#endif // defined (AM_PACKAGE_BGA)
#define AM_HAL_PIN_26_EXTLF (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_26_M0nCE3 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_26_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_26_GPIO (AM_HAL_GPIO_FUNC(3))
@ -319,11 +311,10 @@
#define AM_HAL_PIN_26_M3nCE0 (AM_HAL_GPIO_FUNC(7))
#if defined (AM_PACKAGE_BGA)
#define AM_HAL_PIN_27_EXTHF (AM_HAL_GPIO_FUNC(0) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_27_M1nCE4 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_27_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_27_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_27_M2SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_27_M2SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_27_M2SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_27_M2SCKLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_27_M2SCLLB (AM_HAL_GPIO_FUNC(7))
@ -333,7 +324,7 @@
#define AM_HAL_PIN_28_M1nCE5 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_28_TCTB1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_28_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_28_M2WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE)
#define AM_HAL_PIN_28_M2WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_28_M2MOSI (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_28_M5nCE3 (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_28_SLWIR3LB (AM_HAL_GPIO_FUNC(7))
@ -353,7 +344,6 @@
#define AM_HAL_PIN_30_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_30_UART0TX (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_30_UART1RTS (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_30_SWO (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_30_I2S_DAT (AM_HAL_GPIO_FUNC(7))
#endif // defined (AM_PACKAGE_BGA)
@ -433,7 +423,7 @@
#define AM_HAL_PIN_38_M1nCE3 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_38_UART0CTS (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_38_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_38_M3WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE)
#define AM_HAL_PIN_38_M3WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_38_M3MOSI (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_38_M4nCE7 (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_38_SLWIR3LB (AM_HAL_GPIO_FUNC(7))
@ -443,7 +433,7 @@
#define AM_HAL_PIN_39_UART1TX (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_39_CLKOUT (AM_HAL_GPIO_FUNC(2))
#define AM_HAL_PIN_39_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_39_M4SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_39_M4SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_39_M4SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_39_M4SCKLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_39_M4SCLLB (AM_HAL_GPIO_FUNC(7))
@ -452,7 +442,7 @@
#define AM_HAL_PIN_40_UART1RX (AM_HAL_GPIO_FUNC(1) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_40_TRIG0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_40_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_40_M4SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_40_M4SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_40_M4MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_40_SLMISOLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_40_SLSDALB (AM_HAL_GPIO_FUNC(7))
@ -465,6 +455,7 @@
#define AM_HAL_PIN_41_M5nCE7 (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_41_M4nCE2 (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_41_UART0RTS (AM_HAL_GPIO_FUNC(7))
// PSOURCE usage in pushpull: GPIOWT=1 to activate the power switch, GPIOWT=0 to disable
#define AM_HAL_PIN_41_PSOURCE (AM_HAL_GPIO_FUNC(3) | AM_HAL_PIN_DIR_OUTPUT | AM_HAL_GPIO_POWER)
#if defined (AM_PACKAGE_BGA)
@ -472,7 +463,7 @@
#define AM_HAL_PIN_42_M0nCE0 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_42_TCTA0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_42_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_42_M3SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_42_M3SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_42_M3SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_42_M3SCKLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_42_M3SCLLB (AM_HAL_GPIO_FUNC(7))
@ -483,7 +474,7 @@
#define AM_HAL_PIN_43_M0nCE1 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_43_TCTB0 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_43_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_43_M3SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_43_M3SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_43_M3MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_43_SLMISOLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_43_SLSDALB (AM_HAL_GPIO_FUNC(7))
@ -493,7 +484,7 @@
#define AM_HAL_PIN_44_M0nCE2 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_44_TCTA1 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_44_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_44_M4WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE)
#define AM_HAL_PIN_44_M4WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_44_M4MOSI (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_44_M5nCE6 (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_44_SLWIR3LB (AM_HAL_GPIO_FUNC(7))
@ -506,7 +497,7 @@
#define AM_HAL_PIN_45_M4nCE3 (AM_HAL_GPIO_FUNC(4))
#define AM_HAL_PIN_45_M3nCE6 (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_45_M5nCE5 (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_45_TCTA1 (AM_HAL_GPIO_FUNC(7) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_45_SWO (AM_HAL_GPIO_FUNC(7))
#endif // defined (AM_PACKAGE_BGA)
#if defined (AM_PACKAGE_BGA)
@ -524,7 +515,7 @@
#define AM_HAL_PIN_47_M0nCE5 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_47_TCTB2 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_47_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_47_M5WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_3STATE)
#define AM_HAL_PIN_47_M5WIR3 (AM_HAL_GPIO_FUNC(4) | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_47_M5MOSI (AM_HAL_GPIO_FUNC(5))
#define AM_HAL_PIN_47_M4nCE5 (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_47_SLWIR3LB (AM_HAL_GPIO_FUNC(7))
@ -533,7 +524,7 @@
#define AM_HAL_PIN_48_M0nCE6 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_48_TCTA3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_48_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_48_M5SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_48_M5SCL (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_48_M5SCK (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_48_M5SCKLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_48_M5SCLLB (AM_HAL_GPIO_FUNC(7))
@ -542,7 +533,7 @@
#define AM_HAL_PIN_49_M0nCE7 (AM_HAL_GPIO_FUNC(1))
#define AM_HAL_PIN_49_TCTB3 (AM_HAL_GPIO_FUNC(2) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_49_GPIO (AM_HAL_GPIO_FUNC(3))
#define AM_HAL_PIN_49_M5SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN)
#define AM_HAL_PIN_49_M5SDA (AM_HAL_GPIO_FUNC(4) | AM_HAL_PIN_DIR_OPENDRAIN | AM_HAL_GPIO_INPEN)
#define AM_HAL_PIN_49_M5MISO (AM_HAL_GPIO_FUNC(5) | AM_HAL_PIN_DIR_INPUT)
#define AM_HAL_PIN_49_SLMISOLB (AM_HAL_GPIO_FUNC(6))
#define AM_HAL_PIN_49_SLSDALB (AM_HAL_GPIO_FUNC(7))

2
bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

11
bsp/apollo2/libraries/drivers/hal/am_hal_pwrctrl.h
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -319,6 +319,11 @@
#define AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_ALL \
AM_HAL_PWRCTRL_PWRONSTATUS_SRAM_256K
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Function prototypes
@ -332,6 +337,10 @@ extern void am_hal_pwrctrl_bucks_enable(void);
extern void am_hal_pwrctrl_bucks_disable(void);
extern void am_hal_pwrctrl_low_power_init(void);
#ifdef __cplusplus
}
#endif
#endif // AM_HAL_PWRCTRL_H
//*****************************************************************************

2
bsp/apollo2/libraries/drivers/hal/am_hal_queue.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

2
bsp/apollo2/libraries/drivers/hal/am_hal_queue.h
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_QUEUE_H

2
bsp/apollo2/libraries/drivers/hal/am_hal_reset.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

2
bsp/apollo2/libraries/drivers/hal/am_hal_reset.h
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_RSTGEN_H

2
bsp/apollo2/libraries/drivers/hal/am_hal_rtc.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_rtc.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_RTC_H
#define AM_HAL_RTC_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! @name OSC Start and Stop
@ -149,6 +144,11 @@ typedef struct am_hal_rtc_time_struct
uint32_t ui32Hundredths;
}am_hal_rtc_time_t;
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

27
bsp/apollo2/libraries/drivers/hal/am_hal_stimer.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -136,11 +136,14 @@ am_hal_stimer_counter_clear(void)
//!
//! @param ui32CmprInstance is the compare register instance number (0-7).
//! @param ui32Delta is the value to add to the STimer counter and load into
//! the comparator register.
//! the comparator register. It should be > 1
//!
//! NOTE: There is no way to set an absolute value into a comparator register.
//! Only deltas added to the STimer counter can be written to the compare
//! registers.
//! CAUTION: The HAL implementation requires temporarily disabling the
//! comparison. To avoid the remote possibility of losing an interrupt
//! during that time, delta should always be set to a value greater than 1
//!
//! @return None.
//
@ -148,12 +151,32 @@ am_hal_stimer_counter_clear(void)
void
am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, uint32_t ui32Delta)
{
uint32_t cfgVal;
uint32_t ui32Critical = 0;
if ( ui32CmprInstance > 7 )
{
return;
}
cfgVal = AM_REG(CTIMER, STCFG);
// We need to disable the compare temporarily while setting the delta value
// That leaves a corner case where we could miss the trigger if setting a very
// small delta. To avoid this, we take critical section, and we should ensure
// that delta value is at least > 1
// Disable the compare if already enabled, when setting the new value
AM_REG(CTIMER, STCFG) &= ~((AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance));
//
// Start a critical section.
//
ui32Critical = am_hal_interrupt_master_disable();
AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta;
// Restore Compare Enable bit
AM_REG(CTIMER, STCFG) |= cfgVal & (AM_HAL_STIMER_CFG_COMPARE_A_ENABLE << ui32CmprInstance);
//
// End the critical section.
//
am_hal_interrupt_master_set(ui32Critical);
}
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_stimer.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_STIMER_H
#define AM_HAL_STIMER_H
#ifdef __cplusplus
extern "C"
{
#endif
//
// Compute address of a given COMPARE or CAPTURE register.
// Note - For Apollo2, the parameter n should be 0 (as only 1 stimer module
@ -204,6 +199,11 @@ am_hal_stimer_config_t;
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

6
bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -731,8 +731,6 @@ am_hal_sysctrl_buck_update_complete(void)
static void
am_hal_sysctrl_buckA_ctimer_isr(void)
{
volatile uint32_t ui32BuckTimer = g_ui32BuckTimer - 1;
//
// Begin critical section.
// Although a relatively long time, the following 2us delay is critically
@ -792,8 +790,6 @@ am_hal_sysctrl_buckA_ctimer_isr(void)
static void
am_hal_sysctrl_buckB_ctimer_isr(void)
{
volatile uint32_t ui32BuckTimer = g_ui32BuckTimer - 1;
//
// Begin critical section.
// Although a relatively long time, the following 2us delay is critically

10
bsp/apollo2/libraries/drivers/hal/am_hal_sysctrl.h
View File

@ -42,16 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_SYSCTRL_H
#define AM_HAL_SYSCTRL_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
@ -86,6 +82,10 @@ extern "C"
//
#define AM_HAL_SYSCTRL_BUCK_CTIMER_ZX_CONSTANT 0x01000000 // No timer, apply a constant value
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

2
bsp/apollo2/libraries/drivers/hal/am_hal_systick.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

2
bsp/apollo2/libraries/drivers/hal/am_hal_systick.h
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_SYSTICK_H

4
bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.c
View File

@ -44,7 +44,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -350,7 +350,7 @@ am_hal_tpiu_enable(am_hal_tpiu_config_t *psConfig)
//
// Wait for 50us for the data to flush out.
//
am_hal_itm_delay_us(50);
am_hal_flash_delay(FLASH_CYCLES_US(50));
}
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_tpiu.h
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_TPIU_H
@ -50,11 +50,6 @@
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// TPIU bit rate defines.
@ -165,6 +160,11 @@ typedef struct
}
am_hal_tpiu_config_t;
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

2
bsp/apollo2/libraries/drivers/hal/am_hal_ttp.c
View File

@ -39,7 +39,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#include "am_mcu_apollo.h"

2
bsp/apollo2/libraries/drivers/hal/am_hal_ttp.h
View File

@ -39,7 +39,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_TTP_H

2
bsp/apollo2/libraries/drivers/hal/am_hal_uart.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_uart.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_UART_H
#define AM_HAL_UART_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! @name UART Interrupts
@ -270,6 +265,11 @@ am_hal_uart_pwrsave_t;
//*****************************************************************************
extern am_hal_uart_pwrsave_t am_hal_uart_pwrsave[AM_REG_UART_NUM_MODULES];
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

2
bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

12
bsp/apollo2/libraries/drivers/hal/am_hal_vcomp.h
View File

@ -42,17 +42,12 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_VCOMP_H
#define AM_HAL_VCOMP_H
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! @name Positive Input Selection
@ -145,6 +140,11 @@ typedef struct
}
am_hal_vcomp_config_t;
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// External function definitions

2
bsp/apollo2/libraries/drivers/hal/am_hal_wdt.c
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

2
bsp/apollo2/libraries/drivers/hal/am_hal_wdt.h
View File

@ -42,7 +42,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_HAL_WDT_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_adc.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_ADC_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_base_addresses.h
View File

@ -37,7 +37,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_BASE_ADDRESSES_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_cachectrl.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_CACHECTRL_H

13
bsp/apollo2/libraries/drivers/regs/am_reg_clkgen.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_CLKGEN_H
@ -66,7 +66,6 @@
#define AM_REG_CLKGEN_CCTRL_O 0x00000018
#define AM_REG_CLKGEN_STATUS_O 0x0000001C
#define AM_REG_CLKGEN_HFADJ_O 0x00000020
#define AM_REG_CLKGEN_HFVAL_O 0x00000024
#define AM_REG_CLKGEN_CLOCKEN_O 0x00000028
#define AM_REG_CLKGEN_CLOCKEN2_O 0x0000002C
#define AM_REG_CLKGEN_CLOCKEN3_O 0x00000030
@ -390,16 +389,6 @@
#define AM_REG_CLKGEN_HFADJ_HFADJEN_DIS 0x00000000
#define AM_REG_CLKGEN_HFADJ_HFADJEN_EN 0x00000001
//*****************************************************************************
//
// CLKGEN_HFVAL - HFADJ readback
//
//*****************************************************************************
// Current HFTUNE value
#define AM_REG_CLKGEN_HFVAL_HFTUNERB_S 0
#define AM_REG_CLKGEN_HFVAL_HFTUNERB_M 0x000007FF
#define AM_REG_CLKGEN_HFVAL_HFTUNERB(n) (((uint32_t)(n) << 0) & 0x000007FF)
//*****************************************************************************
//
// CLKGEN_CLOCKEN - Clock Enable Status

4
bsp/apollo2/libraries/drivers/regs/am_reg_ctimer.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_CTIMER_H
@ -51,7 +51,7 @@
//*****************************************************************************
#define AM_REG_CTIMER_NUM_MODULES 1
#define AM_REG_CTIMERn(n) \
(REG_CTIMER_BASEADDR + 0x00000000 * n)
(REG_CTIMER_BASEADDR + 0x00000010 * n)
//*****************************************************************************
//

2
bsp/apollo2/libraries/drivers/regs/am_reg_flashctrl.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_FLASHCTRL_H

24
bsp/apollo2/libraries/drivers/regs/am_reg_gpio.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_GPIO_H
@ -1348,7 +1348,7 @@
#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_SLWIR3LB 0x30000000
#define AM_REG_GPIO_PADREGB_PAD7FNCSEL_M1nCE1 0x38000000
// Pad 7 drive strentgh
// Pad 7 drive strength
#define AM_REG_GPIO_PADREGB_PAD7STRNG_S 26
#define AM_REG_GPIO_PADREGB_PAD7STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGB_PAD7STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -1514,7 +1514,7 @@
#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_UART0RX 0x30000000
#define AM_REG_GPIO_PADREGC_PAD11FNCSEL_PDM_DATA 0x38000000
// Pad 11 drive strentgh
// Pad 11 drive strength
#define AM_REG_GPIO_PADREGC_PAD11STRNG_S 26
#define AM_REG_GPIO_PADREGC_PAD11STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGC_PAD11STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -1673,7 +1673,7 @@
#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWDIO 0x30000000
#define AM_REG_GPIO_PADREGD_PAD15FNCSEL_SWO 0x38000000
// Pad 15 drive strentgh
// Pad 15 drive strength
#define AM_REG_GPIO_PADREGD_PAD15STRNG_S 26
#define AM_REG_GPIO_PADREGD_PAD15STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGD_PAD15STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -1814,7 +1814,7 @@
#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_UART1RX 0x30000000
#define AM_REG_GPIO_PADREGE_PAD19FNCSEL_I2S_BCLK 0x38000000
// Pad 19 drive strentgh
// Pad 19 drive strength
#define AM_REG_GPIO_PADREGE_PAD19STRNG_S 26
#define AM_REG_GPIO_PADREGE_PAD19STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGE_PAD19STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -1955,7 +1955,7 @@
#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_TCTB1 0x30000000
#define AM_REG_GPIO_PADREGF_PAD23FNCSEL_UNDEF7 0x38000000
// Pad 23 drive strentgh
// Pad 23 drive strength
#define AM_REG_GPIO_PADREGF_PAD23STRNG_S 26
#define AM_REG_GPIO_PADREGF_PAD23STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGF_PAD23STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -2112,7 +2112,7 @@
#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCKLB 0x30000000
#define AM_REG_GPIO_PADREGG_PAD27FNCSEL_M2SCLLB 0x38000000
// Pad 27 drive strentgh
// Pad 27 drive strength
#define AM_REG_GPIO_PADREGG_PAD27STRNG_S 26
#define AM_REG_GPIO_PADREGG_PAD27STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGG_PAD27STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -2262,7 +2262,7 @@
#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF6 0x30000000
#define AM_REG_GPIO_PADREGH_PAD31FNCSEL_UNDEF7 0x38000000
// Pad 31 drive strentgh
// Pad 31 drive strength
#define AM_REG_GPIO_PADREGH_PAD31STRNG_S 26
#define AM_REG_GPIO_PADREGH_PAD31STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGH_PAD31STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -2403,7 +2403,7 @@
#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_UA0RTS 0x30000000
#define AM_REG_GPIO_PADREGI_PAD35FNCSEL_M3nCE2 0x38000000
// Pad 35 drive strentgh
// Pad 35 drive strength
#define AM_REG_GPIO_PADREGI_PAD35STRNG_S 26
#define AM_REG_GPIO_PADREGI_PAD35STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGI_PAD35STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -2553,7 +2553,7 @@
#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCKLB 0x30000000
#define AM_REG_GPIO_PADREGJ_PAD39FNCSEL_M4SCLLB 0x38000000
// Pad 39 drive strentgh
// Pad 39 drive strength
#define AM_REG_GPIO_PADREGJ_PAD39STRNG_S 26
#define AM_REG_GPIO_PADREGJ_PAD39STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGJ_PAD39STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -2703,7 +2703,7 @@
#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLMISOLB 0x30000000
#define AM_REG_GPIO_PADREGK_PAD43FNCSEL_SLSDALB 0x38000000
// Pad 43 drive strentgh
// Pad 43 drive strength
#define AM_REG_GPIO_PADREGK_PAD43STRNG_S 26
#define AM_REG_GPIO_PADREGK_PAD43STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGK_PAD43STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)
@ -2869,7 +2869,7 @@
#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_M4nCE5 0x30000000
#define AM_REG_GPIO_PADREGL_PAD47FNCSEL_SLWIR3LB 0x38000000
// Pad 47 drive strentgh
// Pad 47 drive strength
#define AM_REG_GPIO_PADREGL_PAD47STRNG_S 26
#define AM_REG_GPIO_PADREGL_PAD47STRNG_M 0x04000000
#define AM_REG_GPIO_PADREGL_PAD47STRNG(n) (((uint32_t)(n) << 26) & 0x04000000)

2
bsp/apollo2/libraries/drivers/regs/am_reg_iomstr.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_IOMSTR_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_ioslave.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_IOSLAVE_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_itm.h
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@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_ITM_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_jedec.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_JEDEC_H

27
bsp/apollo2/libraries/drivers/regs/am_reg_macros.h
View File

@ -1,6 +1,7 @@
//*****************************************************************************
//
//! @file am_reg_macros.h
// am_reg_macros.h
//! @file
//!
//! @brief Helper macros for using hardware registers.
//
@ -37,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
@ -106,10 +107,15 @@ extern "C"
// Register access macros for single-instance modules
// AM_REG - Write a register of a module.
// AM_BFW - Write a value to a bitfield of a register.
// AM_BFWe - Use a defined enum value to write a value to a bitfield.
// AM_BFWe - Use a defined enum value to write a value to a register bitfield.
// AM_BFR - Read a bitfield value from a register.
// AM_BFM - Read and mask a bitfield, but leave the value in its bit position.
// (Useful for comparing with enums.)
// AM_BFM - Read and mask a bitfield from a register, but leave the value in
// its bit position. Useful for comparing with enums.
//
// AM_BFV - Move a value to a bitfield. This macro is used for creating a
// value, it does not modify any register.
// AM_BFX - Extract the value of a bitfield from a 32-bit value, such as that
// read from a register. Does not read or modify any register.
//
//*****************************************************************************
#define AM_REG(module, reg) \
@ -139,16 +145,19 @@ extern "C"
//*****************************************************************************
//
// Register access macros for multi-instance modules
// AM_REGADDRn - Calc the register address inside a multiple instance module.
// AM_REGn - Write a register of a multiple instance module.
// AM_BFWn - Write a value to a bitfield of a register in a multiple instance.
// AM_BFWen - Use a defined enum value to write a value to a bitfield of a
// register in a multiple instance.
// AM_BFRn - Read a bitfield value from a register in a multiple instance.
// AM_BFMn - Read a bitfield, but leave the value in its bitfield position.
// AM_BFMn - Read and mask a bitfield, but leave the value in its bit position.
// (Useful for comparing with enums.)
//
//*****************************************************************************
#define AM_REGADDRn(module, instance, reg) \
(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O)
#define AM_REGn(module, instance, reg) \
AM_REGVAL(AM_REG_##module##n(instance) + AM_REG_##module##_##reg##_O)
@ -187,9 +196,9 @@ extern "C"
// no operator to simply write the value atomically.
// AM_REGa_SET - Set bits in a single instance module according to the mask.
// AM_REGa_CLR - Clear bits in a single instance module according to the mask.
// AM_REGna - Multiple module version of AM_REGa.
// AM_REGna_SET - Multiple instance version of AM_REGa_SET.
// AM_REGna_CLR - Multiple instance version of AM_REGa_CLR.
// AM_REGan - Multiple module version of AM_REGa.
// AM_REGan_SET - Multiple instance version of AM_REGa_SET.
// AM_REGan_CLR - Multiple instance version of AM_REGa_CLR.
// AM_BFWa - Write a value to a register bitfield.
// AM_BFWae - Use a defined enum value to write a value to a bitfield.
// AM_BFWan - Write a value to a bitfield of a register in a multiple instance.

2
bsp/apollo2/libraries/drivers/regs/am_reg_macros_asm.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************

3
bsp/apollo2/libraries/drivers/regs/am_reg_mcuctrl.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_MCUCTRL_H
@ -143,6 +143,7 @@
#define AM_REG_MCUCTRL_CHIPREV_REVMIN_M 0x0000000F
#define AM_REG_MCUCTRL_CHIPREV_REVMIN(n) (((uint32_t)(n) << 0) & 0x0000000F)
#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV0 0x00000000
#define AM_REG_MCUCTRL_CHIPREV_REVMIN_REV2 0x00000002
//*****************************************************************************
//

2
bsp/apollo2/libraries/drivers/regs/am_reg_nvic.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_NVIC_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_pdm.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_PDM_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_pwrctrl.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_PWRCTRL_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_rstgen.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_RSTGEN_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_rtc.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_RTC_H

45
bsp/apollo2/libraries/drivers/regs/am_reg_sysctrl.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_SYSCTRL_H
@ -58,6 +58,8 @@
// Register offsets.
//
//*****************************************************************************
#define AM_REG_SYSCTRL_ICTR_O 0xE000E004
#define AM_REG_SYSCTRL_ACTLR_O 0xE000E008
#define AM_REG_SYSCTRL_ICSR_O 0xE000ED04
#define AM_REG_SYSCTRL_VTOR_O 0xE000ED08
#define AM_REG_SYSCTRL_AIRCR_O 0xE000ED0C
@ -78,6 +80,47 @@
#define AM_REG_SYSCTRL_FPCAR_O 0xE000EF38
#define AM_REG_SYSCTRL_FPDSCR_O 0xE000EF3C
//*****************************************************************************
//
// SYSCTRL_ICTR - Interrupt Controller Type Register (NVIC)
//
//*****************************************************************************
// Total number of interrupt lines in groups of 32.
#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_S 0
#define AM_REG_SYSCTRL_ICTR_INTLINESNUM_M 0x0000000F
#define AM_REG_SYSCTRL_ICTR_INTLINESNUM(n) (((uint32_t)(n) << 0) & 0x0000000F)
//*****************************************************************************
//
// SYSCTRL_ACTLR - Auxilliary Control Register
//
//*****************************************************************************
// Disables lazy stacking of floating point context.
#define AM_REG_SYSCTRL_ACTLR_DISFPCA_S 9
#define AM_REG_SYSCTRL_ACTLR_DISFPCA_M 0x00000200
#define AM_REG_SYSCTRL_ACTLR_DISFPCA(n) (((uint32_t)(n) << 9) & 0x00000200)
// Disables floating point instructions completing out of order with respect to
// integer instructions.
#define AM_REG_SYSCTRL_ACTLR_DISOOFP_S 8
#define AM_REG_SYSCTRL_ACTLR_DISOOFP_M 0x00000100
#define AM_REG_SYSCTRL_ACTLR_DISOOFP(n) (((uint32_t)(n) << 8) & 0x00000100)
// Disables folding of IT instructions.
#define AM_REG_SYSCTRL_ACTLR_DISFOLD_S 2
#define AM_REG_SYSCTRL_ACTLR_DISFOLD_M 0x00000004
#define AM_REG_SYSCTRL_ACTLR_DISFOLD(n) (((uint32_t)(n) << 2) & 0x00000004)
// Disables write buffer use during default memory map accesses.
#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_S 1
#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF_M 0x00000002
#define AM_REG_SYSCTRL_ACTLR_DISDEFWBUF(n) (((uint32_t)(n) << 1) & 0x00000002)
// Disables interruption of multi-cycle instructions.
#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_S 0
#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT_M 0x00000001
#define AM_REG_SYSCTRL_ACTLR_DISMCYCINT(n) (((uint32_t)(n) << 0) & 0x00000001)
//*****************************************************************************
//
// SYSCTRL_ICSR - Interrupt Control and State Register

2
bsp/apollo2/libraries/drivers/regs/am_reg_systick.h
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@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_SYSTICK_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_tpiu.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_TPIU_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_uart.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_UART_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_vcomp.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_VCOMP_H

2
bsp/apollo2/libraries/drivers/regs/am_reg_wdt.h
View File

@ -38,7 +38,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
//
//*****************************************************************************
#ifndef AM_REG_WDT_H

1
bsp/apollo2/libraries/startup/SConscript
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@ -18,6 +18,7 @@ elif rtconfig.CROSS_TOOL == 'iar':
src = src + ['iar/' + 'startup_iar.c']
path = [cwd]
path += [cwd + '/cmsis/include']
CPPDEFINES = ['AM_PACKAGE_BGA', 'AM_PART_APOLLO2']

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bsp/apollo2/project.uvoptx
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bsp/apollo2/project.uvprojx
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