start_gcc.s fix: disable interrupt in svc mode, add rw,bss init code.
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1481 bbd45198-f89e-11dd-88c7-29a3b14d5316
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@ -102,12 +102,14 @@ pll_loop:
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#ifdef __FLASH_BUILD__
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#ifdef __FLASH_BUILD__
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/* copy exception vectors into internal sram */
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/* copy exception vectors into internal sram */
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/*
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mov r8, #RAM_BASE
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mov r8, #RAM_BASE
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ldr r9, =_start
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ldr r9, =_start
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ldmia r9!, {r0-r7}
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ldmia r9!, {r0-r7}
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stmia r8!, {r0-r7}
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stmia r8!, {r0-r7}
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ldmia r9!, {r0-r6}
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ldmia r9!, {r0-r6}
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stmia r8!, {r0-r6}
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stmia r8!, {r0-r6}
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*/
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#endif
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#endif
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/* setup stack for each mode */
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/* setup stack for each mode */
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@ -135,18 +137,60 @@ pll_loop:
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sub r0, r0, #IRQ_STACK_SIZE
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sub r0, r0, #IRQ_STACK_SIZE
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/* supervisor mode */
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/* supervisor mode */
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msr cpsr_c, #MODE_SVC
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msr cpsr_c, #MODE_SVC|I_BIT|F_BIT
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mov sp, r0
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mov sp, r0
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/* remap SRAM to 0x0000 */
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/* remap SRAM to 0x0000 */
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/*
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ldr r0, =0xFFFFFF00
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ldr r0, =0xFFFFFF00
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mov r1, #0x01
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mov r1, #0x01
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str r1, [r0]
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str r1, [r0]
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*/
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/* mask all IRQs */
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/* mask all IRQs */
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ldr r1, =0xFFFFF124
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ldr r1, =0xFFFFF124
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ldr r0, =0XFFFFFFFF
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ldr r0, =0XFFFFFFFF
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str r0, [r1]
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str r0, [r1]
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/* copy .data to SRAM */
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ldr r1, =_sidata /* .data start in image */
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ldr r2, =_edata /* .data end in image */
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ldr r3, =_sdata /* sram data start */
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data_loop:
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ldr r0, [r1, #0]
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str r0, [r3]
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add r1, r1, #4
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add r3, r3, #4
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cmp r3, r2 /* check if data to clear */
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blo data_loop /* loop until done */
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/* clear .bss */
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mov r0,#0 /* get a zero */
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ldr r1,=__bss_start /* bss start */
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ldr r2,=__bss_end /* bss end */
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bss_loop:
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cmp r1,r2 /* check if data to clear */
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strlo r0,[r1],#4 /* clear 4 bytes */
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blo bss_loop /* loop until done */
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/* call C++ constructors of global objects */
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ldr r0, =__ctors_start__
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ldr r1, =__ctors_end__
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ctor_loop:
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cmp r0, r1
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beq ctor_end
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ldr r2, [r0], #4
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stmfd sp!, {r0-r1}
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mov lr, pc
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bx r2
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ldmfd sp!, {r0-r1}
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b ctor_loop
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ctor_end:
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/* start RT-Thread Kernel */
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/* start RT-Thread Kernel */
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ldr pc, _rtthread_startup
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ldr pc, _rtthread_startup
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