diff --git a/bsp/cvitek/cv1800b/board/board.c b/bsp/cvitek/cv1800b/board/board.c
index ad1ee75b07..6df8cd7a23 100755
--- a/bsp/cvitek/cv1800b/board/board.c
+++ b/bsp/cvitek/cv1800b/board/board.c
@@ -109,12 +109,3 @@ void rt_hw_board_init(void)
     rt_kprintf("heap: [0x%08x - 0x%08x]\n", (rt_ubase_t)RT_HW_HEAP_BEGIN, (rt_ubase_t)RT_HW_HEAP_END);
 #endif /* RT_USING_HEAP */
 }
-
-void rt_hw_cpu_reset(void)
-{
-    sbi_shutdown();
-
-    while (1)
-        ;
-}
-MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/cvitek/drivers/SConscript b/bsp/cvitek/drivers/SConscript
index 519df88a0e..83c882470c 100755
--- a/bsp/cvitek/drivers/SConscript
+++ b/bsp/cvitek/drivers/SConscript
@@ -1,7 +1,10 @@
 from building import *
 
 cwd     = GetCurrentDir()
-src     = ['drv_uart.c']
+src     = Split('''
+drv_uart.c
+drv_por.c
+''')
 CPPDEFINES = []
 
 CPPPATH = [cwd]
diff --git a/bsp/cvitek/drivers/drv_por.c b/bsp/cvitek/drivers/drv_por.c
new file mode 100644
index 0000000000..0d25f06582
--- /dev/null
+++ b/bsp/cvitek/drivers/drv_por.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date         Author          Notes
+ * 2024-03-21   qiujingbao     the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+
+#define DBG_TAG "DRV.POR"
+#define DBG_LVL DBG_WARNING
+#include <rtdbg.h>
+
+#include "mmio.h"
+
+#define CVI_RTC_CTRL_BASE       0x05025000U
+#define CVI_RTC_REG_BASE        0x05026000U
+#define RTC_CTRL0_UNLOCKKEY     0x4
+#define RTC_CTRL0               0x8
+#define RTC_APB_BUSY_SEL        0x3C
+#define RTC_EN_WARM_RST_REQ     0xCC
+#define RSM_STATE               0xD4
+#define ST_ON                   0x3
+
+static int cvi_restart(void)
+{
+    /* Enable power suspend wakeup source mask */
+    mmio_write_32(CVI_RTC_REG_BASE + RTC_APB_BUSY_SEL,0x1);
+
+    /* unlock register */
+    mmio_write_32(CVI_RTC_CTRL_BASE + RTC_CTRL0_UNLOCKKEY, 0xAB18);
+
+    mmio_write_32(CVI_RTC_REG_BASE + RTC_EN_WARM_RST_REQ, 0x1);
+
+    while (mmio_read_32(CVI_RTC_REG_BASE + RTC_EN_WARM_RST_REQ) != 0x01);
+
+    while (mmio_read_32(CVI_RTC_REG_BASE + RSM_STATE) != ST_ON);
+
+    mmio_write_32( CVI_RTC_CTRL_BASE + RTC_CTRL0,0xFFFF0800 | (0x1 << 4));
+
+    return 0;
+}
+
+void rt_hw_cpu_reset(void)
+{
+    cvi_restart();
+
+    while (1);
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);