Fixed sample rate not set correctly under slave I2S mode. (Tested this time. ^_^)
Added locking mechanism to periperials on SPI1. Added DMA mode read/write routine to SPI Flash. (Debug reuiqred. WARNING: !!! ENABLING DMA MODE MAY DESTROY YOUR DATA IN THE SPI FLASH !!!) git-svn-id: https://rt-thread.googlecode.com/svn/trunk@538 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
kyle.hu.gz
parent
28232de6d0
commit
04428f9a8a
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@ -18,6 +18,8 @@
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#include "stm32f10x.h"
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#include "board.h"
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struct rt_semaphore spi1_lock;
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/**
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* @addtogroup STM32
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*/
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@ -87,7 +89,7 @@ static void all_device_reset(void)
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| RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG,ENABLE);
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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/* SDIO POWER */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
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@ -279,6 +281,11 @@ void rt_hw_board_init()
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/* Enable SPI_MASTER */
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SPI_Cmd(SPI1, ENABLE);
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SPI_CalculateCRC(SPI1, DISABLE);
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if (rt_sem_init(&spi1_lock, "spi1lock", 1, RT_IPC_FLAG_FIFO) != RT_EOK)
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{
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rt_kprintf("init spi1 lock semaphore failed\n");
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}
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}
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}/* rt_hw_board_init */
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@ -69,6 +69,8 @@ void rt_hw_board_init(void);
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void rt_hw_usart_init(void);
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void rt_hw_sdcard_init(void);
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extern struct rt_semaphore spi1_lock;
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#endif
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// <<< Use Configuration Wizard in Context Menu >>>
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@ -81,6 +81,10 @@ struct codec_device codec;
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static uint16_t r06 = REG_CLOCK_GEN | CLKSEL_PLL | MCLK_DIV2 | BCLK_DIV8;
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#if !CODEC_MASTER_MODE
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static int codec_sr_new = 0;
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#endif
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static void NVIC_Configuration(void)
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{
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NVIC_InitTypeDef NVIC_InitStructure;
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@ -108,7 +112,7 @@ static void GPIO_Configuration(void)
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// WS
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GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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#if CODEC_MASTER_MODE
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
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#else
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@ -207,10 +211,14 @@ uint8_t SPI_WriteByte(unsigned char data)
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static void codec_send(rt_uint16_t s_data)
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{
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rt_sem_take(&spi1_lock, RT_WAITING_FOREVER);
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codec_reset_csb();
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SPI_WriteByte((s_data >> 8) & 0xFF);
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SPI_WriteByte(s_data & 0xFF);
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codec_set_csb();
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rt_sem_release(&spi1_lock);
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}
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static rt_err_t codec_init(rt_device_t dev)
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@ -406,7 +414,7 @@ rt_err_t sample_rate(int sr)
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codec_send(r07);
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#if !CODEC_MASTER_MODE
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I2S_Configuration((uint32_t) sr);
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codec_sr_new = sr;
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#endif
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return RT_EOK;
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@ -481,9 +489,7 @@ static rt_err_t codec_control(rt_device_t dev, rt_uint8_t cmd, void *args)
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break;
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case CODEC_CMD_SAMPLERATE:
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dev->close(dev);
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sample_rate(*((int*) args));
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dev->open(dev,0);
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break;
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case CODEC_CMD_EQ:
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@ -601,6 +607,15 @@ void codec_dma_isr(void)
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/* save current data pointer */
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data_ptr = codec.data_list[codec.read_index].data_ptr;
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#if !CODEC_MASTER_MODE
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if (codec_sr_new)
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{
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I2S_Configuration(codec_sr_new);
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I2S_Cmd(CODEC_I2S_PORT, ENABLE);
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codec_sr_new = 0;
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}
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#endif
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codec.read_index = next_index;
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if (next_index != codec.put_index)
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{
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@ -1,8 +1,22 @@
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#include <stm32f10x.h>
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#include "board.h"
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#include "spi_flash.h"
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#include "rtthread.h"
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extern unsigned char SPI_WriteByte(unsigned char data);
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/*
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* WARNING: !!! ENABLING DMA MODE MAY DESTROY YOUR DATA IN THE SPI FLASH !!!
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* Don't set SPI_FLASH_USE_DMA to 1 unless you know what you're doing!
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* However, readonly access is just fine. :)
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*/
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#define SPI_FLASH_USE_DMA 0
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#define SECTOR_SIZE 512
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extern uint8_t SPI_WriteByte(unsigned char data);
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#if SPI_FLASH_USE_DMA
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static uint8_t dummy = 0;
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static uint8_t _spi_flash_buffer[SECTOR_SIZE];
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#endif
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/********************** hardware *************************************/
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/* SPI_FLASH_CS PA4 */
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@ -22,7 +36,7 @@ static void GPIO_Configuration(void)
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_3;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_Init(GPIOA, &GPIO_InitStructure);
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FLASH_RST_0(); // RESET
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@ -30,7 +44,90 @@ static void GPIO_Configuration(void)
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FLASH_RST_1();
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}
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static unsigned char SPI_HostReadByte(void)
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#if SPI_FLASH_USE_DMA
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static void DMA_RxConfiguration(rt_uint32_t addr, rt_size_t size)
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_ClearFlag(DMA1_FLAG_TC2 | DMA1_FLAG_TE2 | DMA1_FLAG_TC3 | DMA1_FLAG_TE3);
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dummy = 0;
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/* DMA Channel configuration ----------------------------------------------*/
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DMA_Cmd(DMA1_Channel2, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(SPI1->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) addr;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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DMA_InitStructure.DMA_BufferSize = size;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel2, &DMA_InitStructure);
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DMA_Cmd(DMA1_Channel2, ENABLE);
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/* Dummy TX channel configuration */
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DMA_Cmd(DMA1_Channel3, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(SPI1->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32)(&dummy);
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = size;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel3, &DMA_InitStructure);
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DMA_Cmd(DMA1_Channel3, ENABLE);
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}
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static void DMA_TxConfiguration(rt_uint32_t addr, rt_size_t size)
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{
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DMA_InitTypeDef DMA_InitStructure;
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DMA_ClearFlag(DMA1_FLAG_TC2 | DMA1_FLAG_TE2 | DMA1_FLAG_TC3 | DMA1_FLAG_TE3);
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/* DMA Channel configuration ----------------------------------------------*/
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DMA_Cmd(DMA1_Channel2, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(SPI1->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32)(&dummy);
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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DMA_InitStructure.DMA_BufferSize = size;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel2, &DMA_InitStructure);
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/* DMA Channel configuration ----------------------------------------------*/
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DMA_Cmd(DMA1_Channel3, DISABLE);
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DMA_InitStructure.DMA_PeripheralBaseAddr = (u32)(&(SPI1->DR));
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DMA_InitStructure.DMA_MemoryBaseAddr = (u32) addr;
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DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
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DMA_InitStructure.DMA_BufferSize = size;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Priority = DMA_Priority_Medium;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel3, &DMA_InitStructure);
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DMA_Cmd(DMA1_Channel3, ENABLE);
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}
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#endif
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static uint8_t SPI_HostReadByte(void)
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{
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//return SPI_WriteByte(0x00);
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//Wait until the transmit buffer is empty
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}
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static void SPI_HostWriteByte(unsigned char wByte)
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static void SPI_HostWriteByte(uint8_t wByte)
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{
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SPI_WriteByte(wByte);
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}
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@ -63,9 +160,9 @@ static void SPI_HostWriteByte(unsigned char wByte)
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/* 1:ready | | AT45DB161:1011 | */
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/* --------------------------------------------------------------------------*/
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/*****************************************************************************/
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static unsigned char AT45DB_StatusRegisterRead(void)
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static uint8_t AT45DB_StatusRegisterRead(void)
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{
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unsigned char i;
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uint8_t i;
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FLASH_CS_0();
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SPI_HostWriteByte(AT45DB_READ_STATE_REGISTER);
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@ -77,74 +174,122 @@ static unsigned char AT45DB_StatusRegisterRead(void)
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static void wait_busy(void)
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{
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unsigned int i=0;
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while (i++<3000)
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uint16_t i = 0;
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while (i++ < 10000)
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{
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if (AT45DB_StatusRegisterRead() & 0x80)
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{
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break;
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return;
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}
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}
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if( !(i<3000) )
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{
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rt_kprintf("\r\nSPI_FLASH timeout!!!");
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}
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rt_kprintf("\r\nSPI_FLASH timeout!!!\r\n");
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}
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static void read_page(unsigned int page,unsigned char * pHeader)
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static void read_page(uint32_t page, uint8_t *pHeader)
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{
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unsigned int i=0;
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#if SPI_FLASH_USE_DMA
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rt_sem_take(&spi1_lock, RT_WAITING_FOREVER);
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wait_busy();
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DMA_RxConfiguration((rt_uint32_t) pHeader, SECTOR_SIZE);
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FLASH_CS_0();
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SPI_HostWriteByte(AT45DB_MM_PAGE_TO_B1_XFER);
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SPI_HostWriteByte((unsigned char)(page >> 6));
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SPI_HostWriteByte((unsigned char)(page << 2));
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SPI_HostWriteByte(AT45DB_MM_PAGE_READ);
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SPI_HostWriteByte((uint8_t)(page >> 6));
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SPI_HostWriteByte((uint8_t)(page << 2));
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SPI_HostWriteByte(0x00);
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// 4 don't care bytes
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SPI_HostWriteByte(0x00);
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SPI_HostWriteByte(0x00);
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SPI_HostWriteByte(0x00);
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SPI_HostWriteByte(0x00);
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SPI_I2S_ClearFlag(SPI1, SPI_I2S_FLAG_RXNE);
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SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
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while (DMA_GetFlagStatus(DMA1_FLAG_TC2) == RESET);
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FLASH_CS_1();
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wait_busy();
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SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, DISABLE);
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rt_sem_release(&spi1_lock);
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#else
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uint16_t i;
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rt_sem_take(&spi1_lock, RT_WAITING_FOREVER);
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FLASH_CS_0();
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SPI_HostWriteByte(AT45DB_BUFFER_1_READ);
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SPI_HostWriteByte(AT45DB_MM_PAGE_READ);
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SPI_HostWriteByte((uint8_t)(page >> 6));
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SPI_HostWriteByte((uint8_t)(page << 2));
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SPI_HostWriteByte(0x00);
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// 4 don't care bytes
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SPI_HostWriteByte(0x00);
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SPI_HostWriteByte(0x00);
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SPI_HostWriteByte(0x00);
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SPI_HostWriteByte(0x00);
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for (i=0; i<512; i++)
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for (i = 0; i < SECTOR_SIZE; i++)
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{
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*pHeader++ = SPI_HostReadByte();
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}
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FLASH_CS_1();
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rt_sem_release(&spi1_lock);
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#endif
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}
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static void write_page(unsigned int page,unsigned char * pHeader)
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static void write_page(uint32_t page, uint8_t *pHeader)
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{
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unsigned int i;
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#if SPI_FLASH_USE_DMA
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rt_sem_take(&spi1_lock, RT_WAITING_FOREVER);
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DMA_TxConfiguration((rt_uint32_t) pHeader, SECTOR_SIZE);
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FLASH_CS_0();
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SPI_HostWriteByte(AT45DB_MM_PAGE_PROG_THRU_BUFFER1);
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SPI_HostWriteByte((uint8_t) (page >> 6));
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SPI_HostWriteByte((uint8_t) (page << 2));
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SPI_HostWriteByte(0x00);
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SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx, ENABLE);
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while (DMA_GetFlagStatus(DMA1_FLAG_TC3) == RESET);
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FLASH_CS_1();
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SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx, DISABLE);
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wait_busy();
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rt_sem_release(&spi1_lock);
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#else
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uint16_t i;
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rt_sem_take(&spi1_lock, RT_WAITING_FOREVER);
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FLASH_CS_0();
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SPI_HostWriteByte(AT45DB_BUFFER_2_WRITE);
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SPI_HostWriteByte(0);
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SPI_HostWriteByte(0);
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SPI_HostWriteByte(0);
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for(i=0; i<512; i++)
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SPI_HostWriteByte(AT45DB_MM_PAGE_PROG_THRU_BUFFER1);
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SPI_HostWriteByte((uint8_t) (page >> 6));
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SPI_HostWriteByte((uint8_t) (page << 2));
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SPI_HostWriteByte(0x00);
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for (i = 0; i < SECTOR_SIZE; i++)
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{
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SPI_HostWriteByte(*pHeader++);
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}
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FLASH_CS_1();
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wait_busy();
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FLASH_CS_0();
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SPI_HostWriteByte(AT45DB_B2_TO_MM_PAGE_PROG_WITH_ERASE);
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SPI_HostWriteByte((unsigned char)(page>>6));
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SPI_HostWriteByte((unsigned char)(page<<2));
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SPI_HostWriteByte(0x00);
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FLASH_CS_1();
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rt_sem_release(&spi1_lock);
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#endif
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}
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@ -176,42 +321,53 @@ static rt_err_t rt_spi_flash_control(rt_device_t dev, rt_uint8_t cmd, void *args
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static rt_size_t rt_spi_flash_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
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{
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rt_uint8_t *ptr;
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rt_uint32_t index, nr;
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nr = size/512;
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ptr = (rt_uint8_t*)buffer;
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nr = size / SECTOR_SIZE;
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for (index = 0; index < nr; index++)
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{
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/* only supply single block read: block size 512Byte */
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read_page((pos + index * 512)/512, &ptr[index * 512]);
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#if SPI_FLASH_USE_DMA
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read_page((pos / SECTOR_SIZE + index), _spi_flash_buffer);
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rt_memcpy(((rt_uint8_t *) buffer + index * SECTOR_SIZE), _spi_flash_buffer, SECTOR_SIZE);
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#else
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read_page((pos / SECTOR_SIZE + index), ((rt_uint8_t *) buffer + index * SECTOR_SIZE));
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#endif
|
||||
}
|
||||
|
||||
return nr * 512;
|
||||
return nr * SECTOR_SIZE;
|
||||
}
|
||||
|
||||
static rt_size_t rt_spi_flash_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||
{
|
||||
rt_uint8_t *ptr;
|
||||
rt_uint32_t index, nr;
|
||||
|
||||
nr = size / 512;
|
||||
ptr = (rt_uint8_t*)buffer;
|
||||
nr = size / SECTOR_SIZE;
|
||||
|
||||
for (index = 0; index < nr; index++)
|
||||
{
|
||||
/* only supply single block write: block size 512Byte */
|
||||
write_page((pos + index * 512)/512, &ptr[index * 512]);
|
||||
#if SPI_FLASH_USE_DMA
|
||||
rt_memcpy(_spi_flash_buffer, ((rt_uint8_t *) buffer + index * SECTOR_SIZE), SECTOR_SIZE);
|
||||
write_page((pos / SECTOR_SIZE + index), _spi_flash_buffer);
|
||||
#else
|
||||
write_page((pos / SECTOR_SIZE + index), ((rt_uint8_t *) buffer + index * SECTOR_SIZE));
|
||||
#endif
|
||||
}
|
||||
|
||||
return nr * 512;
|
||||
return nr * SECTOR_SIZE;
|
||||
}
|
||||
|
||||
void rt_hw_spi_flash_init(void)
|
||||
{
|
||||
GPIO_Configuration();
|
||||
|
||||
#if SPI_FLASH_USE_DMA
|
||||
/* Enable the DMA1 Clock */
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
|
||||
#endif
|
||||
|
||||
/* register spi_flash device */
|
||||
spi_flash_device.type = RT_Device_Class_Block;
|
||||
spi_flash_device.init = rt_spi_flash_init;
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ thanks to gxlujd.
|
|||
#define AT45DB_PAGE_ERASE 0x81 /* 页删除（每页512/528字节） */
|
||||
#define AT45DB_SECTOR_ERASE 0x7C /* 扇区擦除（每扇区128K字节）*/
|
||||
#define AT45DB_READ_STATE_REGISTER 0xD7 /* 读取状态寄存器 */
|
||||
|
||||
#define AT45DB_MM_PAGE_READ 0xD2 /* 读取主储存器的指定页 */
|
||||
#define AT45DB_MM_PAGE_PROG_THRU_BUFFER1 0x82 /* 通过缓冲区写入主储存器 */
|
||||
|
||||
extern void rt_hw_spi_flash_init(void);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue