From 72fd4f04279599197454bb19bdfb38ec3d61613b Mon Sep 17 00:00:00 2001 From: luhuadong Date: Thu, 27 Jun 2019 15:21:17 +0800 Subject: [PATCH 1/2] =?UTF-8?q?stm32f767-st-nucleo=20BSP=20=E6=B7=BB?= =?UTF-8?q?=E5=8A=A0=E4=BB=A5=E5=A4=AA=E7=BD=91=E9=A9=B1=E5=8A=A8=E6=94=AF?= =?UTF-8?q?=E6=8C=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/stm32f767-st-nucleo/README.md | 2 +- bsp/stm32/stm32f767-st-nucleo/board/Kconfig | 20 +++++++++++++++++- .../stm32f767-st-nucleo/board/SConscript | 4 ++++ .../board/ports/phy_reset.c | 21 +++++++++++++++++++ 4 files changed, 45 insertions(+), 2 deletions(-) create mode 100644 bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c diff --git a/bsp/stm32/stm32f767-st-nucleo/README.md b/bsp/stm32/stm32f767-st-nucleo/README.md index b5c74c87f6..45ccf66f70 100644 --- a/bsp/stm32/stm32f767-st-nucleo/README.md +++ b/bsp/stm32/stm32f767-st-nucleo/README.md @@ -38,7 +38,7 @@ NUCLEO-F767ZI 是st推出的一款基于 ARM Cortex-M7 内核的开发板，最 | **板载外设** | **支持情况** | **备注** | | :-----------------| :----------: | :-------------------------------------| | USB 转串口3 | 支持 | | -| 以太网 | 暂不支持 | 即将支持 | +| 以太网 | 支持 | PHY 选项 LAN8720A（兼容 LAN8742A） | | **片上外设** | **支持情况** | **备注** | | GPIO | 支持 | PA0, PA1... PK15 ---> PIN: 0, 1...144 | | UART | 支持 | UART3 | diff --git a/bsp/stm32/stm32f767-st-nucleo/board/Kconfig b/bsp/stm32/stm32f767-st-nucleo/board/Kconfig index 0e62854a44..920138393f 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f767-st-nucleo/board/Kconfig @@ -7,11 +7,29 @@ config SOC_STM32F767ZI menu "Onboard Peripheral Drivers" - config BSP_USING_USB_TO_USART + config BSP_USING_USB_TO_USART bool "Enable USB TO USART (uart3)" select BSP_USING_UART3 default y + config BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_LWIP + default n + + if BSP_USING_ETH + choice + prompt "On-board PHY chip" + default PHY_USING_LAN8720A + + config PHY_USING_LAN8720A + bool "LAN8720A" + + config PHY_USING_DM9161CEP + bool "DM9161CEP" + + endchoice + endif endmenu diff --git a/bsp/stm32/stm32f767-st-nucleo/board/SConscript b/bsp/stm32/stm32f767-st-nucleo/board/SConscript index 12ea0a24cc..a49a0955b1 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/SConscript +++ b/bsp/stm32/stm32f767-st-nucleo/board/SConscript @@ -7,8 +7,12 @@ cwd = GetCurrentDir() src = Glob('board.c') src += Glob('CubeMX_Config/Src/stm32f7xx_hal_msp.c') +if GetDepend(['BSP_USING_ETH']): + src += Glob('ports/phy_reset.c') + path = [cwd] path += [cwd + '/CubeMX_Config/Inc'] +path += [cwd + '/ports'] if rtconfig.CROSS_TOOL == 'gcc': src += [cwd + '/../../libraries/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s'] diff --git a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c new file mode 100644 index 0000000000..012d5a81eb --- /dev/null +++ b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2006-2019, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-06-27 luhuadong first version + */ + +#include + +void phy_reset(void) +{ + /* + * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin, + * so no additional reset is required. + */ + + return ; +} From 97d8f14aebd3f55f2de01742fbf4caac01fc614e Mon Sep 17 00:00:00 2001 From: luhuadong Date: Thu, 27 Jun 2019 17:14:03 +0800 Subject: [PATCH 2/2] =?UTF-8?q?=E8=B0=83=E6=95=B4=E7=BC=A9=E8=BF=9B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/stm32f767-st-nucleo/board/Kconfig | 28 +++++++++---------- .../board/ports/phy_reset.c | 12 ++++---- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/bsp/stm32/stm32f767-st-nucleo/board/Kconfig b/bsp/stm32/stm32f767-st-nucleo/board/Kconfig index 920138393f..6bb14b0a83 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/Kconfig +++ b/bsp/stm32/stm32f767-st-nucleo/board/Kconfig @@ -12,24 +12,24 @@ menu "Onboard Peripheral Drivers" select BSP_USING_UART3 default y - config BSP_USING_ETH - bool "Enable Ethernet" - select RT_USING_LWIP - default n + config BSP_USING_ETH + bool "Enable Ethernet" + select RT_USING_LWIP + default n - if BSP_USING_ETH - choice - prompt "On-board PHY chip" - default PHY_USING_LAN8720A + if BSP_USING_ETH + choice + prompt "On-board PHY chip" + default PHY_USING_LAN8720A - config PHY_USING_LAN8720A - bool "LAN8720A" + config PHY_USING_LAN8720A + bool "LAN8720A" - config PHY_USING_DM9161CEP - bool "DM9161CEP" + config PHY_USING_DM9161CEP + bool "DM9161CEP" - endchoice - endif + endchoice + endif endmenu diff --git a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c index 012d5a81eb..8a833eec2a 100644 --- a/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c +++ b/bsp/stm32/stm32f767-st-nucleo/board/ports/phy_reset.c @@ -12,10 +12,10 @@ void phy_reset(void) { - /* - * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin, - * so no additional reset is required. - */ - - return ; + /* + * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin, + * so no additional reset is required. + */ + + return ; }