mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2025-02-07 19:14:34 +08:00
update lpc178x bsp
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1764 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
parent
5de50e1422
commit
01a17f4f38
@ -40,19 +40,19 @@
|
|||||||
/* thread phase init */
|
/* thread phase init */
|
||||||
void rt_init_thread_entry(void *parameter)
|
void rt_init_thread_entry(void *parameter)
|
||||||
{
|
{
|
||||||
unsigned int count=0;
|
// unsigned int count=0;
|
||||||
|
//
|
||||||
while (1)
|
// while (1)
|
||||||
{
|
// {
|
||||||
/* led1 on */
|
// /* led1 on */
|
||||||
rt_kprintf("on count : %d\r\n",count);
|
// rt_kprintf("on count : %d\r\n",count);
|
||||||
count++;
|
// count++;
|
||||||
rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
|
// rt_thread_delay( RT_TICK_PER_SECOND/2 ); /* sleep 0.5 second and switch to other thread */
|
||||||
|
//
|
||||||
/* led1 off */
|
// /* led1 off */
|
||||||
rt_kprintf("led off\r\n");
|
// rt_kprintf("led off\r\n");
|
||||||
rt_thread_delay( RT_TICK_PER_SECOND/2 );
|
// rt_thread_delay( RT_TICK_PER_SECOND/2 );
|
||||||
}
|
// }
|
||||||
|
|
||||||
/* Filesystem Initialization */
|
/* Filesystem Initialization */
|
||||||
#ifdef RT_USING_DFS
|
#ifdef RT_USING_DFS
|
||||||
|
@ -20,6 +20,7 @@
|
|||||||
#define RT_UART_RX_BUFFER_SIZE 64
|
#define RT_UART_RX_BUFFER_SIZE 64
|
||||||
#define RT_USING_UART0
|
#define RT_USING_UART0
|
||||||
#define RT_USING_UART1
|
#define RT_USING_UART1
|
||||||
|
#define RT_USING_UART2
|
||||||
|
|
||||||
#define CONSOLE_DEVICE "uart1"
|
#define CONSOLE_DEVICE "uart1"
|
||||||
#define FINSH_DEVICE_NAME "uart1"
|
#define FINSH_DEVICE_NAME "uart1"
|
||||||
|
@ -46,231 +46,255 @@
|
|||||||
|
|
||||||
/*@{*/
|
/*@{*/
|
||||||
|
|
||||||
#define UART_BAUDRATE 115200
|
|
||||||
#define LPC_UART LPC_UART0
|
|
||||||
#define UART_IRQn UART0_IRQn
|
|
||||||
|
|
||||||
struct rt_uart_lpc
|
struct rt_uart_lpc
|
||||||
{
|
{
|
||||||
struct rt_device parent;
|
struct rt_device parent;
|
||||||
|
|
||||||
LPC_UART_TypeDef * UART;
|
LPC_UART_TypeDef * UART;
|
||||||
|
IRQn_Type UART_IRQn;
|
||||||
|
|
||||||
/* buffer for reception */
|
/* buffer for reception */
|
||||||
rt_uint8_t read_index, save_index;
|
rt_uint8_t read_index, save_index;
|
||||||
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#ifdef RT_USING_UART0
|
||||||
|
struct rt_uart_lpc uart0_device;
|
||||||
|
#endif
|
||||||
#ifdef RT_USING_UART1
|
#ifdef RT_USING_UART1
|
||||||
struct rt_uart_lpc uart1_device;
|
struct rt_uart_lpc uart1_device;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
void UART0_IRQHandler(void)
|
void UART0_IRQHandler(void)
|
||||||
{
|
{
|
||||||
// rt_ubase_t level, iir;
|
rt_ubase_t level, iir;
|
||||||
// struct rt_uart_lpc* uart = &uart_device;
|
struct rt_uart_lpc* uart = &uart0_device;
|
||||||
//
|
|
||||||
// /* read IIR and clear it */
|
/* enter interrupt */
|
||||||
// iir = LPC_UART->IIR;
|
rt_interrupt_enter();
|
||||||
//
|
|
||||||
|
/* read IIR and clear it */
|
||||||
|
iir = uart->UART->IIR;
|
||||||
|
|
||||||
|
iir >>= 1; /* skip pending bit in IIR */
|
||||||
|
iir &= 0x07; /* check bit 1~3, interrupt identification */
|
||||||
|
|
||||||
|
if (iir == IIR_RDA) /* Receive Data Available */
|
||||||
|
{
|
||||||
|
/* Receive Data Available */
|
||||||
|
uart->rx_buffer[uart->save_index] = uart->UART->RBR;
|
||||||
|
|
||||||
|
level = rt_hw_interrupt_disable();
|
||||||
|
uart->save_index ++;
|
||||||
|
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||||
|
uart->save_index = 0;
|
||||||
|
rt_hw_interrupt_enable(level);
|
||||||
|
|
||||||
|
/* invoke callback */
|
||||||
|
if(uart->parent.rx_indicate != RT_NULL)
|
||||||
|
{
|
||||||
|
rt_size_t length;
|
||||||
|
if (uart->read_index > uart->save_index)
|
||||||
|
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
|
||||||
|
else
|
||||||
|
length = uart->save_index - uart->read_index;
|
||||||
|
|
||||||
|
uart->parent.rx_indicate(&uart->parent, length);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
void UART1_IRQHandler(void)
|
||||||
|
{
|
||||||
|
rt_ubase_t level, iir;
|
||||||
|
struct rt_uart_lpc* uart = &uart1_device;
|
||||||
|
|
||||||
|
/* enter interrupt */
|
||||||
|
rt_interrupt_enter();
|
||||||
|
|
||||||
|
/* read IIR and clear it */
|
||||||
|
iir = uart->UART->IIR;
|
||||||
|
|
||||||
// iir >>= 1; /* skip pending bit in IIR */
|
// iir >>= 1; /* skip pending bit in IIR */
|
||||||
// iir &= 0x07; /* check bit 1~3, interrupt identification */
|
// iir &= 0x07; /* check bit 1~3, interrupt identification */
|
||||||
//
|
|
||||||
// if (iir == IIR_RDA) /* Receive Data Available */
|
if (iir == UART_IIR_INTID_RDA) /* Receive Data Available */
|
||||||
// {
|
{
|
||||||
// /* Receive Data Available */
|
/* Receive Data Available */
|
||||||
// uart->rx_buffer[uart->save_index] = LPC_UART->RBR;
|
uart->rx_buffer[uart->save_index] = uart->UART->RBR;
|
||||||
//
|
|
||||||
// level = rt_hw_interrupt_disable();
|
level = rt_hw_interrupt_disable();
|
||||||
// uart->save_index ++;
|
uart->save_index ++;
|
||||||
// if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
|
if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
|
||||||
// uart->save_index = 0;
|
uart->save_index = 0;
|
||||||
// rt_hw_interrupt_enable(level);
|
rt_hw_interrupt_enable(level);
|
||||||
//
|
|
||||||
// /* invoke callback */
|
/* invoke callback */
|
||||||
// if(uart->parent.rx_indicate != RT_NULL)
|
if(uart->parent.rx_indicate != RT_NULL)
|
||||||
// {
|
{
|
||||||
// rt_size_t length;
|
rt_size_t length;
|
||||||
// if (uart->read_index > uart->save_index)
|
if (uart->read_index > uart->save_index)
|
||||||
// length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
|
length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
|
||||||
// else
|
else
|
||||||
// length = uart->save_index - uart->read_index;
|
length = uart->save_index - uart->read_index;
|
||||||
//
|
|
||||||
// uart->parent.rx_indicate(&uart->parent, length);
|
uart->parent.rx_indicate(&uart->parent, length);
|
||||||
// }
|
}
|
||||||
// }
|
}
|
||||||
//
|
|
||||||
// return;
|
/* leave interrupt */
|
||||||
|
rt_interrupt_leave();
|
||||||
|
|
||||||
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
static rt_err_t rt_uart_init (rt_device_t dev)
|
static rt_err_t rt_uart_init (rt_device_t dev)
|
||||||
{
|
{
|
||||||
// rt_uint32_t Fdiv;
|
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
|
||||||
// rt_uint32_t pclkdiv, pclk;
|
UART_CFG_Type UART_ConfigStruct;
|
||||||
//
|
|
||||||
// /* Init UART Hardware */
|
#ifdef RT_USING_UART0
|
||||||
// if (LPC_UART == LPC_UART0)
|
if( uart->UART == LPC_UART0 )
|
||||||
// {
|
{
|
||||||
// LPC_PINCON->PINSEL0 &= ~0x000000F0;
|
/*
|
||||||
// LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
|
* Initialize UART0 pin connect
|
||||||
// /* By default, the PCLKSELx value is zero, thus, the PCLK for
|
* P0.2: TXD
|
||||||
// all the peripherals is 1/4 of the SystemFrequency. */
|
* P0.3: RXD
|
||||||
// /* Bit 6~7 is for UART0 */
|
*/
|
||||||
// pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
|
PINSEL_ConfigPin(0, 2, 1);
|
||||||
// switch ( pclkdiv )
|
PINSEL_ConfigPin(0, 2, 1);
|
||||||
// {
|
|
||||||
// case 0x00:
|
UART_ConfigStruct.Baud_rate = 115200;
|
||||||
// default:
|
UART_ConfigStruct.Databits = UART_DATABIT_8;
|
||||||
// pclk = SystemCoreClock/4;
|
UART_ConfigStruct.Parity = UART_PARITY_NONE;
|
||||||
// break;
|
UART_ConfigStruct.Stopbits = UART_STOPBIT_1;
|
||||||
// case 0x01:
|
|
||||||
// pclk = SystemCoreClock;
|
UART_Init( uart->UART, &UART_ConfigStruct);
|
||||||
// break;
|
|
||||||
// case 0x02:
|
// Enable UART Transmit
|
||||||
// pclk = SystemCoreClock/2;
|
UART_TxCmd( uart->UART, ENABLE);
|
||||||
// break;
|
|
||||||
// case 0x03:
|
UART_IntConfig( uart->UART, UART_INTCFG_RLS, ENABLE);
|
||||||
// pclk = SystemCoreClock/8;
|
}
|
||||||
// break;
|
#endif
|
||||||
// }
|
|
||||||
//
|
#ifdef RT_USING_UART1
|
||||||
// LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
if( ((LPC_UART1_TypeDef *)uart->UART) == LPC_UART1 )
|
||||||
// Fdiv = ( pclk / 16 ) / UART_BAUDRATE; /*baud rate */
|
{
|
||||||
// LPC_UART0->DLM = Fdiv / 256;
|
/*
|
||||||
// LPC_UART0->DLL = Fdiv % 256;
|
* Initialize UART1 pin connect
|
||||||
// LPC_UART0->LCR = 0x03; /* DLAB = 0 */
|
* P3.16: TXD
|
||||||
// LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
* P3.17: RXD
|
||||||
// }
|
*/
|
||||||
// else if ((LPC_UART1_TypeDef*)LPC_UART == LPC_UART1)
|
PINSEL_ConfigPin(3, 16, 3);
|
||||||
// {
|
PINSEL_ConfigPin(3, 17, 3);
|
||||||
// LPC_PINCON->PINSEL4 &= ~0x0000000F;
|
|
||||||
// LPC_PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
|
UART_ConfigStruct.Baud_rate = 115200;
|
||||||
//
|
UART_ConfigStruct.Databits = UART_DATABIT_8;
|
||||||
// /* By default, the PCLKSELx value is zero, thus, the PCLK for
|
UART_ConfigStruct.Parity = UART_PARITY_NONE;
|
||||||
// all the peripherals is 1/4 of the SystemFrequency. */
|
UART_ConfigStruct.Stopbits = UART_STOPBIT_1;
|
||||||
// /* Bit 8,9 are for UART1 */
|
|
||||||
// pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
|
UART_Init( uart->UART,&UART_ConfigStruct);
|
||||||
// switch ( pclkdiv )
|
|
||||||
// {
|
// Enable UART Transmit
|
||||||
// case 0x00:
|
UART_TxCmd( uart->UART, ENABLE);
|
||||||
// default:
|
|
||||||
// pclk = SystemCoreClock/4;
|
UART_IntConfig( uart->UART, UART_INTCFG_RLS, ENABLE);
|
||||||
// break;
|
UART_IntConfig( uart->UART, UART_INTCFG_RBR, ENABLE);
|
||||||
// case 0x01:
|
}
|
||||||
// pclk = SystemCoreClock;
|
#endif
|
||||||
// break;
|
|
||||||
// case 0x02:
|
#ifdef RT_USING_UART2
|
||||||
// pclk = SystemCoreClock/2;
|
if( uart->UART == LPC_UART2 )
|
||||||
// break;
|
{
|
||||||
// case 0x03:
|
}
|
||||||
// pclk = SystemCoreClock/8;
|
#endif
|
||||||
// break;
|
|
||||||
// }
|
|
||||||
//
|
|
||||||
// LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
|
||||||
// Fdiv = ( pclk / 16 ) / UART_BAUDRATE ; /*baud rate */
|
|
||||||
// LPC_UART1->DLM = Fdiv / 256;
|
|
||||||
// LPC_UART1->DLL = Fdiv % 256;
|
|
||||||
// LPC_UART1->LCR = 0x03; /* DLAB = 0 */
|
|
||||||
// LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
|
||||||
// }
|
|
||||||
//
|
|
||||||
// /* Ensure a clean start, no data in either TX or RX FIFO. */
|
|
||||||
// while (( LPC_UART->LSR & (LSR_THRE|LSR_TEMT)) != (LSR_THRE|LSR_TEMT) );
|
|
||||||
// while ( LPC_UART->LSR & LSR_RDR )
|
|
||||||
// {
|
|
||||||
// Fdiv = LPC_UART->RBR; /* Dump data from RX FIFO */
|
|
||||||
// }
|
|
||||||
// LPC_UART->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART interrupt */
|
|
||||||
|
|
||||||
return RT_EOK;
|
return RT_EOK;
|
||||||
}
|
}
|
||||||
|
|
||||||
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
|
static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
|
||||||
{
|
{
|
||||||
// RT_ASSERT(dev != RT_NULL);
|
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
|
||||||
// if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
|
||||||
// {
|
RT_ASSERT(dev != RT_NULL);
|
||||||
// /* Enable the UART Interrupt */
|
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||||
// NVIC_EnableIRQ(UART_IRQn);
|
{
|
||||||
// }
|
/* Enable the UART Interrupt */
|
||||||
|
NVIC_EnableIRQ( uart->UART_IRQn );
|
||||||
|
}
|
||||||
|
|
||||||
return RT_EOK;
|
return RT_EOK;
|
||||||
}
|
}
|
||||||
|
|
||||||
static rt_err_t rt_uart_close(rt_device_t dev)
|
static rt_err_t rt_uart_close(rt_device_t dev)
|
||||||
{
|
{
|
||||||
// RT_ASSERT(dev != RT_NULL);
|
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
|
||||||
// if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
|
||||||
// {
|
RT_ASSERT(dev != RT_NULL);
|
||||||
// /* Disable the UART Interrupt */
|
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||||
// NVIC_DisableIRQ(UART_IRQn);
|
{
|
||||||
// }
|
/* Disable the UART Interrupt */
|
||||||
|
NVIC_DisableIRQ( uart->UART_IRQn );
|
||||||
|
}
|
||||||
|
|
||||||
return RT_EOK;
|
return RT_EOK;
|
||||||
}
|
}
|
||||||
|
|
||||||
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
||||||
{
|
{
|
||||||
// rt_uint8_t* ptr;
|
rt_uint8_t* ptr;
|
||||||
// struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
|
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
|
||||||
// RT_ASSERT(uart != RT_NULL);
|
RT_ASSERT(uart != RT_NULL);
|
||||||
//
|
|
||||||
// /* point to buffer */
|
/* point to buffer */
|
||||||
// ptr = (rt_uint8_t*) buffer;
|
ptr = (rt_uint8_t*) buffer;
|
||||||
// if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
if (dev->flag & RT_DEVICE_FLAG_INT_RX)
|
||||||
// {
|
{
|
||||||
// while (size)
|
while (size)
|
||||||
// {
|
{
|
||||||
// /* interrupt receive */
|
/* interrupt receive */
|
||||||
// rt_base_t level;
|
rt_base_t level;
|
||||||
//
|
|
||||||
// /* disable interrupt */
|
/* disable interrupt */
|
||||||
// level = rt_hw_interrupt_disable();
|
level = rt_hw_interrupt_disable();
|
||||||
// if (uart->read_index != uart->save_index)
|
if (uart->read_index != uart->save_index)
|
||||||
// {
|
{
|
||||||
// *ptr = uart->rx_buffer[uart->read_index];
|
*ptr = uart->rx_buffer[uart->read_index];
|
||||||
//
|
|
||||||
// uart->read_index ++;
|
uart->read_index ++;
|
||||||
// if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
|
if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
|
||||||
// uart->read_index = 0;
|
uart->read_index = 0;
|
||||||
// }
|
}
|
||||||
// else
|
else
|
||||||
// {
|
{
|
||||||
// /* no data in rx buffer */
|
/* no data in rx buffer */
|
||||||
//
|
|
||||||
// /* enable interrupt */
|
/* enable interrupt */
|
||||||
// rt_hw_interrupt_enable(level);
|
rt_hw_interrupt_enable(level);
|
||||||
// break;
|
break;
|
||||||
// }
|
}
|
||||||
//
|
|
||||||
// /* enable interrupt */
|
/* enable interrupt */
|
||||||
// rt_hw_interrupt_enable(level);
|
rt_hw_interrupt_enable(level);
|
||||||
//
|
|
||||||
// ptr ++;
|
ptr ++;
|
||||||
// size --;
|
size --;
|
||||||
// }
|
}
|
||||||
//
|
|
||||||
// return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
|
||||||
// }
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
||||||
{
|
{
|
||||||
// rt_uint32_t i = size;
|
|
||||||
// char *ptr;
|
|
||||||
// ptr = (char*)buffer;
|
|
||||||
//
|
|
||||||
// while(i)
|
|
||||||
// {
|
|
||||||
// UART_SendByte((LPC_UART_TypeDef*)LPC_UART1,*ptr);
|
|
||||||
// i--;
|
|
||||||
// ptr++;
|
|
||||||
// }
|
|
||||||
// return size;
|
|
||||||
|
|
||||||
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
|
struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
|
||||||
char *ptr;
|
char *ptr;
|
||||||
ptr = (char*)buffer;
|
ptr = (char*)buffer;
|
||||||
@ -282,9 +306,11 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer
|
|||||||
{
|
{
|
||||||
if (*ptr == '\n')
|
if (*ptr == '\n')
|
||||||
{
|
{
|
||||||
|
while (!(uart->UART->LSR & UART_LSR_THRE));
|
||||||
UART_SendByte( uart->UART,'\r');
|
UART_SendByte( uart->UART,'\r');
|
||||||
}
|
}
|
||||||
|
|
||||||
|
while (!(uart->UART->LSR & UART_LSR_THRE));
|
||||||
UART_SendByte( uart->UART,*ptr);
|
UART_SendByte( uart->UART,*ptr);
|
||||||
ptr ++;
|
ptr ++;
|
||||||
size --;
|
size --;
|
||||||
@ -292,44 +318,45 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer
|
|||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
while ( size != 0 )
|
UART_Send( uart->UART, (uint8_t *)buffer, size, BLOCKING);
|
||||||
{
|
}
|
||||||
UART_SendByte( uart->UART,*ptr);
|
|
||||||
ptr++;
|
|
||||||
size--;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return (rt_size_t) ptr - (rt_size_t) buffer;
|
return (rt_size_t) ptr - (rt_size_t) buffer;
|
||||||
}
|
}
|
||||||
|
|
||||||
void rt_hw_uart_init(void)
|
void rt_hw_uart_init(void)
|
||||||
{
|
{
|
||||||
#ifdef RT_USING_UART1
|
|
||||||
struct rt_uart_lpc* uart;
|
struct rt_uart_lpc* uart;
|
||||||
UART_CFG_Type UART_ConfigStruct;
|
|
||||||
|
|
||||||
/*
|
#ifdef RT_USING_UART0
|
||||||
* Initialize UART1 pin connect
|
/* get uart device */
|
||||||
* P3.16: TXD
|
uart = &uart0_device;
|
||||||
* P3.17: RXD
|
uart0_device.UART = LPC_UART0;
|
||||||
*/
|
uart0_device.UART_IRQn = UART0_IRQn;
|
||||||
PINSEL_ConfigPin(3, 16, 3);
|
|
||||||
PINSEL_ConfigPin(3, 17, 3);
|
|
||||||
|
|
||||||
UART_ConfigStruct.Baud_rate = 115200;
|
/* device initialization */
|
||||||
UART_ConfigStruct.Databits = UART_DATABIT_8;
|
uart->parent.type = RT_Device_Class_Char;
|
||||||
UART_ConfigStruct.Parity = UART_PARITY_NONE;
|
rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
|
||||||
UART_ConfigStruct.Stopbits = UART_STOPBIT_1;
|
uart->read_index = uart->save_index = 0;
|
||||||
|
|
||||||
UART_Init((LPC_UART_TypeDef *)LPC_UART1,&UART_ConfigStruct);
|
/* device interface */
|
||||||
|
uart->parent.init = rt_uart_init;
|
||||||
|
uart->parent.open = rt_uart_open;
|
||||||
|
uart->parent.close = rt_uart_close;
|
||||||
|
uart->parent.read = rt_uart_read;
|
||||||
|
uart->parent.write = rt_uart_write;
|
||||||
|
uart->parent.control = RT_NULL;
|
||||||
|
uart->parent.user_data = RT_NULL;
|
||||||
|
|
||||||
// Enable UART Transmit
|
rt_device_register(&uart->parent,
|
||||||
UART_TxCmd((LPC_UART_TypeDef *)LPC_UART1, ENABLE);
|
"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef RT_USING_UART1
|
||||||
/* get uart device */
|
/* get uart device */
|
||||||
uart = &uart1_device;
|
uart = &uart1_device;
|
||||||
uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
|
uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
|
||||||
|
uart1_device.UART_IRQn = UART1_IRQn;
|
||||||
|
|
||||||
/* device initialization */
|
/* device initialization */
|
||||||
uart->parent.type = RT_Device_Class_Char;
|
uart->parent.type = RT_Device_Class_Char;
|
||||||
|
@ -85,12 +85,12 @@ void rtthread_startup(void)
|
|||||||
|
|
||||||
#ifdef RT_USING_HEAP
|
#ifdef RT_USING_HEAP
|
||||||
#ifdef __CC_ARM
|
#ifdef __CC_ARM
|
||||||
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x10008000);
|
rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)(0x10000000 + 1024*64));
|
||||||
#elif __ICCARM__
|
#elif __ICCARM__
|
||||||
rt_system_heap_init(__segment_end("HEAP"), (void*)0x10008000);
|
rt_system_heap_init(__segment_end("HEAP"), (void*)(0x10000000 + 1024*64));
|
||||||
#else
|
#else
|
||||||
/* init memory system */
|
/* init memory system */
|
||||||
rt_system_heap_init((void*)&__bss_end, (void*)0x10008000);
|
rt_system_heap_init((void*)&__bss_end, (void*)(0x10000000 + 1024*64));
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
Loading…
x
Reference in New Issue
Block a user