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update STM32F4xx_StdPeriph_Driver to V1.1.0.

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git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1959 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong 2012-02-18 03:53:33 +00:00
parent 4362efb322
commit 017e673c17
67 changed files with 419 additions and 326 deletions
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161
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Include/stm32f4xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F4xx devices.
@ -105,12 +105,12 @@
#endif /* HSI_VALUE */
/**
* @brief STM32F4XX Standard Peripherals Library version number V1.0.0RC1
* @brief STM32F4XX Standard Peripherals Library version number V1.0.0
*/
#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4XX_STDPERIPH_VERSION_RC (0x01) /*!< [7:0] release candidate */
#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
|(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
@ -127,10 +127,16 @@
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#if !defined (__FPU_PRESENT)
#define __FPU_PRESENT 1 /*!< FPU present */
#endif /* __FPU_PRESENT */
/**
* @brief STM32F4XX Interrupt Number Definition, according to the selected device
@ -656,7 +662,7 @@ typedef struct
__IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
__IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x24-0x28 */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
} GPIO_TypeDef;
/**
@ -999,16 +1005,25 @@ typedef struct
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
@ -1074,7 +1089,6 @@ typedef struct
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000)
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
@ -4444,40 +4458,74 @@ typedef struct
#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001)
#define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002)
#define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004)
#define GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008)
#define GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010)
#define GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020)
#define GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040)
#define GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080)
#define GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100)
#define GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200)
#define GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400)
#define GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800)
#define GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000)
#define GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000)
#define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000)
#define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000)
#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001)
#define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002)
#define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004)
#define GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008)
#define GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010)
#define GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020)
#define GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040)
#define GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080)
#define GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100)
#define GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200)
#define GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400)
#define GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800)
#define GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000)
#define GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000)
#define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000)
#define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000)
#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
@ -4698,7 +4746,9 @@ typedef struct
#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
#define PWR_CR_FPDS ((uint16_t)0x0200) /*!< Flash power down in Stop mode */
#define PWR_CR_PMODE ((uint16_t)0x4000) /*!< Performance mode */
#define PWR_CR_VOS ((uint16_t)0x4000) /*!< Regulator voltage scaling output selection */
/* Legacy define */
#define PWR_CR_PMODE PWR_CR_VOS
/******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
@ -4707,7 +4757,9 @@ typedef struct
#define PWR_CSR_BRR ((uint16_t)0x0008) /*!< Backup regulator ready */
#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */
#define PWR_CSR_BRE ((uint16_t)0x0200) /*!< Backup regulator enable */
#define PWR_CSR_REGRDY ((uint16_t)0x4000) /*!< Main Regulator ready */
#define PWR_CSR_VOSRDY ((uint16_t)0x4000) /*!< Regulator voltage scaling output selection ready */
/* Legacy define */
#define PWR_CSR_REGRDY PWR_CSR_VOSRDY
/******************************************************************************/
/* */
@ -4836,7 +4888,7 @@ typedef struct
#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E00) /*!< HCLK divided by 16 */
#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
/*!< RTCPRE configuration */
#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
@ -4947,11 +4999,13 @@ typedef struct
#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
#define RCC_APB2RSTR_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
/* Old SPI1RST bit definition, maintained for legacy purpose */
#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
@ -4965,6 +5019,7 @@ typedef struct
#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
@ -5777,7 +5832,9 @@ typedef struct
#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_MII_RMII ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */
@ -6447,12 +6504,14 @@ typedef struct
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP ((uint32_t)0x00001000)
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
/* Old IWDGSTOP bit definition, maintained for legacy purpose */
#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
/******************** Bit definition for DBGMCU_APB2_FZ register ************/
#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)

4
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Include/system_stm32f4xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
******************************************************************************
* @attention

10
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Release_Notes.html
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File diff suppressed because one or more lines are too long

9
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TASKING/cstart_thumb2.asm
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@ -14,6 +14,8 @@
.weak __get_argcv
.extern __argcvbuf
.weak __argcvbuf
;;.extern __init_hardware
.extern SystemInit
.if @defined('__PROF_ENABLE__')
@ -39,12 +41,6 @@ _Next:
ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table
mov sp,r1
;FPU settings
ldr r0, =0xE000ED88 ; Enable CP10,CP11
ldr r1,[r0]
orr r1,r1,#(0xF << 20)
str r1,[r0]
; Call the clock system intitialization function.
bl SystemInit
@ -84,6 +80,7 @@ clear:
done:
.if @defined('__POSIX__')
;; posix stack buffer for system upbringing

13
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f4xx.s
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@ -2,15 +2,15 @@
******************************************************************************
* @file startup_stm32f4xx.s
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief STM32F4xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3220F-EVAL board to be used as data memory (optional,
* STM324xG-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
@ -93,13 +93,6 @@ LoopFillZerobss:
cmp r2, r3
bcc FillZerobss
/*FPU settings*/
ldr r0, =0xE000ED88 // Enable CP10,CP11
ldr r1,[r0]
orr r1,r1,#(0xF << 20)
str r1,[r0]
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */

13
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s
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@ -1,13 +1,16 @@
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f4xx.s
;* Author : MCD Application Team
;* Version : V1.0.0RC1
;* Date : 25-August-2011
;* Version : V1.0.0
;* Date : 30-September-2011
;* Description : STM32F4xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
@ -169,12 +172,6 @@ Reset_Handler PROC
IMPORT SystemInit
IMPORT __main
;FPU settings
LDR R0, =0xE000ED88 ; Enable CP10,CP11
LDR R1,[R0]
ORR R1,R1,#(0xF << 20)
STR R1,[R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__main

12
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f4xx.s
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@ -2,15 +2,15 @@
******************************************************************************
* @file startup_stm32f4xx.s
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief STM32F4xx Devices vector table for RIDE7 toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Configure the clock system and the external SRAM mounted on
* STM3220F-EVAL board to be used as data memory (optional,
* STM324xG-EVAL board to be used as data memory (optional,
* to be enabled by user)
* - Branches to main in the C library (which eventually
* calls main()).
@ -93,12 +93,6 @@ LoopFillZerobss:
cmp r2, r3
bcc FillZerobss
/* FPU settings */
ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
ldr r1,[r0]
orr r1,r1,#(0xF << 20)
str r1,[r0]
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call the application's entry point.*/

17
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s
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@ -1,14 +1,19 @@
;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f4xx.s
;* Author : MCD Application Team
;* Version : V1.0.0RC1
;* Date : 25-August-2011
;* Description : STM32F40x devices vector table for EWARM toolchain.
;* Version : V1.0.0
;* Date : 30-September-2011
;* Description : STM32F4xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
@ -160,12 +165,6 @@ __vector_table
SECTION .text:CODE:REORDER(2)
Reset_Handler
;FPU settings
LDR R0, =0xE000ED88 ; Enable CP10,CP11
LDR R1,[R0]
ORR R1,R1,#(0xF << 20)
STR R1,[R0]
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start

27
bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices,
* and is generated by the clock configuration tool
@ -74,7 +74,7 @@
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* High Performance mode | Enabled
* Main regulator output voltage | Scale1 mode
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
@ -132,6 +132,7 @@
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM324xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
@ -141,8 +142,9 @@
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 336
@ -153,6 +155,8 @@
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
/******************************************************************************/
/**
* @}
*/
@ -203,6 +207,11 @@ static void SetSysClock(void);
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
@ -358,9 +367,9 @@ static void SetSysClock(void)
if (HSEStatus == (uint32_t)0x01)
{
/* Enable high performance mode, System frequency up to 168 MHz */
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_PMODE;
PWR->CR |= PWR_CR_VOS;
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
@ -496,14 +505,14 @@ void SystemInit_ExtMemCtl(void)
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400;
FSMC_Bank1->BTCR[3] = 0x00010603;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 3;//0;
p.FSMC_AddressSetupTime = 3;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 6;//4;
p.FSMC_DataSetupTime = 6;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;

6
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html
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4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file misc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_adc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_can.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_crc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the Cryptographic
* processor(CRYP) firmware library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dac.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dbgmcu.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
******************************************************************************
* @attention

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dcmi.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DCMI firmware library.
******************************************************************************
* @attention

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_exti.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_fsmc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_gpio.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the GPIO firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the HASH
* firmware library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_i2c.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_iwdg.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************

30
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_pwr.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
@ -88,6 +88,14 @@
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
/** @defgroup PWR_Regulator_Voltage_Scale
* @{
*/
#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x00004000)
#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00000000)
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2))
/**
* @}
*/
@ -100,11 +108,19 @@
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_BRR PWR_CSR_BRR
#define PWR_FLAG_REGRDY PWR_CSR_REGRDY
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
/** @defgroup PWR_Flag_Legacy
* @{
*/
#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
/**
* @}
*/
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
((FLAG) == PWR_FLAG_REGRDY))
((FLAG) == PWR_FLAG_VOSRDY))
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
/**
@ -131,11 +147,11 @@ void PWR_PVDCmd(FunctionalState NewState);
/* WakeUp pins configuration functions ****************************************/
void PWR_WakeUpPinCmd(FunctionalState NewState);
/* Backup Regulator configuration functions ***********************************/
/* Main and Backup Regulators configuration functions *************************/
void PWR_BackupRegulatorCmd(FunctionalState NewState);
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
/* Performance Mode and FLASH Power Down configuration functions **************/
void PWR_HighPerformanceModeCmd(FunctionalState NewState);
/* FLASH Power Down configuration functions ***********************************/
void PWR_FlashPowerDownCmd(FunctionalState NewState);
/* Low Power modes configuration functions ************************************/

7
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rcc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the RCC firmware library.
******************************************************************************
* @attention
@ -263,6 +263,7 @@ typedef struct
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
@ -271,7 +272,7 @@ typedef struct
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
/**

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rng.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the Random
* Number Generator(RNG) firmware library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rtc.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_sdio.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************

6
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_spi.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
******************************************************************************
@ -129,7 +129,7 @@ typedef struct
((PERIPH) == I2S3ext))
#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \
((PERIPH) == I2S2ext))
((PERIPH) == I2S3ext))
/** @defgroup SPI_data_direction

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_syscfg.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_tim.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************

17
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_usart.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
@ -238,13 +238,23 @@ typedef struct
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE ((uint16_t)0x0360)
#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
/** @defgroup USART_Legacy
* @{
*/
#define USART_IT_ORE USART_IT_ORE_ER
/**
* @}
*/
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
@ -253,6 +263,7 @@ typedef struct
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \
((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_wwdg.h
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file misc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
*

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_adc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* - Initialization and Configuration (in addition to ADC multi mode

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_can.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller area network (CAN) peripheral:
* - Initialization and Configuration

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_crc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @attention

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Cryptographic processor (CRYP) peripheral:
* - Initialization and Configuration functions

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp_aes.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using AES in ECB/CBC/CTR modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp_des.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using DES in ECB/CBC modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_tdes.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp_tdes.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to encrypt and decrypt an
* input message using TDES in ECB/CBC modes .
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dac.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dac.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* - DAC channels configuration: trigger, output buffer, data format

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dbgmcu.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @attention

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dcmi.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the DCMI peripheral:
* - Initialization and Configuration

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* - Initialization and Configuration

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_exti.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* - Initialization and Configuration

14
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* - FLASH Interface configuration
@ -119,13 +119,13 @@
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
|***************|****************|****************|*****************|*****************|*****************************+
| | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V |
@ -134,6 +134,8 @@
|---------------|----------------|----------------|-----------------|-----------------|-----------------------------|
|PSIZE[1:0] | 10 | 01 | 00 | 11 |
+-------------------------------------------------------------------------------------------------------------------+
@note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz.
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
- void FLASH_PrefetchBufferCmd(FunctionalState NewState)
- void FLASH_InstructionCacheCmd(FunctionalState NewState)

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_fsmc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the FSMC peripheral:
* - Interface with SRAM, PSRAM, NOR and OneNAND memories

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_gpio.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* - Initialization and Configuration

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the HASH / HMAC Processor (HASH) peripheral:
* - Initialization and Configuration functions

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash_md5.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to compute the HASH MD5 and
* HMAC MD5 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash_sha1.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides high level functions to compute the HASH SHA1 and
* HMAC SHA1 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_i2c.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Inter-integrated circuit (I2C)
* - Initialization and Configuration

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_iwdg.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral:
* - Prescaler and Counter configuration

80
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
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@ -2,15 +2,15 @@
******************************************************************************
* @file stm32f4xx_pwr.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* - Backup Domain Access
* - PVD configuration
* - WakeUp pin configuration
* - Backup Regulator configuration
* - Performance Mode and FLASH Power Down configuration functions
* - Main and Backup Regulators configuration
* - FLASH Power Down configuration
* - Low Power modes configuration
* - Flags management
*
@ -249,12 +249,12 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
* @}
*/
/** @defgroup PWR_Group4 Backup Regulator configuration functions
* @brief Backup Regulator configuration functions
/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
* @brief Main and Backup Regulators configuration functions
*
@verbatim
===============================================================================
Backup Regulator configuration functions
Main and Backup Regulators configuration functions
===============================================================================
- The backup domain includes 4 Kbytes of backup SRAM accessible only from the
@ -275,6 +275,16 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
a protection level change from level 1 to level 0 is requested.
Refer to the description of Read protection (RDP) in the Flash programming manual.
- The main internal regulator can be configured to have a tradeoff between performance
and power consumption when the device does not operate at the maximum frequency.
This is done through PWR_MainRegulatorModeConfig() function which configure VOS bit
in PWR_CR register:
- When this bit is set (Regulator voltage output Scale 1 mode selected) the System
frequency can go up to 168 MHz.
- When this bit is reset (Regulator voltage output Scale 2 mode selected) the System
frequency can go up to 144 MHz.
Refer to the datasheets for more details.
@endverbatim
* @{
*/
@ -293,24 +303,45 @@ void PWR_BackupRegulatorCmd(FunctionalState NewState)
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
}
/**
* @brief Configures the main internal regulator output voltage.
* @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
* @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode,
* System frequency up to 168 MHz.
* @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode,
* System frequency up to 144 MHz.
* @retval None
*/
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage));
if (PWR_Regulator_Voltage == PWR_Regulator_Voltage_Scale2)
{
PWR->CR &= ~PWR_Regulator_Voltage_Scale1;
}
else
{
PWR->CR |= PWR_Regulator_Voltage_Scale1;
}
}
/**
* @}
*/
/** @defgroup PWR_Group5 Performance Mode and FLASH Power Down configuration functions
* @brief Performance Mode and FLASH Power Down configuration functions
/** @defgroup PWR_Group5 FLASH Power Down configuration functions
* @brief FLASH Power Down configuration functions
*
@verbatim
===============================================================================
Performance Mode and FLASH Power Down configuration functions
FLASH Power Down configuration functions
===============================================================================
- By setting the PMODE bit in the PWR_CR register by using the PWR_HighPerformanceModeCmd()
function, the high performance mode is selected and the high voltage regulator
minimum value should be around 1.2V.
When reset, the low performance mode is selected and the low voltage regulator
minimum value should be around 1.08V.
- By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
function, the Flash memory also enters power down mode when the device enters
Stop mode. When the Flash memory is in power down mode, an additional startup
@ -320,20 +351,6 @@ void PWR_BackupRegulatorCmd(FunctionalState NewState)
* @{
*/
/**
* @brief Enables or disables the high performance mode.
* @param NewState: new state of the performance mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void PWR_HighPerformanceModeCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
*(__IO uint32_t *) CR_PMODE_BB = (uint32_t)NewState;
}
/**
* @brief Enables or disables the Flash Power Down in STOP mode.
* @param NewState: new state of the Flash power mode.
@ -581,7 +598,8 @@ void PWR_EnterSTANDBYMode(void)
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_REGRDY: Main regulator ready flag.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @retval The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)

27
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rcc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Reset and clock control (RCC) peripheral:
* - Internal/external clocks, PLL, CSS and MCO configuration
@ -156,7 +156,7 @@ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6
4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
5. PLL (clocked by HSI or HSE), featuring two different output clocks:
- The first output is used to generate the high speed system clock (up to 120 MHz)
- The first output is used to generate the high speed system clock (up to 168 MHz)
- The second output is used to generate the clock for the USB OTG FS (48 MHz),
the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
@ -421,7 +421,7 @@ void RCC_LSICmd(FunctionalState NewState)
*
* @param PLLP: specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
* @note You have to set the PLLP parameter correctly to not exceed 120 MHz on
* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
* the System clock frequency.
*
* @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
@ -466,7 +466,6 @@ void RCC_PLLCmd(FunctionalState NewState)
/**
* @brief Configures the PLLI2S clock multiplication and division factors.
*
* @note PLLI2S is available only in Silicon RevisionB and RevisionY.
* @note This function must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* RCC_PLLConfig function )
@ -494,7 +493,6 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
/**
* @brief Enables or disables the PLLI2S.
* @note PLLI2S is available only in RevisionB and RevisionY
* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
* @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
* @retval None
@ -635,7 +633,7 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
to 48. This clock is derived of the main PLL through PLLQ divider.
- IWDG clock which is always the LSI clock.
2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz.
Depending on the device voltage range, the maximum frequency should be
adapted accordingly:
+-------------------------------------------------------------------------------------+
@ -652,15 +650,16 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
+-------------------------------------------------------------------------------------+
@note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz.
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
@endverbatim
* @{
@ -1036,10 +1035,7 @@ void RCC_BackupResetCmd(FunctionalState NewState)
/**
* @brief Configures the I2S clock source (I2SCLK).
*
* @note This function must be called before enabling the I2S APB clock.
* @note This function applies only to Silicon RevisionB and RevisionY.
*
* @param RCC_I2SCLKSource: specifies the I2S clock source.
* This parameter can be one of the following values:
* @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
@ -1073,6 +1069,7 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
* @arg RCC_AHB1Periph_GPIOI: GPIOI clock
* @arg RCC_AHB1Periph_CRC: CRC clock
* @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock
* @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
* @arg RCC_AHB1Periph_DMA1: DMA1 clock
* @arg RCC_AHB1Periph_DMA2: DMA2 clock
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rng.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
* - Initialization and Configuration

5
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rtc.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* - Initialization
@ -1048,7 +1048,6 @@ void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);
}
}

4
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_sdio.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Secure digital input/output interface (SDIO)
* peripheral:

10
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_spi.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Serial peripheral interface (SPI):
* - Initialization and Configuration
@ -125,10 +125,6 @@
* ...
*
*
*
* @note This driver supports only the I2S clock scheme available in Silicon
* RevisionB and RevisionY.
*
* @note In I2S mode: if an external clock is used as source clock for the I2S,
* then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should
* be enabled and set to the value of the source clock frequency (in Hz).
@ -368,7 +364,7 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
packetlength = 2;
}
/* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */
/* Get I2S source Clock frequency ****************************************/
/* If an external I2S clock has to be used, this define should be set
in the project configuration or in the stm32f4xx_conf.h file */

11
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_syscfg.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the SYSCFG peripheral.
*
* @verbatim
@ -97,13 +97,6 @@ void SYSCFG_DeInit(void)
* @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
*
* @note In remap mode, the FSMC addressing is fixed to the remap address area only
* (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not
* accessible. The FSMC remap function must be disabled to allows addressing
* other memory devices through the FSMC and/or to access FSMC control
* registers.
*
* @retval None
*/
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)

11
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_tim.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the TIM peripheral:
* - TimeBase management
@ -482,10 +482,10 @@ void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
* @param TIMx: where x can be 1 to 14 to select the TIM peripheral.
* @param TIM_UpdateSource: specifies the Update source.
* This parameter can be one of the following values:
* @arg TIM_UpdateSource_Regular: Source of update is the counter
* @arg TIM_UpdateSource_Global: Source of update is the counter
* overflow/underflow or the setting of UG bit, or an update
* generation through the slave mode controller.
* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
* @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow.
* @retval None
*/
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
@ -1908,6 +1908,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
{
/* TI2 Configuration */
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
@ -1917,6 +1918,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
{
/* TI3 Configuration */
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);
@ -1926,6 +1928,7 @@ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
else
{
/* TI4 Configuration */
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
TIM_ICInitStruct->TIM_ICSelection,
TIM_ICInitStruct->TIM_ICFilter);

7
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_usart.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Universal synchronous asynchronous receiver
* transmitter (USART):
@ -1345,7 +1345,8 @@ void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
* @arg USART_IT_TC: Transmission complete interrupt
* @arg USART_IT_RXNE: Receive Data register not empty interrupt
* @arg USART_IT_IDLE: Idle line detection interrupt
* @arg USART_IT_ORE: OverRun Error interrupt
* @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set
* @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set
* @arg USART_IT_NE: Noise Error interrupt
* @arg USART_IT_FE: Framing Error interrupt
* @arg USART_IT_PE: Parity Error interrupt

6
bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_wwdg.c
* @author MCD Application Team
* @version V1.0.0RC1
* @date 25-August-2011
* @version V1.0.0
* @date 30-September-2011
* @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral:
* - Prescaler, Refresh window and Counter configuration
@ -35,7 +35,7 @@
* WWDG counter clock = PCLK1 / Prescaler
* WWDG timeout = (WWDG counter clock) * (counter value)
*
* Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms
* Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
*
* ===================================================================
* How to use this driver