support GCC compiler for LM3S platform
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@235 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
qiuyiuestc
parent
5696b4853a
commit
017d2b7662
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@ -0,0 +1,15 @@
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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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LR_IROM1 0x00000000 0x00040000 { ; load region size_region
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ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 0x20000000 0x00010000 { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -21,8 +21,6 @@ CPU='lm3s'
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#EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
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#EXEC_PATH = 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
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PLATFORM = 'armcc'
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PLATFORM = 'armcc'
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EXEC_PATH = 'E:/Keil'
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EXEC_PATH = 'E:/Keil'
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#PLATFORM = 'iar'
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#EXEC_PATH = 'E:/Program Files/IAR Systems/Embedded Workbench 5.4/'
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BUILD = 'debug'
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BUILD = 'debug'
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if PLATFORM == 'gcc':
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if PLATFORM == 'gcc':
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@ -40,7 +38,7 @@ if PLATFORM == 'gcc':
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DEVICE = ' -mcpu=cortex-m3 -mthumb'
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DEVICE = ' -mcpu=cortex-m3 -mthumb'
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CFLAGS = DEVICE + ' -Dsourcerygxx' + ' -DRT_USING_MINILIBC'
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CFLAGS = DEVICE + ' -Dsourcerygxx' + ' -DRT_USING_MINILIBC'
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AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
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AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
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LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lm3s.map,-cref,-u,ResetISR -T lm3s_rom.ld'
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LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lm3s.map,-cref,-u,Reset_Handler -T lm3s_rom.ld'
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CPATH = ''
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CPATH = ''
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LPATH = ''
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LPATH = ''
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@ -65,7 +63,7 @@ elif PLATFORM == 'armcc':
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DEVICE = ' --device DARMSTM'
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DEVICE = ' --device DARMSTM'
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CFLAGS = DEVICE + ' --apcs=interwork'
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CFLAGS = DEVICE + ' --apcs=interwork'
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AFLAGS = DEVICE
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AFLAGS = DEVICE
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LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct'
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LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-lm3s.map --scatter lm3s_rom.sct'
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CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
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CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
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LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
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LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
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@ -82,21 +80,3 @@ elif PLATFORM == 'armcc':
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if RT_USING_FINSH:
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if RT_USING_FINSH:
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LFLAGS += ' --keep __fsym_* --keep __vsym_*'
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LFLAGS += ' --keep __fsym_* --keep __vsym_*'
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POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
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POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
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elif PLATFORM == 'iar':
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# toolchains
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CC = 'iccarm'
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AS = 'iasmarm'
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AR = 'iarchive'
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LINK = 'ilinkarm'
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TARGET_EXT = 'out'
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DEVICE = ' --cpu DARMSTM --thumb'
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CFLAGS = ''
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AFLAGS = ''
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LFLAGS = ' --config stm32f10x_flash.icf'
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EXEC_PATH += '/arm/bin/'
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RT_USING_MINILIBC = False
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POST_ACTION = ''
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@ -0,0 +1,31 @@
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/*
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* File : fault_gcc.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2009, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-10-11 Bernard first version
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*/
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.cpu cortex-m3
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.fpu softvfp
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.syntax unified
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.thumb
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.text
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.global rt_hw_hard_fault
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.type rt_hw_hard_fault, %function
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rt_hw_hard_fault:
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/* get current context */
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MRS r0, psp /* get fault thread stack pointer */
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PUSH {lr}
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BL rt_hw_hard_fault_exception
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POP {lr}
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ORR lr, lr, #0x04
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BX lr
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@ -1,242 +0,0 @@
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//*****************************************************************************
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//
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// startup.c - Boot code for Stellaris.
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//
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// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved.
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//
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 2752 of the Stellaris Peripheral Driver Library.
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Forward declaration of the default fault handlers.
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//
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//*****************************************************************************
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void ResetISR(void);
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static void NmiSR(void);
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static void FaultISR(void);
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static void IntDefaultHandler(void);
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//*****************************************************************************
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//
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// The entry point for the application.
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//
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//*****************************************************************************
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extern int main(void);
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//*****************************************************************************
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//
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// Reserve space for the system stack.
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//
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//*****************************************************************************
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#ifndef STACK_SIZE
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#define STACK_SIZE 64
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#endif
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static unsigned long pulStack[STACK_SIZE];
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//*****************************************************************************
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//
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// The minimal vector table for a Cortex M3. Note that the proper constructs
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// must be placed on this to ensure that it ends up at physical address
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// 0x0000.0000.
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//
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//*****************************************************************************
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__attribute__ ((section(".isr_vector")))
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void (* const g_pfnVectors[])(void) =
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{
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(void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
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// The initial stack pointer
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ResetISR, // The reset handler
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NmiSR, // The NMI handler
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FaultISR, // The hard fault handler
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IntDefaultHandler, // The MPU fault handler
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IntDefaultHandler, // The bus fault handler
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IntDefaultHandler, // The usage fault handler
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // SVCall handler
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IntDefaultHandler, // Debug monitor handler
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0, // Reserved
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IntDefaultHandler, // The PendSV handler
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IntDefaultHandler, // The SysTick handler
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IntDefaultHandler, // GPIO Port A
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IntDefaultHandler, // GPIO Port B
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IntDefaultHandler, // GPIO Port C
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IntDefaultHandler, // GPIO Port D
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IntDefaultHandler, // GPIO Port E
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IntDefaultHandler, // UART0 Rx and Tx
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IntDefaultHandler, // UART1 Rx and Tx
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IntDefaultHandler, // SSI Rx and Tx
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IntDefaultHandler, // I2C Master and Slave
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IntDefaultHandler, // PWM Fault
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IntDefaultHandler, // PWM Generator 0
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IntDefaultHandler, // PWM Generator 1
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IntDefaultHandler, // PWM Generator 2
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IntDefaultHandler, // Quadrature Encoder
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IntDefaultHandler, // ADC Sequence 0
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IntDefaultHandler, // ADC Sequence 1
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IntDefaultHandler, // ADC Sequence 2
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IntDefaultHandler, // ADC Sequence 3
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IntDefaultHandler, // Watchdog timer
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IntDefaultHandler, // Timer 0 subtimer A
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IntDefaultHandler, // Timer 0 subtimer B
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IntDefaultHandler, // Timer 1 subtimer A
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IntDefaultHandler, // Timer 1 subtimer B
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IntDefaultHandler, // Timer 2 subtimer A
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IntDefaultHandler, // Timer 2 subtimer B
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IntDefaultHandler, // Analog Comparator 0
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IntDefaultHandler, // Analog Comparator 1
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IntDefaultHandler, // Analog Comparator 2
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IntDefaultHandler, // System Control (PLL, OSC, BO)
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IntDefaultHandler, // FLASH Control
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IntDefaultHandler, // GPIO Port F
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IntDefaultHandler, // GPIO Port G
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IntDefaultHandler, // GPIO Port H
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IntDefaultHandler, // UART2 Rx and Tx
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IntDefaultHandler, // SSI1 Rx and Tx
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IntDefaultHandler, // Timer 3 subtimer A
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IntDefaultHandler, // Timer 3 subtimer B
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IntDefaultHandler, // I2C1 Master and Slave
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IntDefaultHandler, // Quadrature Encoder 1
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IntDefaultHandler, // CAN0
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IntDefaultHandler, // CAN1
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IntDefaultHandler, // CAN2
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IntDefaultHandler, // Ethernet
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IntDefaultHandler, // Hibernate
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IntDefaultHandler, // USB0
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IntDefaultHandler, // PWM Generator 3
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IntDefaultHandler, // uDMA Software Transfer
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IntDefaultHandler // uDMA Error
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};
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//*****************************************************************************
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//
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// The following are constructs created by the linker, indicating where the
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// the "data" and "bss" segments reside in memory. The initializers for the
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// for the "data" segment resides immediately following the "text" segment.
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//
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//*****************************************************************************
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extern unsigned long _etext;
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extern unsigned long _sdata;
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extern unsigned long _edata;
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extern unsigned long _sbss;
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extern unsigned long _ebss;
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//*****************************************************************************
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//
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// This is the code that gets called when the processor first starts execution
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// following a reset event. Only the absolutely necessary set is performed,
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// after which the application supplied main() routine is called. Any fancy
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// actions (such as making decisions based on the reset cause register, and
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// resetting the bits in that register) are left solely in the hands of the
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// application.
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//
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//*****************************************************************************
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void
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ResetISR(void)
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{
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unsigned long *pulSrc, *pulDest;
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//
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// Copy the data segment initializers from flash to SRAM.
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//
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pulSrc = &_etext;
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for(pulDest = &_sdata; pulDest < &_edata; )
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{
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*pulDest++ = *pulSrc++;
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}
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//
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// Zero fill the bss segment. This is done with inline assembly since this
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// will clear the value of pulDest if it is not kept in a register.
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//
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__asm(" ldr r0, =_sbss\n"
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" ldr r1, =_ebss\n"
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" mov r2, #0\n"
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" .thumb_func\n"
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"zero_loop:\n"
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" cmp r0, r1\n"
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" it lt\n"
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" strlt r2, [r0], #4\n"
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" blt zero_loop");
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//
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// Call the application's entry point.
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//
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main();
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}
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||||||
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//*****************************************************************************
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//
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// This is the code that gets called when the processor receives a NMI. This
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// simply enters an infinite loop, preserving the system state for examination
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||||||
// by a debugger.
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//
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//*****************************************************************************
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static void
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NmiSR(void)
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{
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//
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// Enter an infinite loop.
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//
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while(1)
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||||||
{
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||||||
}
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}
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//*****************************************************************************
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|
||||||
//
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||||||
// This is the code that gets called when the processor receives a fault
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||||||
// interrupt. This simply enters an infinite loop, preserving the system state
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||||||
// for examination by a debugger.
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||||||
//
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//*****************************************************************************
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static void
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FaultISR(void)
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||||||
{
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||||||
//
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// Enter an infinite loop.
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||||||
//
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while(1)
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{
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||||||
}
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}
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||||||
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||||||
//*****************************************************************************
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|
||||||
//
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|
||||||
// This is the code that gets called when the processor receives an unexpected
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||||||
// interrupt. This simply enters an infinite loop, preserving the system state
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||||||
// for examination by a debugger.
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|
||||||
//
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//*****************************************************************************
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||||||
static void
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IntDefaultHandler(void)
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|
||||||
{
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||||||
//
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||||||
// Go into an infinite loop.
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|
||||||
//
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|
||||||
while(1)
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|
||||||
{
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|
||||||
}
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}
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@ -0,0 +1,195 @@
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/**
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******************************************************************************
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* @file startup_stm32f10x_hd.s
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* @author MCD Application Team
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* @version V3.1.2
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* @date 09/28/2009
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* @brief STM32F10x High Density Devices vector table for RIDE7 toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address,
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* - Configure external SRAM mounted on STM3210E-EVAL board
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||||||
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* to be used as data memory (optional, to be enabled by user)
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||||||
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* - Branches to main in the C library (which eventually
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||||||
|
* calls main()).
|
||||||
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* After Reset the Cortex-M3 processor is in Thread mode,
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||||||
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* priority is Privileged, and the Stack is set to Main.
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||||||
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******************************************************************************
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||||||
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* @copy
|
||||||
|
*
|
||||||
|
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||||
|
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||||
|
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||||
|
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||||
|
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||||
|
*
|
||||||
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
|
||||||
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*/
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.section .bss.init
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.equ Stack_Size, 0x00000200
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.space Stack_Size
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||||||
|
Initial_spTop:
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m3
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
// .equ Initial_spTop, 0x20000200
|
||||||
|
.equ BootRAM, 0xF1E0F85F
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
/* restore original stack pointer */
|
||||||
|
LDR r0, =Initial_spTop
|
||||||
|
MSR msp, r0
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
movs r1, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyDataInit
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b LoopFillZerobss
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word Initial_spTop
|
||||||
|
.word Reset_Handler
|
||||||
|
.word Default_Handler //NMI_Handler
|
||||||
|
.word rt_hw_hard_fault
|
||||||
|
.word Default_Handler //MemManage_Handler
|
||||||
|
.word Default_Handler //BusFault_Handler
|
||||||
|
.word Default_Handler //UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word Default_Handler //SVC_Handler
|
||||||
|
.word Default_Handler //DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word rt_hw_pend_sv
|
||||||
|
.word rt_hw_timer_handler
|
||||||
|
.word Default_Handler // GPIO Port A
|
||||||
|
.word Default_Handler // GPIO Port B
|
||||||
|
.word Default_Handler // GPIO Port C
|
||||||
|
.word Default_Handler // GPIO Port D
|
||||||
|
.word Default_Handler // GPIO Port E
|
||||||
|
.word rt_hw_uart_isr_1 // UART0 Rx and Tx
|
||||||
|
.word Default_Handler // UART1 Rx and Tx
|
||||||
|
.word Default_Handler // SSI Rx and Tx
|
||||||
|
.word Default_Handler // I2C Master and Slave
|
||||||
|
.word Default_Handler // PWM Fault
|
||||||
|
.word Default_Handler // PWM Generator 0
|
||||||
|
.word Default_Handler // PWM Generator 1
|
||||||
|
.word Default_Handler // PWM Generator 2
|
||||||
|
.word Default_Handler // Quadrature Encoder
|
||||||
|
.word Default_Handler // ADC Sequence 0
|
||||||
|
.word Default_Handler // ADC Sequence 1
|
||||||
|
.word Default_Handler // ADC Sequence 2
|
||||||
|
.word Default_Handler // ADC Sequence 3
|
||||||
|
.word Default_Handler // Watchdog timer
|
||||||
|
.word Default_Handler // Timer 0 subtimer A
|
||||||
|
.word Default_Handler // Timer 0 subtimer B
|
||||||
|
.word Default_Handler // Timer 1 subtimer A
|
||||||
|
.word Default_Handler // Timer 1 subtimer B
|
||||||
|
.word Default_Handler // Timer 2 subtimer A
|
||||||
|
.word Default_Handler // Timer 2 subtimer B
|
||||||
|
.word Default_Handler // Analog Comparator 0
|
||||||
|
.word Default_Handler // Analog Comparator 1
|
||||||
|
.word Default_Handler // Analog Comparator 2
|
||||||
|
.word Default_Handler // System Control (PLL, OSC,
|
||||||
|
.word Default_Handler // FLASH Control
|
||||||
|
.word Default_Handler // GPIO Port F
|
||||||
|
.word Default_Handler // GPIO Port G
|
||||||
|
.word Default_Handler // GPIO Port H
|
||||||
|
.word Default_Handler // UART2 Rx and Tx
|
||||||
|
.word Default_Handler // SSI1 Rx and Tx
|
||||||
|
.word Default_Handler // Timer 3 subtimer A
|
||||||
|
.word Default_Handler // Timer 3 subtimer B
|
||||||
|
.word Default_Handler // I2C1 Master and Slave
|
||||||
|
.word Default_Handler // Quadrature Encoder 1
|
||||||
|
.word Default_Handler // CAN0
|
||||||
|
.word Default_Handler // CAN1
|
||||||
|
.word Default_Handler // CAN2
|
||||||
|
.word luminaryif_isr // Ethernet
|
||||||
|
.word Default_Handler // Hibernate
|
||||||
|
.word Default_Handler // USB0
|
||||||
|
.word Default_Handler // PWM Generator 3
|
||||||
|
.word Default_Handler // uDMA Software Transfer
|
||||||
|
.word Default_Handler // uDMA Error
|
||||||
Loading…
Reference in New Issue