2021-09-02 09:55:07 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-08-20 Abbcc first version
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtthread.h>
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#include <apm32f10x.h>
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#include "apm32f10x_gpio.h"
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#include "apm32f10x_rcm.h"
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#include "apm32f10x_misc.h"
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#include "apm32f10x_rcm.h"
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#include "apm32f10x_eint.h"
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#include "apm32f10x_usart.h"
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#include "drv_common.h"
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#include "drv_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define APM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
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#define APM32_FLASH_SIZE (512 * 1024)
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#define APM32_FLASH_END_ADDRESS ((uint32_t)(APM32_FLASH_START_ADRESS + APM32_FLASH_SIZE))
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/* Internal SRAM memory size[Kbytes] <6-128>, Default: 128 */
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#define APM32_SRAM_SIZE 128
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#define APM32_SRAM_END (0x20000000 + APM32_SRAM_SIZE * 1024)
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2021-12-30 03:14:07 +08:00
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#if defined(__ARMCC_VERSION)
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2021-09-02 09:55:07 +08:00
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="CSTACK"
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#define HEAP_BEGIN (__segment_end("CSTACK"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN ((void *)&__bss_end)
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#endif
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#define HEAP_END APM32_SRAM_END
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void SystemClock_Config(void);
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void apm32_usart_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __BOARD_H__ */
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