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rt-thread-official/libcpu/mips/common/exception_gcc.S

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[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2019-12-04 Jiaxun Yang Initial version
fix mips stackframe and exception
2020-08-26 12:03:01 +08:00
* 2020-07-26 lizhirui Add xtlb exception entry
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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*/
fix mips64 some bug
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#ifndef __ASSEMBLY__
#define __ASSEMBLY__
#endif
#include <mips.h>
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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.section ".exc_vectors", "ax"
.extern tlb_refill_handler
.extern cache_error_handler
.extern mips_irq_handle
/* 0x0 - TLB refill handler */
.global tlb_refill_exception
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.type tlb_refill_exception,@function
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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ebase_start:
tlb_refill_exception:
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b _general_exception_handler
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop
fix mips stackframe and exception
2020-08-26 12:03:01 +08:00
/* 0x080 - XTLB refill handler */
.org ebase_start + 0x080
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b _general_exception_handler
fix mips stackframe and exception
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nop
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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/* 0x100 - Cache error handler */
.org ebase_start + 0x100
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j cache_error_handler
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop
/* 0x180 - Exception/Interrupt handler */
.global general_exception
[asm] 解决tab和空格混用的问题
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.type general_exception,@function
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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.org ebase_start + 0x180
general_exception:
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b _general_exception_handler
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop
/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
.global irq_exception
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.type irq_exception,@function
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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.org ebase_start + 0x200
irq_exception:
[asm] 解决tab和空格混用的问题
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b _general_exception_handler
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop
/* general exception handler */
_general_exception_handler:
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.set noreorder
PTR_LA k0, mips_irq_handle
jr k0
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop
[asm] 解决tab和空格混用的问题
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.set reorder
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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/* interrupt handler */
_irq_handler:
[asm] 解决tab和空格混用的问题
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.set noreorder
PTR_LA k0, mips_irq_handle
jr k0
[libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
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nop
[asm] 解决tab和空格混用的问题
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.set reorder