2018-09-20 23:18:14 +08:00
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/*
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2022-05-19 14:06:35 +08:00
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2018-09-20 23:18:14 +08:00
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*
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2018-10-21 14:45:29 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2018-09-20 23:18:14 +08:00
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*
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* Change Logs:
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* Date Author Notes
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2019-06-12 15:01:12 +08:00
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* 2017-08-08 Yang the first version
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* 2018-03-24 LaiYiKeTang add hardware iic
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* 2019-04-22 tyustli add imxrt series support
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*
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2018-09-20 23:18:14 +08:00
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*/
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#include <rtthread.h>
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2019-06-12 15:01:12 +08:00
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#ifdef BSP_USING_I2C
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#define LOG_TAG "drv.i2c"
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#include <drv_log.h>
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2022-01-26 00:54:03 +08:00
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#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) && !defined(BSP_USING_I2C5)&& !defined(BSP_USING_I2C6)
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2019-06-12 15:01:12 +08:00
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#error "Please define at least one BSP_USING_I2Cx"
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#endif
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2018-09-20 23:18:14 +08:00
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#include <rtdevice.h>
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#include "fsl_lpi2c.h"
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#include "drv_i2c.h"
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2019-06-12 15:01:12 +08:00
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struct imxrt_i2c_bus
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{
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struct rt_i2c_bus_device parent;
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LPI2C_Type *I2C;
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struct rt_i2c_msg *msg;
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rt_uint32_t msg_cnt;
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volatile rt_uint32_t msg_ptr;
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volatile rt_uint32_t dptr;
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char *device_name;
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2022-01-26 12:24:09 +08:00
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#ifdef SOC_IMXRT1170_SERIES
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clock_root_t clock_root;
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#endif
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2019-06-12 15:01:12 +08:00
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};
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2018-09-20 23:18:14 +08:00
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2019-06-12 15:01:12 +08:00
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#if defined (BSP_USING_I2C1)
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2018-09-20 23:18:14 +08:00
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#define I2C1BUS_NAME "i2c1"
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2019-06-12 15:01:12 +08:00
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#endif /*BSP_USING_I2C1*/
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#if defined (BSP_USING_I2C2)
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2018-09-20 23:18:14 +08:00
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#define I2C2BUS_NAME "i2c2"
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2019-06-12 15:01:12 +08:00
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#endif /*BSP_USING_I2C2*/
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#if !defined (MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/
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#if defined (BSP_USING_I2C3)
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2018-09-20 23:18:14 +08:00
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#define I2C3BUS_NAME "i2c3"
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2019-06-12 15:01:12 +08:00
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#endif /*BSP_USING_I2C3*/
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#if defined (BSP_USING_I2C4)
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2018-09-20 23:18:14 +08:00
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#define I2C4BUS_NAME "i2c4"
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2019-06-12 15:01:12 +08:00
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#endif /*BSP_USING_I2C4*/
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2022-01-26 00:54:03 +08:00
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#if defined (BSP_USING_I2C5)
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#define I2C5BUS_NAME "i2c5"
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#endif /*BSP_USING_I2C5*/
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#if defined (BSP_USING_I2C6)
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#define I2C6BUS_NAME "i2c6"
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#endif /*BSP_USING_I2C6*/
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2019-06-12 15:01:12 +08:00
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#endif /* MIMXRT1015_SERIES */
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2018-09-20 23:18:14 +08:00
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2022-01-26 00:54:03 +08:00
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/* Select USB1 PLL (360 MHz) as master lpi2c clock source */
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#define LPI2C_CLOCK_SOURCE_SELECT (1U)
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2022-01-26 12:24:09 +08:00
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#ifdef SOC_IMXRT1170_SERIES
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2022-01-26 00:54:03 +08:00
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/* Clock divider for master lpi2c clock source */
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#define LPI2C_CLOCK_SOURCE_DIVIDER (12U)
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#else
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#define LPI2C_CLOCK_SOURCE_DIVIDER (0U)
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2018-09-20 23:18:14 +08:00
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/* Get frequency of lpi2c clock */
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2022-01-26 00:54:03 +08:00
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#define LPI2C_CLOCK_FREQUENCY ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (LPI2C_CLOCK_SOURCE_DIVIDER + 1U))
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2018-09-20 23:18:14 +08:00
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2022-01-26 00:54:03 +08:00
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#endif
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2019-06-12 15:01:12 +08:00
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#ifdef BSP_USING_I2C1
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static struct imxrt_i2c_bus lpi2c1 =
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2018-09-20 23:18:14 +08:00
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{
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.I2C = LPI2C1,
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.device_name = I2C1BUS_NAME,
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};
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#endif /* RT_USING_HW_I2C1 */
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2019-06-12 15:01:12 +08:00
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#ifdef BSP_USING_I2C2
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static struct imxrt_i2c_bus lpi2c2 =
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2018-09-20 23:18:14 +08:00
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{
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.I2C = LPI2C2,
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.device_name = I2C2BUS_NAME,
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};
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#endif /* RT_USING_HW_I2C2 */
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2019-06-12 15:01:12 +08:00
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#if !defined (MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/
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#ifdef BSP_USING_I2C3
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static struct imxrt_i2c_bus lpi2c3 =
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2018-09-20 23:18:14 +08:00
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{
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.I2C = LPI2C3,
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.device_name = I2C3BUS_NAME,
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};
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#endif /* RT_USING_HW_I2C3 */
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2019-06-12 15:01:12 +08:00
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#ifdef BSP_USING_I2C4
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static struct imxrt_i2c_bus lpi2c4 =
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2018-09-20 23:18:14 +08:00
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{
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.I2C = LPI2C4,
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.device_name = I2C4BUS_NAME,
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};
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#endif /* RT_USING_HW_I2C4 */
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2022-01-26 00:54:03 +08:00
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#ifdef BSP_USING_I2C5
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static struct imxrt_i2c_bus lpi2c5 =
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{
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.I2C = LPI2C5,
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.device_name = I2C5BUS_NAME,
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};
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#endif /* RT_USING_HW_I2C5 */
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#ifdef BSP_USING_I2C6
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static struct imxrt_i2c_bus lpi2c6 =
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{
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.I2C = LPI2C6,
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.device_name = I2C6BUS_NAME,
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};
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#endif /* RT_USING_HW_I2C6 */
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2019-06-12 15:01:12 +08:00
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#endif /* MIMXRT1015_SERIES */
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2022-01-26 00:54:03 +08:00
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#if (defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || defined(BSP_USING_I2C4) ||defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6))
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2018-09-20 23:18:14 +08:00
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static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num);
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static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num);
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static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus,
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rt_uint32_t,
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rt_uint32_t);
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static const struct rt_i2c_bus_device_ops imxrt_i2c_ops =
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{
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2019-06-12 15:01:12 +08:00
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.master_xfer = imxrt_i2c_mst_xfer,
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.slave_xfer = imxrt_i2c_slv_xfer,
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.i2c_bus_control = imxrt_i2c_bus_control,
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2018-09-20 23:18:14 +08:00
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};
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2019-06-12 15:01:12 +08:00
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static rt_err_t imxrt_lpi2c_configure(struct imxrt_i2c_bus *bus, lpi2c_master_config_t *cfg)
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2018-09-20 23:18:14 +08:00
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{
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RT_ASSERT(bus != RT_NULL);
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RT_ASSERT(cfg != RT_NULL);
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bus->parent.ops = &imxrt_i2c_ops;
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2022-01-26 12:24:09 +08:00
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#ifdef SOC_IMXRT1170_SERIES
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clock_root_config_t rootCfg = {0};
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rootCfg.mux = LPI2C_CLOCK_SOURCE_SELECT;
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rootCfg.div = LPI2C_CLOCK_SOURCE_DIVIDER + 1;
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CLOCK_SetRootClock(bus->clock_root, &rootCfg);
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volatile uint32_t freq = CLOCK_GetRootClockFreq(bus->clock_root);
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LPI2C_MasterInit(bus->I2C, cfg, freq);
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2022-01-26 00:54:03 +08:00
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#else
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2022-01-26 12:24:09 +08:00
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CLOCK_SetMux(kCLOCK_Lpi2cMux, LPI2C_CLOCK_SOURCE_SELECT);
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CLOCK_SetDiv(kCLOCK_Lpi2cDiv, LPI2C_CLOCK_SOURCE_DIVIDER);
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2018-09-20 23:18:14 +08:00
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LPI2C_MasterInit(bus->I2C, cfg, LPI2C_CLOCK_FREQUENCY);
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2022-01-26 12:24:09 +08:00
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#endif
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2018-09-20 23:18:14 +08:00
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return RT_EOK;
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}
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status_t LPI2C_MasterCheck(LPI2C_Type *base, uint32_t status)
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{
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status_t result = kStatus_Success;
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/* Check for error. These errors cause a stop to automatically be sent. We must */
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/* clear the errors before a new transfer can start. */
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status &= 0x3c00;
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if (status)
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{
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/* Select the correct error code. Ordered by severity, with bus issues first. */
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if (status & kLPI2C_MasterPinLowTimeoutFlag)
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{
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result = kStatus_LPI2C_PinLowTimeout;
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}
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else if (status & kLPI2C_MasterArbitrationLostFlag)
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{
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result = kStatus_LPI2C_ArbitrationLost;
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}
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else if (status & kLPI2C_MasterNackDetectFlag)
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{
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result = kStatus_LPI2C_Nak;
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}
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else if (status & kLPI2C_MasterFifoErrFlag)
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{
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result = kStatus_LPI2C_FifoError;
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}
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else
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{
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assert(false);
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}
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/* Clear the flags. */
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LPI2C_MasterClearStatusFlags(base, status);
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/* Reset fifos. These flags clear automatically. */
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base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
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}
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return result;
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}
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/*!
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* @brief Wait until the tx fifo all empty.
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* @param base The LPI2C peripheral base address.
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* @retval #kStatus_Success
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* @retval #kStatus_LPI2C_PinLowTimeout
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* @retval #kStatus_LPI2C_ArbitrationLost
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* @retval #kStatus_LPI2C_Nak
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* @retval #kStatus_LPI2C_FifoError
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*/
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static status_t LPI2C_MasterWaitForTxFifoAllEmpty(LPI2C_Type *base)
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{
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uint32_t status;
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size_t txCount;
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2019-06-12 15:01:12 +08:00
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2018-09-20 23:18:14 +08:00
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do
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{
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status_t result;
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/* Get the number of words in the tx fifo and compute empty slots. */
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LPI2C_MasterGetFifoCounts(base, NULL, &txCount);
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/* Check for error flags. */
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status = LPI2C_MasterGetStatusFlags(base);
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result = LPI2C_MasterCheck(base, status);
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if (result)
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{
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return result;
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}
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}
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2019-06-12 15:01:12 +08:00
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2018-09-20 23:18:14 +08:00
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while (txCount);
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2019-06-12 15:01:12 +08:00
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2018-09-20 23:18:14 +08:00
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return kStatus_Success;
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}
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static rt_size_t imxrt_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
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struct rt_i2c_msg msgs[],
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rt_uint32_t num)
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{
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2019-06-12 15:01:12 +08:00
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struct imxrt_i2c_bus *imxrt_i2c;
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2018-09-20 23:18:14 +08:00
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rt_size_t i;
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RT_ASSERT(bus != RT_NULL);
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2019-06-12 15:01:12 +08:00
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imxrt_i2c = (struct imxrt_i2c_bus *) bus;
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2018-09-20 23:18:14 +08:00
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2019-06-12 15:01:12 +08:00
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imxrt_i2c->msg = msgs;
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imxrt_i2c->msg_ptr = 0;
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imxrt_i2c->msg_cnt = num;
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imxrt_i2c->dptr = 0;
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2018-09-20 23:18:14 +08:00
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for (i = 0; i < num; i++)
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{
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2019-06-12 15:01:12 +08:00
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if (imxrt_i2c->msg[i].flags & RT_I2C_RD)
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2018-09-20 23:18:14 +08:00
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{
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2022-01-26 12:24:09 +08:00
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if ((imxrt_i2c->msg[i].flags & RT_I2C_NO_START) != RT_I2C_NO_START)
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{
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if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success)
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{
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i = 0;
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break;
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}
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while (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
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{
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}
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if (LPI2C_MasterRepeatedStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
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{
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i = 0;
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break;
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}
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}
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else
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{
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if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
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{
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i = 0;
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break;
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}
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while (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
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{
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|
}
|
|
|
|
}
|
2019-06-12 15:01:12 +08:00
|
|
|
|
2021-05-28 14:20:49 +08:00
|
|
|
if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Read) != kStatus_Success)
|
2018-09-20 23:18:14 +08:00
|
|
|
{
|
|
|
|
i = 0;
|
|
|
|
break;
|
|
|
|
}
|
2019-06-12 15:01:12 +08:00
|
|
|
|
|
|
|
while (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
|
2018-09-20 23:18:14 +08:00
|
|
|
{
|
|
|
|
}
|
2019-06-12 15:01:12 +08:00
|
|
|
|
|
|
|
if (LPI2C_MasterReceive(imxrt_i2c->I2C, imxrt_i2c->msg[i].buf, imxrt_i2c->msg[i].len) != kStatus_Success)
|
2018-09-20 23:18:14 +08:00
|
|
|
{
|
|
|
|
i = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2019-06-12 15:01:12 +08:00
|
|
|
if (LPI2C_MasterStart(imxrt_i2c->I2C, imxrt_i2c->msg[i].addr, kLPI2C_Write) != kStatus_Success)
|
2018-09-20 23:18:14 +08:00
|
|
|
{
|
|
|
|
i = 0;
|
|
|
|
break;
|
|
|
|
}
|
2022-01-26 12:24:09 +08:00
|
|
|
|
2022-05-19 14:06:35 +08:00
|
|
|
// while((LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterBusBusyFlag))
|
|
|
|
// {
|
|
|
|
// }
|
2022-01-26 00:54:03 +08:00
|
|
|
if(LPI2C_MasterWaitForTxFifoAllEmpty(imxrt_i2c->I2C) != kStatus_Success)
|
|
|
|
{
|
|
|
|
i = 0;
|
|
|
|
break;
|
|
|
|
}
|
2022-01-26 12:24:09 +08:00
|
|
|
|
|
|
|
if (LPI2C_MasterGetStatusFlags(imxrt_i2c->I2C) & kLPI2C_MasterNackDetectFlag)
|
2018-09-20 23:18:14 +08:00
|
|
|
{
|
2022-01-26 12:24:09 +08:00
|
|
|
i = 0;
|
2022-01-26 00:54:03 +08:00
|
|
|
break;
|
2018-09-20 23:18:14 +08:00
|
|
|
}
|
2019-06-12 15:01:12 +08:00
|
|
|
|
|
|
|
if (LPI2C_MasterSend(imxrt_i2c->I2C, imxrt_i2c->msg[i].buf, imxrt_i2c->msg[i].len) != kStatus_Success)
|
2018-09-20 23:18:14 +08:00
|
|
|
{
|
|
|
|
i = 0;
|
|
|
|
break;
|
|
|
|
}
|
2019-06-12 15:01:12 +08:00
|
|
|
|
|
|
|
if (LPI2C_MasterWaitForTxFifoAllEmpty(imxrt_i2c->I2C) != kStatus_Success)
|
2018-09-20 23:18:14 +08:00
|
|
|
{
|
|
|
|
i = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2022-01-26 12:24:09 +08:00
|
|
|
|
|
|
|
if (LPI2C_MasterStop(imxrt_i2c->I2C) != kStatus_Success)
|
|
|
|
{
|
|
|
|
i = 0;
|
|
|
|
}
|
|
|
|
|
2018-09-20 23:18:14 +08:00
|
|
|
}
|
|
|
|
|
2019-06-12 15:01:12 +08:00
|
|
|
imxrt_i2c->msg = RT_NULL;
|
|
|
|
imxrt_i2c->msg_ptr = 0;
|
|
|
|
imxrt_i2c->msg_cnt = 0;
|
|
|
|
imxrt_i2c->dptr = 0;
|
|
|
|
|
2018-09-20 23:18:14 +08:00
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
static rt_size_t imxrt_i2c_slv_xfer(struct rt_i2c_bus_device *bus,
|
|
|
|
struct rt_i2c_msg msgs[],
|
|
|
|
rt_uint32_t num)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
static rt_err_t imxrt_i2c_bus_control(struct rt_i2c_bus_device *bus,
|
|
|
|
rt_uint32_t cmd,
|
|
|
|
rt_uint32_t arg)
|
|
|
|
{
|
|
|
|
return RT_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int rt_hw_i2c_init(void)
|
|
|
|
{
|
|
|
|
lpi2c_master_config_t masterConfig = {0};
|
|
|
|
|
2019-06-12 15:01:12 +08:00
|
|
|
#if defined(BSP_USING_I2C1)
|
2018-09-20 23:18:14 +08:00
|
|
|
LPI2C_MasterGetDefaultConfig(&masterConfig);
|
|
|
|
#if defined(HW_I2C1_BADURATE_400kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 400000U;
|
|
|
|
#elif defined(HW_I2C1_BADURATE_100kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 100000U;
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /*HW_I2C1_BADURATE_400kHZ*/
|
2018-09-20 23:18:14 +08:00
|
|
|
imxrt_lpi2c_configure(&lpi2c1, &masterConfig);
|
|
|
|
rt_i2c_bus_device_register(&lpi2c1.parent, lpi2c1.device_name);
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* BSP_USING_I2C1 */
|
2018-09-20 23:18:14 +08:00
|
|
|
|
2019-06-12 15:01:12 +08:00
|
|
|
#if defined(BSP_USING_I2C2)
|
2018-09-20 23:18:14 +08:00
|
|
|
LPI2C_MasterGetDefaultConfig(&masterConfig);
|
|
|
|
#if defined(HW_I2C2_BADURATE_400kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 400000U;
|
|
|
|
#elif defined(HW_I2C2_BADURATE_100kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 100000U;
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* HW_I2C2_BADURATE_400kHZ */
|
2018-09-20 23:18:14 +08:00
|
|
|
imxrt_lpi2c_configure(&lpi2c2, &masterConfig);
|
|
|
|
rt_i2c_bus_device_register(&lpi2c2.parent, lpi2c2.device_name);
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* BSP_USING_I2C2 */
|
2018-09-20 23:18:14 +08:00
|
|
|
|
2019-06-12 15:01:12 +08:00
|
|
|
#if !defined(MIMXRT1015_SERIES) /* imxrt1015 only have two i2c bus*/
|
|
|
|
|
|
|
|
#if defined(BSP_USING_I2C3)
|
2018-09-20 23:18:14 +08:00
|
|
|
LPI2C_MasterGetDefaultConfig(&masterConfig);
|
|
|
|
#if defined(HW_I2C3_BADURATE_400kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 400000U;
|
|
|
|
#elif defined(HW_I2C3_BADURATE_100kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 100000U;
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* HW_I2C3_BADURATE_400kHZ */
|
2018-09-20 23:18:14 +08:00
|
|
|
imxrt_lpi2c_configure(&lpi2c3, &masterConfig);
|
|
|
|
rt_i2c_bus_device_register(&lpi2c3.parent, lpi2c3.device_name);
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* BSP_USING_I2C3 */
|
2018-09-20 23:18:14 +08:00
|
|
|
|
2019-06-12 15:01:12 +08:00
|
|
|
#if defined(BSP_USING_I2C4)
|
2018-09-20 23:18:14 +08:00
|
|
|
LPI2C_MasterGetDefaultConfig(&masterConfig);
|
|
|
|
#if defined(HW_I2C4_BADURATE_400kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 400000U;
|
|
|
|
#elif defined(HW_I2C4_BADURATE_100kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 100000U;
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* HW_I2C4_BADURATE_400kHZ */
|
2018-09-20 23:18:14 +08:00
|
|
|
imxrt_lpi2c_configure(&lpi2c4, &masterConfig);
|
|
|
|
rt_i2c_bus_device_register(&lpi2c4.parent, lpi2c4.device_name);
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* BSP_USING_I2C4 */
|
2018-09-20 23:18:14 +08:00
|
|
|
|
2022-01-26 00:54:03 +08:00
|
|
|
#if defined(BSP_USING_I2C5)
|
|
|
|
LPI2C_MasterGetDefaultConfig(&masterConfig);
|
|
|
|
#if defined(HW_I2C5_BADURATE_400kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 400000U;
|
|
|
|
#elif defined(HW_I2C5_BADURATE_100kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 100000U;
|
|
|
|
#endif /* HW_I2C5_BADURATE_400kHZ */
|
2022-01-26 12:24:09 +08:00
|
|
|
lpi2c5.clock_root = kCLOCK_Root_Lpi2c5;
|
2022-01-26 00:54:03 +08:00
|
|
|
imxrt_lpi2c_configure(&lpi2c5, &masterConfig);
|
|
|
|
rt_i2c_bus_device_register(&lpi2c5.parent, lpi2c5.device_name);
|
|
|
|
#endif /* BSP_USING_I2C5 */
|
|
|
|
|
|
|
|
#if defined(BSP_USING_I2C6)
|
|
|
|
LPI2C_MasterGetDefaultConfig(&masterConfig);
|
|
|
|
#if defined(HW_I2C6_BADURATE_400kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 400000U;
|
|
|
|
#elif defined(HW_I2C6_BADURATE_100kHZ)
|
|
|
|
masterConfig.baudRate_Hz = 100000U;
|
|
|
|
#endif /* HW_I2C6_BADURATE_400kHZ */
|
2022-01-26 12:24:09 +08:00
|
|
|
lpi2c6.clock_root = kCLOCK_Root_Lpi2c6;
|
2022-01-26 00:54:03 +08:00
|
|
|
imxrt_lpi2c_configure(&lpi2c6, &masterConfig);
|
|
|
|
rt_i2c_bus_device_register(&lpi2c6.parent, lpi2c6.device_name);
|
|
|
|
#endif /* BSP_USING_I2C6 */
|
|
|
|
|
|
|
|
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* MIMXRT1015_SERIES */
|
2018-09-20 23:18:14 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-06-12 15:01:12 +08:00
|
|
|
INIT_DEVICE_EXPORT(rt_hw_i2c_init);
|
2018-09-20 23:18:14 +08:00
|
|
|
|
2019-06-12 15:01:12 +08:00
|
|
|
#endif /* BSP_USING_I2C */
|