2023-05-11 10:25:21 +08:00
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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2023-03-20 zhangyan first version
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2024-06-16 15:42:37 +08:00
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* 2023-05-31 zhangyan improve functions
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2023-05-11 10:25:21 +08:00
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*
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*/
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2023-08-02 13:27:09 +08:00
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#include "rtconfig.h"
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2023-12-08 17:57:55 +08:00
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#include "rtdevice.h"
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#define LOG_TAG "qspi_drv"
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#include "drv_log.h"
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2023-05-11 10:25:21 +08:00
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#include <rtthread.h>
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2023-08-05 14:45:11 +08:00
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#ifdef RT_USING_SMART
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#include <ioremap.h>
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#endif
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2023-08-02 13:27:09 +08:00
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#include "drv_qspi.h"
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2023-05-11 10:25:21 +08:00
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#include "fqspi_flash.h"
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2023-08-02 13:27:09 +08:00
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#include "fiopad.h"
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2023-08-05 14:45:11 +08:00
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#include "fqspi_hw.h"
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2023-12-08 17:57:55 +08:00
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#include "fio_mux.h"
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2023-08-05 14:45:11 +08:00
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#define QSPI_ALIGNED_BYTE 4
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2023-08-02 13:27:09 +08:00
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2023-12-08 17:57:55 +08:00
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typedef struct
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2023-05-11 10:25:21 +08:00
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{
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2023-12-08 17:57:55 +08:00
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rt_uint32_t fqspi_id;
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const char *name;
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rt_uint32_t init; /* 0 is init already */
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FQspiCtrl fqspi;
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struct rt_spi_bus qspi_bus;
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} phytium_qspi_bus;
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2023-05-11 10:25:21 +08:00
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2023-08-02 13:27:09 +08:00
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rt_err_t FQspiInit(phytium_qspi_bus *phytium_qspi_bus)
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2023-05-11 10:25:21 +08:00
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{
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FError ret = FT_SUCCESS;
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2023-08-02 13:27:09 +08:00
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rt_uint32_t qspi_id = phytium_qspi_bus->fqspi_id;
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2023-11-21 17:42:23 +08:00
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FIOPadSetQspiMux(qspi_id, FQSPI_CS_0);
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FIOPadSetQspiMux(qspi_id, FQSPI_CS_1);
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2023-05-11 10:25:21 +08:00
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2023-08-02 13:27:09 +08:00
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FQspiDeInitialize(&(phytium_qspi_bus->fqspi));
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2023-11-21 17:42:23 +08:00
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2023-05-11 10:25:21 +08:00
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FQspiConfig pconfig = *FQspiLookupConfig(qspi_id);
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2023-08-02 13:27:09 +08:00
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#ifdef RT_USING_SMART
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pconfig.base_addr = (uintptr)rt_ioremap((void *)pconfig.base_addr, 0x1000);
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#endif
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2023-05-11 10:25:21 +08:00
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/* Norflash init, include reset and read flash_size */
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2023-08-02 13:27:09 +08:00
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ret = FQspiCfgInitialize(&(phytium_qspi_bus->fqspi), &pconfig);
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2023-05-11 10:25:21 +08:00
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if (FT_SUCCESS != ret)
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{
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2023-08-02 13:27:09 +08:00
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LOG_E("Qspi init failed.\n");
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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else
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{
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2024-07-22 10:33:39 +08:00
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LOG_D("Qspi init successfully.\n");
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2023-05-11 10:25:21 +08:00
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}
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/* Detect connected flash infomation */
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2023-08-02 13:27:09 +08:00
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ret = FQspiFlashDetect(&(phytium_qspi_bus->fqspi));
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2023-05-11 10:25:21 +08:00
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if (FT_SUCCESS != ret)
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{
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2023-08-02 13:27:09 +08:00
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LOG_E("Qspi flash detect failed.\n");
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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else
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{
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2024-07-22 10:33:39 +08:00
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LOG_D("Qspi flash detect successfully.\n");
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2023-05-11 10:25:21 +08:00
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}
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2024-06-16 15:42:37 +08:00
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#ifdef USING_QSPI_CHANNEL0
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phytium_qspi_bus->fqspi.config.channel = 0;
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#elif defined USING_QSPI_CHANNEL1
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phytium_qspi_bus->fqspi.config.channel = 1;
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#endif
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#ifdef RT_USING_SMART
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phytium_qspi_bus->fqspi.config.mem_start = (uintptr)rt_ioremap((void *)phytium_qspi_bus->fqspi.config.mem_start, (phytium_qspi_bus->fqspi.config.channel + 1) * (phytium_qspi_bus->fqspi.flash_size));
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#endif
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2023-05-11 10:25:21 +08:00
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return RT_EOK;
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}
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2023-11-21 17:42:23 +08:00
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#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
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void FtDumpHexByte(const u8 *ptr, u32 buflen)
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{
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u8 *buf = (u8 *)ptr;
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fsize_t i, j;
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for (i = 0; i < buflen; i += 16)
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{
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rt_kprintf("%p: ", ptr + i);
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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{
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rt_kprintf("%02X ", buf[i + j]);
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}
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else
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{
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rt_kprintf(" ");
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}
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rt_kprintf(" ");
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for (j = 0; j < 16; j++)
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if (i + j < buflen)
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{
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rt_kprintf("%c", (char)(__is_print(buf[i + j]) ? buf[i + j] : '.'));
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}
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rt_kprintf("\r\n");
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}
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}
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2023-05-11 10:25:21 +08:00
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static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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2023-08-02 13:27:09 +08:00
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phytium_qspi_bus *qspi_bus;
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2023-08-05 14:45:11 +08:00
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qspi_bus = (phytium_qspi_bus *)(struct phytium_qspi_bus *) device->bus->parent.user_data;
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2023-05-11 10:25:21 +08:00
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rt_err_t ret = RT_EOK;
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2023-08-02 13:27:09 +08:00
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ret = FQspiInit(qspi_bus);
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2023-05-11 10:25:21 +08:00
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if (RT_EOK != ret)
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{
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qspi_bus->init = RT_FALSE;
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2024-07-22 10:33:39 +08:00
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LOG_E("Qspi init failed!!!\n");
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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qspi_bus->init = RT_EOK;
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return RT_EOK;
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}
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2023-08-05 14:45:11 +08:00
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static rt_ssize_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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2023-05-11 10:25:21 +08:00
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{
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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2024-04-11 00:09:17 +08:00
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FError ret = FT_SUCCESS;
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2023-08-02 13:27:09 +08:00
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phytium_qspi_bus *qspi_bus;
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2023-05-11 10:25:21 +08:00
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struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
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2024-04-11 00:09:17 +08:00
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2023-05-11 10:25:21 +08:00
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rt_uint32_t cmd = qspi_message->instruction.content;
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rt_uint32_t flash_addr = qspi_message->address.content;
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2024-04-11 00:09:17 +08:00
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rt_uint32_t len = message->length;
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2023-08-02 13:27:09 +08:00
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2023-08-05 14:45:11 +08:00
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const void *rcvb = message->recv_buf;
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const void *sndb = message->send_buf;
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2023-05-11 10:25:21 +08:00
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2023-08-05 14:45:11 +08:00
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qspi_bus = (phytium_qspi_bus *)(struct phytium_qspi_bus *) device->bus->parent.user_data;
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2023-05-11 10:25:21 +08:00
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/*Distinguish the write mode according to different commands*/
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2023-08-02 13:27:09 +08:00
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if (cmd == FQSPI_FLASH_CMD_PP || cmd == FQSPI_FLASH_CMD_QPP || cmd == FQSPI_FLASH_CMD_4PP || cmd == FQSPI_FLASH_CMD_4QPP)
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2023-05-11 10:25:21 +08:00
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{
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ret = FQspiFlashErase(&(qspi_bus->fqspi), FQSPI_FLASH_CMD_SE, flash_addr);
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if (FT_SUCCESS != ret)
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{
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2023-08-02 13:27:09 +08:00
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LOG_E("Failed to erase mem, test result 0x%x.\r\n", ret);
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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/* write norflash data */
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2024-06-16 15:42:37 +08:00
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ret = FQspiFlashWriteData(&(qspi_bus->fqspi), cmd, flash_addr, (u8 *)message->send_buf, len);
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2023-05-11 10:25:21 +08:00
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if (FT_SUCCESS != ret)
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{
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2023-08-02 13:27:09 +08:00
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LOG_E("Failed to write mem, test result 0x%x.\r\n", ret);
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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else
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{
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2024-07-22 10:33:39 +08:00
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LOG_D("Write successfully!!!\r\n");
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2023-05-11 10:25:21 +08:00
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}
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return RT_EOK;
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}
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/*Distinguish the read mode according to different commands*/
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2023-08-02 13:27:09 +08:00
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if (cmd == FQSPI_FLASH_CMD_READ || cmd == FQSPI_FLASH_CMD_4READ || cmd == FQSPI_FLASH_CMD_FAST_READ || cmd == FQSPI_FLASH_CMD_4FAST_READ ||
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2023-11-21 17:42:23 +08:00
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cmd == FQSPI_FLASH_CMD_DUAL_READ || cmd == FQSPI_FLASH_CMD_QIOR || cmd == FQSPI_FLASH_CMD_4QIOR)
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2023-05-11 10:25:21 +08:00
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{
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ret |= FQspiFlashReadDataConfig(&(qspi_bus->fqspi), cmd);
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if (FT_SUCCESS != ret)
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{
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2024-07-22 10:33:39 +08:00
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LOG_D("Failed to config read, test result 0x%x.\r\n", ret);
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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/* read norflash data */
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2024-06-16 15:42:37 +08:00
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size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), flash_addr, (u8 *)message->recv_buf, len);
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2024-04-11 00:09:17 +08:00
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if (read_len != len)
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2023-05-11 10:25:21 +08:00
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{
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2024-07-22 10:33:39 +08:00
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LOG_E("Failed to read mem, read len = %d.\r\n", read_len);
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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else
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{
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2024-07-22 10:33:39 +08:00
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LOG_D("Read successfully!!!, read_len = %d\r\n", read_len);
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2023-05-11 10:25:21 +08:00
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}
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2023-08-02 13:27:09 +08:00
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FtDumpHexByte(message->recv_buf, read_len);
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2023-05-11 10:25:21 +08:00
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2024-04-11 00:09:17 +08:00
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return read_len;
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2023-05-11 10:25:21 +08:00
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}
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if (rcvb)
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{
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2023-08-02 13:27:09 +08:00
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if (cmd == FQSPI_FLASH_CMD_RDID || cmd == FQSPI_FLASH_CMD_RDSR1 || cmd == FQSPI_FLASH_CMD_RDSR2 || cmd == FQSPI_FLASH_CMD_RDSR3)
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2023-05-11 10:25:21 +08:00
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{
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2023-08-05 14:45:11 +08:00
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ret |= FQspiFlashSpecialInstruction(&(qspi_bus->fqspi), cmd, (u8 *)rcvb, sizeof(rcvb));
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2023-05-11 10:25:21 +08:00
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if (FT_SUCCESS != ret)
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{
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2023-08-02 13:27:09 +08:00
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LOG_E("Failed to read flash information.\n");
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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}
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2024-04-11 00:09:17 +08:00
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return 1;
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2023-05-11 10:25:21 +08:00
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}
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if (sndb)
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{
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ret |= FQspiFlashEnableWrite(&(qspi_bus->fqspi));
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if (FT_SUCCESS != ret)
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{
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2023-08-02 13:27:09 +08:00
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LOG_E("Failed to enable flash reg write.\n");
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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2023-08-05 14:45:11 +08:00
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ret |= FQspiFlashWriteReg(&(qspi_bus->fqspi), cmd, (u8 *)sndb, 1);
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2023-05-11 10:25:21 +08:00
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if (FT_SUCCESS != ret)
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{
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2023-08-02 13:27:09 +08:00
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LOG_E("Failed to write flash reg.\n");
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2023-12-08 17:57:55 +08:00
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return -RT_ERROR;
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2023-05-11 10:25:21 +08:00
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}
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2024-04-11 00:09:17 +08:00
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return 1;
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2023-05-11 10:25:21 +08:00
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}
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2024-04-11 00:09:17 +08:00
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2024-07-22 10:33:39 +08:00
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LOG_E("cmd not found!!!\r\n");
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2023-08-05 14:45:11 +08:00
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return ret;
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2023-05-11 10:25:21 +08:00
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}
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static struct rt_spi_ops phytium_qspi_ops =
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{
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.configure = phytium_qspi_configure,
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.xfer = phytium_qspi_xfer,
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};
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rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device_name)
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{
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struct rt_qspi_device *qspi_device;
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rt_err_t result = RT_EOK;
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RT_ASSERT(bus_name != RT_NULL);
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RT_ASSERT(device_name != RT_NULL);
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qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
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if (qspi_device == RT_NULL)
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{
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2023-08-02 13:27:09 +08:00
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LOG_E("Qspi bus attach device failed.");
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2023-05-11 10:25:21 +08:00
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result = RT_ENOMEM;
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goto __exit;
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}
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result = rt_spi_bus_attach_device(&(qspi_device->parent), device_name, bus_name, RT_NULL);
|
|
|
|
__exit:
|
|
|
|
if (result != RT_EOK)
|
|
|
|
{
|
|
|
|
if (qspi_device)
|
|
|
|
{
|
|
|
|
rt_free(qspi_device);
|
|
|
|
}
|
2023-08-02 13:27:09 +08:00
|
|
|
}
|
2023-08-05 14:45:11 +08:00
|
|
|
return result;
|
2023-05-11 10:25:21 +08:00
|
|
|
}
|
|
|
|
|
2023-12-08 17:57:55 +08:00
|
|
|
static int rt_qspi_init(phytium_qspi_bus *phytium_qspi)
|
2023-05-11 10:25:21 +08:00
|
|
|
{
|
|
|
|
int result = RT_EOK;
|
2023-08-02 13:27:09 +08:00
|
|
|
|
2023-12-08 17:57:55 +08:00
|
|
|
phytium_qspi->qspi_bus.parent.user_data = phytium_qspi;
|
2023-05-11 10:25:21 +08:00
|
|
|
|
2023-12-08 17:57:55 +08:00
|
|
|
if (rt_qspi_bus_register(&phytium_qspi->qspi_bus, phytium_qspi->name, &phytium_qspi_ops) == RT_EOK)
|
2023-05-11 10:25:21 +08:00
|
|
|
{
|
2024-07-22 10:33:39 +08:00
|
|
|
LOG_D("Qspi bus register successfully!!!\n");
|
2023-05-11 10:25:21 +08:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2023-08-02 13:27:09 +08:00
|
|
|
LOG_E("Qspi bus register Failed!!!\n");
|
2023-05-11 10:25:21 +08:00
|
|
|
result = -RT_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
2023-12-08 17:57:55 +08:00
|
|
|
#if defined(RT_USING_QSPI0)
|
2024-01-13 23:01:55 +08:00
|
|
|
static phytium_qspi_bus phytium_qspi0_bus;
|
2023-12-08 17:57:55 +08:00
|
|
|
#endif
|
2023-05-11 10:25:21 +08:00
|
|
|
|
2023-12-08 17:57:55 +08:00
|
|
|
int rt_hw_qspi_init(void)
|
2023-05-11 10:25:21 +08:00
|
|
|
{
|
2023-12-08 17:57:55 +08:00
|
|
|
#if defined(RT_USING_QSPI0)
|
|
|
|
phytium_qspi0_bus.name = "QSPI0";
|
|
|
|
phytium_qspi0_bus.fqspi_id = FQSPI0_ID;
|
|
|
|
rt_qspi_init(&phytium_qspi0_bus);
|
2023-05-11 10:25:21 +08:00
|
|
|
#endif
|
2023-12-08 17:57:55 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2024-03-24 09:14:37 +08:00
|
|
|
INIT_BOARD_EXPORT(rt_hw_qspi_init);
|