2022-10-20 09:40:14 +08:00
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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2022-07-13 19:56:14 +08:00
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*
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2022-10-20 09:40:14 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2022-07-13 19:56:14 +08:00
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*
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2022-10-20 09:40:14 +08:00
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* Change Logs:
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* Date Author Notes
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* 2022-10-19 Nations first version
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2022-07-13 19:56:14 +08:00
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*/
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#include "drv_i2c.h"
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#ifdef RT_USING_I2C
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#define DBG_TAG "drv.I2C"
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#ifdef RT_I2C_DEBUG
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#define DBG_LVL DBG_LOG
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#else
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#define DBG_LVL DBG_INFO
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#endif
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#include <rtdbg.h>
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#ifdef RT_USING_I2C_BITOPS
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2022-07-15 13:36:32 +08:00
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static const struct n32_soft_i2c_config soft_i2c_config[] =
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{
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#ifdef BSP_USING_I2C1
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I2C1_BUS_CONFIG,
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#endif
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2022-07-13 19:56:14 +08:00
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2022-07-15 13:36:32 +08:00
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#ifdef BSP_USING_I2C2
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I2C2_BUS_CONFIG,
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#endif
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2022-07-13 19:56:14 +08:00
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2022-07-15 13:36:32 +08:00
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#ifdef BSP_USING_I2C3
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I2C3_BUS_CONFIG,
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#endif
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2022-07-13 19:56:14 +08:00
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2022-07-15 13:36:32 +08:00
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#ifdef BSP_USING_I2C4
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I2C4_BUS_CONFIG,
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#endif
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2022-07-13 19:56:14 +08:00
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};
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2022-07-15 13:36:32 +08:00
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static struct n32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
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/**
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*\*\name n32_i2c_gpio_init
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*\*\fun Initializes the i2c pin.
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*\*\param i2c dirver class
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*\*\return none
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**/
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static void n32_i2c_gpio_init(struct n32_i2c *i2c)
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2022-07-13 19:56:14 +08:00
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{
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2022-07-15 13:36:32 +08:00
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struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)i2c->ops.data;
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rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
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rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
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2022-07-13 19:56:14 +08:00
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2022-07-15 13:36:32 +08:00
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rt_pin_write(cfg->scl, PIN_HIGH);
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rt_pin_write(cfg->sda, PIN_HIGH);
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}
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2024-04-30 08:46:12 +08:00
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static void n32_i2c_pin_init(void)
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{
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rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct n32_i2c);
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for(rt_size_t i = 0; i < obj_num; i++)
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{
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n32_i2c_gpio_init(&i2c_obj[i]);
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}
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}
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2022-07-15 13:36:32 +08:00
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/**
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*\*\name n32_set_sda
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*\*\fun sets the sda pin.
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*\*\param data config class
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*\*\param state sda pin state
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*\*\return none
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**/
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static void n32_set_sda(void *data, rt_int32_t state)
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{
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struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data;
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2022-07-13 19:56:14 +08:00
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if (state)
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{
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2022-07-15 13:36:32 +08:00
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rt_pin_write(cfg->sda, PIN_HIGH);
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2022-07-13 19:56:14 +08:00
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}
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else
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{
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2022-07-15 13:36:32 +08:00
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rt_pin_write(cfg->sda, PIN_LOW);
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2022-07-13 19:56:14 +08:00
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}
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}
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2022-07-15 13:36:32 +08:00
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/**
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*\*\name n32_set_scl
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*\*\fun sets the scl pin.
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*\*\param data config class
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*\*\param state scl pin state
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*\*\return none
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**/
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static void n32_set_scl(void *data, rt_int32_t state)
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2022-07-13 19:56:14 +08:00
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{
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2022-07-15 13:36:32 +08:00
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struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data;
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2022-07-13 19:56:14 +08:00
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if (state)
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{
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2022-07-15 13:36:32 +08:00
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rt_pin_write(cfg->scl, PIN_HIGH);
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2022-07-13 19:56:14 +08:00
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}
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else
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{
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2022-07-15 13:36:32 +08:00
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rt_pin_write(cfg->scl, PIN_LOW);
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2022-07-13 19:56:14 +08:00
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}
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}
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2022-07-15 13:36:32 +08:00
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/**
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*\*\name n32_get_sda
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*\*\fun gets the sda pin state.
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*\*\param data config class
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*\*\return sda pin state
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**/
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static rt_int32_t n32_get_sda(void *data)
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2022-07-13 19:56:14 +08:00
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{
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2022-07-15 13:36:32 +08:00
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struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data;
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return rt_pin_read(cfg->sda);
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2022-07-13 19:56:14 +08:00
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}
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2022-07-15 13:36:32 +08:00
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/**
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*\*\name n32_get_scl
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*\*\fun gets the scl pin state.
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*\*\param data config class
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*\*\return scl pin state
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**/
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static rt_int32_t n32_get_scl(void *data)
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2022-07-13 19:56:14 +08:00
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{
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2022-07-15 13:36:32 +08:00
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struct n32_soft_i2c_config* cfg = (struct n32_soft_i2c_config*)data;
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return rt_pin_read(cfg->scl);
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2022-07-13 19:56:14 +08:00
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}
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2022-07-15 13:36:32 +08:00
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/**
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*\*\name n32_udelay
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*\*\fun The time delay function.
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*\*\param us
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*\*\return none
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**/
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static void n32_udelay(rt_uint32_t us)
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2022-07-13 19:56:14 +08:00
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{
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2022-07-15 13:36:32 +08:00
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rt_uint32_t ticks;
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rt_uint32_t told, tnow, tcnt = 0;
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rt_uint32_t reload = SysTick->LOAD;
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ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
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told = SysTick->VAL;
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2022-10-20 09:40:14 +08:00
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while (1)
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2022-07-13 19:56:14 +08:00
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{
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2022-07-15 13:36:32 +08:00
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tnow = SysTick->VAL;
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2022-10-20 09:40:14 +08:00
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if (tnow != told)
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2022-07-15 13:36:32 +08:00
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{
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2022-10-20 09:40:14 +08:00
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if (tnow < told)
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2022-07-15 13:36:32 +08:00
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{
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tcnt += told - tnow;
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}
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else
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{
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tcnt += reload - tnow + told;
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}
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told = tnow;
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2022-10-20 09:40:14 +08:00
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if (tcnt >= ticks)
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2022-07-15 13:36:32 +08:00
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{
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break;
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}
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}
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2022-07-13 19:56:14 +08:00
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}
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}
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2022-07-15 13:36:32 +08:00
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static const struct rt_i2c_bit_ops n32_bit_ops_default =
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{
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.data = RT_NULL,
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2024-04-30 08:46:12 +08:00
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.pin_init = n32_i2c_pin_init,
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2022-07-15 13:36:32 +08:00
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.set_sda = n32_set_sda,
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.set_scl = n32_set_scl,
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.get_sda = n32_get_sda,
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.get_scl = n32_get_scl,
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.udelay = n32_udelay,
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.delay_us = 1,
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2024-04-30 08:46:12 +08:00
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.timeout = 100,
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.i2c_pin_init_flag = RT_FALSE
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2022-07-15 13:36:32 +08:00
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};
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/**
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*\*\name n32_i2c_bus_unlock
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*\*\fun If i2c is locked, this function will unlock it.
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*\*\param cfg
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*\*\return RT_EOK indicates successful unlock
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**/
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static rt_err_t n32_i2c_bus_unlock(const struct n32_soft_i2c_config *cfg)
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2022-07-13 19:56:14 +08:00
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{
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2022-07-15 13:36:32 +08:00
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rt_int32_t i = 0;
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2022-10-20 09:40:14 +08:00
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if (PIN_LOW == rt_pin_read(cfg->sda))
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2022-07-15 13:36:32 +08:00
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{
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2022-10-20 09:40:14 +08:00
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while (i++ < 9)
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2022-07-15 13:36:32 +08:00
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{
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rt_pin_write(cfg->scl, PIN_HIGH);
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n32_udelay(100);
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rt_pin_write(cfg->scl, PIN_LOW);
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n32_udelay(100);
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}
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}
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2022-07-13 19:56:14 +08:00
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2022-10-20 09:40:14 +08:00
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if (PIN_LOW == rt_pin_read(cfg->sda))
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2022-07-15 13:36:32 +08:00
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{
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return -RT_ERROR;
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}
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return RT_EOK;
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2022-07-13 19:56:14 +08:00
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}
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2022-07-15 13:36:32 +08:00
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#endif /* RT_USING_I2C_BITOPS */
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2022-07-13 19:56:14 +08:00
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2022-07-23 11:53:42 +08:00
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#ifdef RT_USING_HARDWARE_I2C
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2022-07-13 19:56:14 +08:00
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2022-10-20 09:40:14 +08:00
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#define I2CT_FLAG_TIMEOUT ((uint32_t)0x1000)
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#define I2CT_LONG_TIMEOUT ((uint32_t)(10 * I2CT_FLAG_TIMEOUT))
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2022-07-13 19:56:14 +08:00
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static uint32_t I2CTimeout = I2CT_LONG_TIMEOUT;
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static int rt_i2c_read(rt_uint32_t i2c_periph, rt_uint16_t slave_address, rt_uint8_t* p_buffer, rt_uint16_t data_byte)
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{
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I2CTimeout = I2CT_LONG_TIMEOUT;
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/* wait until I2C bus is idle */
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2022-10-20 09:40:14 +08:00
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while (I2C_GetFlag((I2C_Module*)i2c_periph, I2C_FLAG_BUSY))
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2022-07-13 19:56:14 +08:00
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{
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if ((I2CTimeout--) == 0)
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return 9;
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};
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I2C_ConfigAck((I2C_Module*)i2c_periph, ENABLE);
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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/** Send START condition */
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I2C_GenerateStart((I2C_Module*)i2c_periph, ENABLE);
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I2CTimeout = I2CT_LONG_TIMEOUT;
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/* wait until SBSEND bit is set */
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while (!I2C_CheckEvent((I2C_Module*)i2c_periph, I2C_EVT_MASTER_MODE_FLAG)) // EV5
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{
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if ((I2CTimeout--) == 0)
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return 10;
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};
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/* send slave address to I2C bus */
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I2C_SendAddr7bit((I2C_Module*)i2c_periph, slave_address, I2C_DIRECTION_RECV);
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2022-07-23 11:53:42 +08:00
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2022-07-13 19:56:14 +08:00
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I2CTimeout = I2CT_LONG_TIMEOUT;
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while (!I2C_CheckEvent((I2C_Module*)i2c_periph, I2C_EVT_MASTER_RXMODE_FLAG)) // EV6
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{
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if ((I2CTimeout--) == 0)
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return 6;
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};
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/* while there is data to be read */
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2022-10-20 09:40:14 +08:00
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while (data_byte)
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2022-07-13 19:56:14 +08:00
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{
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/* wait until the RBNE bit is set and clear it */
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2022-10-20 09:40:14 +08:00
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if (I2C_GetFlag((I2C_Module*)i2c_periph, I2C_FLAG_RXDATNE))
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2022-07-13 19:56:14 +08:00
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{
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/* read a byte*/
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*p_buffer = I2C_RecvData((I2C_Module*)i2c_periph);
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/* point to the next location where the byte read will be saved */
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2022-07-23 11:53:42 +08:00
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p_buffer++;
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2022-07-13 19:56:14 +08:00
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/* decrement the read bytes counter */
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data_byte--;
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2022-10-20 09:40:14 +08:00
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if (1 == data_byte)
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2022-07-13 19:56:14 +08:00
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{
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/* disable acknowledge */
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I2C_ConfigAck((I2C_Module*)i2c_periph, DISABLE);
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/* send a stop condition to I2C bus */
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I2C_GenerateStop((I2C_Module*)i2c_periph, ENABLE);
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}
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}
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}
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/* wait until the stop condition is finished */
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2022-10-20 09:40:14 +08:00
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while (I2C_GetFlag((I2C_Module*)i2c_periph, I2C_FLAG_STOPF))
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2022-07-13 19:56:14 +08:00
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{
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if ((I2CTimeout--) == 0)
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return 7;
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};
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/* enable acknowledge */
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I2C_ConfigAck((I2C_Module*)i2c_periph, ENABLE);
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I2C_ConfigNackLocation((I2C_Module*)i2c_periph,I2C_NACK_POS_CURRENT);
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return 0;
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}
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static int rt_i2c_write(rt_uint32_t i2c_periph, uint16_t slave_address, uint8_t* p_buffer, uint16_t data_byte)
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{
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uint8_t* sendBufferPtr = p_buffer;
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I2CTimeout = I2CT_LONG_TIMEOUT;
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while (I2C_GetFlag((I2C_Module*)i2c_periph, I2C_FLAG_BUSY))
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{
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|
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|
if ((I2CTimeout--) == 0)
|
|
|
|
return 4;
|
|
|
|
};
|
|
|
|
|
|
|
|
I2C_ConfigAck((I2C_Module*)i2c_periph, ENABLE);
|
|
|
|
I2C_GenerateStart((I2C_Module*)i2c_periph, ENABLE);
|
|
|
|
I2CTimeout = I2CT_LONG_TIMEOUT;
|
|
|
|
while (!I2C_CheckEvent((I2C_Module*)i2c_periph, I2C_EVT_MASTER_MODE_FLAG)) // EV5
|
|
|
|
{
|
|
|
|
if ((I2CTimeout--) == 0)
|
|
|
|
return 5;
|
|
|
|
};
|
|
|
|
|
|
|
|
I2C_SendAddr7bit((I2C_Module*)i2c_periph, slave_address, I2C_DIRECTION_SEND);
|
|
|
|
I2CTimeout = I2CT_LONG_TIMEOUT;
|
|
|
|
while (!I2C_CheckEvent((I2C_Module*)i2c_periph, I2C_EVT_MASTER_TXMODE_FLAG)) // EV6
|
|
|
|
{
|
|
|
|
if ((I2CTimeout--) == 0)
|
|
|
|
return 6;
|
|
|
|
};
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
/* send data */
|
2022-07-13 19:56:14 +08:00
|
|
|
while (data_byte-- > 0)
|
|
|
|
{
|
|
|
|
I2C_SendData((I2C_Module*)i2c_periph, *sendBufferPtr++);
|
|
|
|
I2CTimeout = I2CT_LONG_TIMEOUT;
|
|
|
|
while (!I2C_CheckEvent((I2C_Module*)i2c_periph, I2C_EVT_MASTER_DATA_SENDING)) // EV8
|
|
|
|
{
|
|
|
|
if ((I2CTimeout--) == 0)
|
|
|
|
return 7;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
I2CTimeout = I2CT_LONG_TIMEOUT;
|
|
|
|
while (!I2C_CheckEvent((I2C_Module*)i2c_periph, I2C_EVT_MASTER_DATA_SENDED)) // EV8-2
|
|
|
|
{
|
|
|
|
if ((I2CTimeout--) == 0)
|
|
|
|
return 8;
|
|
|
|
};
|
|
|
|
I2C_GenerateStop((I2C_Module*)i2c_periph, ENABLE);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
2023-02-06 07:35:33 +08:00
|
|
|
static rt_ssize_t rt_i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
|
2022-07-13 19:56:14 +08:00
|
|
|
{
|
|
|
|
struct rt_i2c_msg *msg;
|
|
|
|
rt_uint32_t i;
|
2023-03-17 12:12:16 +08:00
|
|
|
rt_err_t ret = -RT_ERROR;
|
2022-07-13 19:56:14 +08:00
|
|
|
|
|
|
|
struct rt_i2c_bus *rt_i2c = (struct rt_i2c_bus *)bus;
|
|
|
|
|
|
|
|
for (i = 0; i < num; i++)
|
|
|
|
{
|
|
|
|
msg = &msgs[i];
|
|
|
|
|
|
|
|
if (msg->flags & RT_I2C_RD)
|
|
|
|
{
|
|
|
|
if (rt_i2c_read(rt_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0)
|
|
|
|
{
|
|
|
|
LOG_E("i2c bus write failed,i2c bus stop!");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
if (rt_i2c_write(rt_i2c->i2c_periph, msg->addr, msg->buf, msg->len) != 0)
|
|
|
|
{
|
|
|
|
LOG_E("i2c bus write failed,i2c bus stop!");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2022-07-23 11:53:42 +08:00
|
|
|
|
2022-07-13 19:56:14 +08:00
|
|
|
ret = i;
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
out:
|
|
|
|
LOG_E("send stop condition\n");
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct rt_i2c_bus_device_ops i2c_ops =
|
2022-07-23 11:53:42 +08:00
|
|
|
{
|
2022-07-13 19:56:14 +08:00
|
|
|
rt_i2c_xfer,
|
|
|
|
RT_NULL,
|
|
|
|
RT_NULL
|
|
|
|
};
|
|
|
|
|
2022-07-15 13:36:32 +08:00
|
|
|
#endif /* RT_USING_HARDWARE_I2C */
|
2022-07-13 19:56:14 +08:00
|
|
|
|
|
|
|
int rt_hw_i2c_init(void)
|
|
|
|
{
|
|
|
|
#ifdef RT_USING_I2C_BITOPS
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct n32_i2c);
|
2022-07-15 13:36:32 +08:00
|
|
|
rt_err_t result;
|
|
|
|
|
2024-04-30 08:46:12 +08:00
|
|
|
for(rt_size_t i = 0; i < obj_num; i++)
|
2022-07-15 13:36:32 +08:00
|
|
|
{
|
|
|
|
i2c_obj[i].ops = n32_bit_ops_default;
|
|
|
|
i2c_obj[i].ops.data = (void*)&soft_i2c_config[i];
|
2023-12-28 16:57:28 +08:00
|
|
|
i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops;
|
2022-07-13 19:56:14 +08:00
|
|
|
|
2023-12-28 16:57:28 +08:00
|
|
|
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name);
|
2022-07-13 19:56:14 +08:00
|
|
|
|
2022-07-15 13:36:32 +08:00
|
|
|
RT_ASSERT(result == RT_EOK);
|
|
|
|
n32_i2c_bus_unlock(&soft_i2c_config[i]);
|
2022-07-13 19:56:14 +08:00
|
|
|
|
2022-07-15 13:36:32 +08:00
|
|
|
rt_kprintf("software simulation %s init done, pin scl: %d, pin sda %d",
|
|
|
|
soft_i2c_config[i].bus_name,
|
|
|
|
soft_i2c_config[i].scl,
|
|
|
|
soft_i2c_config[i].sda);
|
|
|
|
}
|
|
|
|
#endif /* RT_USING_I2C_BITOPS */
|
2022-07-23 11:53:42 +08:00
|
|
|
|
2022-07-15 13:36:32 +08:00
|
|
|
#ifdef RT_USING_HARDWARE_I2C
|
2022-07-13 19:56:14 +08:00
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_InitType GPIO_InitStructure;
|
|
|
|
I2C_InitType I2C_InitStructure;
|
2022-07-13 19:56:14 +08:00
|
|
|
#ifdef BSP_USING_I2C1
|
|
|
|
#define I2C1_SPEED 400000
|
|
|
|
|
|
|
|
static struct rt_i2c_bus i2c_bus1;
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
|
|
|
|
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE);
|
|
|
|
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_I2C1, ENABLE);
|
|
|
|
|
|
|
|
GPIO_InitStruct(&GPIO_InitStructure);
|
2022-07-13 19:56:14 +08:00
|
|
|
/* connect PB8 to I2C1_SCL, PB9 to I2C1_SDA */
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_8 | GPIO_PIN_9;
|
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
|
|
|
|
GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
|
2022-07-23 11:53:42 +08:00
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_ConfigPinRemap(GPIO_RMP_I2C1, ENABLE);
|
|
|
|
#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
|
|
|
|
/* Enable I2C clock */
|
2022-07-13 19:56:14 +08:00
|
|
|
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_I2C1, ENABLE);
|
2022-10-20 09:40:14 +08:00
|
|
|
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE);
|
|
|
|
|
|
|
|
GPIO_InitStruct(&GPIO_InitStructure);
|
|
|
|
/* Confige I2C1_SCL(PB8) and I2C1_SDA(PB9) */
|
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_8 | GPIO_PIN_9;
|
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
|
|
|
|
GPIO_InitStructure.GPIO_Pull = GPIO_Pull_Up;
|
|
|
|
GPIO_InitStructure.GPIO_Alternate = GPIO_AF4_I2C1;
|
|
|
|
GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
|
|
|
|
#endif
|
2022-07-23 11:53:42 +08:00
|
|
|
|
2022-07-13 19:56:14 +08:00
|
|
|
I2C_DeInit(I2C1);
|
|
|
|
I2C_InitStructure.BusMode = I2C_BUSMODE_I2C;
|
|
|
|
I2C_InitStructure.FmDutyCycle = I2C_FMDUTYCYCLE_2;
|
|
|
|
I2C_InitStructure.OwnAddr1 = 0xff;
|
|
|
|
I2C_InitStructure.AckEnable = I2C_ACKEN;
|
|
|
|
I2C_InitStructure.AddrMode = I2C_ADDR_MODE_7BIT;
|
|
|
|
I2C_InitStructure.ClkSpeed = I2C1_SPEED; // 400000 400K
|
|
|
|
|
|
|
|
I2C_Init(I2C1, &I2C_InitStructure);
|
|
|
|
|
|
|
|
rt_memset((void *)&i2c_bus1, 0, sizeof(struct rt_i2c_bus));
|
|
|
|
i2c_bus1.parent.ops = &i2c_ops;
|
|
|
|
i2c_bus1.i2c_periph = (rt_uint32_t)I2C1;
|
|
|
|
rt_i2c_bus_device_register(&i2c_bus1.parent, "i2c1");
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef BSP_USING_I2C2
|
|
|
|
#define I2C2_SPEED 100000
|
|
|
|
|
|
|
|
static struct rt_i2c_bus i2c_bus2;
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
|
|
|
|
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB, ENABLE);
|
2022-07-13 19:56:14 +08:00
|
|
|
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_I2C2, ENABLE);
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_InitStruct(&GPIO_InitStructure);
|
2022-07-13 19:56:14 +08:00
|
|
|
/* connect PB10 to I2C2_SCL, PB11 to I2C2_SDA */
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_10 | GPIO_PIN_11;
|
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
|
|
|
|
GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
|
|
|
|
#elif defined(SOC_N32L43X) || defined(SOC_N32L40X) || defined(SOC_N32G43X)
|
|
|
|
/* Enable I2C clock */
|
|
|
|
RCC_EnableAPB1PeriphClk(RCC_APB1_PERIPH_I2C2, ENABLE);
|
|
|
|
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOB | RCC_APB2_PERIPH_AFIO, ENABLE);
|
|
|
|
|
|
|
|
GPIO_InitStruct(&GPIO_InitStructure);
|
|
|
|
/* Confige I2C1_SCL(PB10) and I2C1_SDA(PB11) */
|
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_10 | GPIO_PIN_11;
|
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
|
|
|
|
GPIO_InitStructure.GPIO_Pull = GPIO_Pull_Up;
|
|
|
|
GPIO_InitStructure.GPIO_Alternate = GPIO_AF6_I2C2;
|
|
|
|
GPIO_InitPeripheral(GPIOB, &GPIO_InitStructure);
|
|
|
|
#endif
|
2022-07-13 19:56:14 +08:00
|
|
|
|
|
|
|
I2C_DeInit(I2C2);
|
|
|
|
I2C_InitStructure.BusMode = I2C_BUSMODE_I2C;
|
|
|
|
I2C_InitStructure.FmDutyCycle = I2C_FMDUTYCYCLE_2;
|
|
|
|
I2C_InitStructure.OwnAddr1 = 0xff;
|
|
|
|
I2C_InitStructure.AckEnable = I2C_ACKEN;
|
|
|
|
I2C_InitStructure.AddrMode = I2C_ADDR_MODE_7BIT;
|
|
|
|
I2C_InitStructure.ClkSpeed = I2C2_SPEED; // 100000 100K
|
|
|
|
|
|
|
|
I2C_Init(I2C2, &I2C_InitStructure);
|
|
|
|
|
|
|
|
rt_memset((void *)&i2c_bus2, 0, sizeof(struct rt_i2c_bus));
|
|
|
|
i2c_bus2.parent.ops = &i2c_ops;
|
|
|
|
i2c_bus2.i2c_periph = (rt_uint32_t)I2C2;
|
|
|
|
rt_i2c_bus_device_register(&i2c_bus2.parent, "i2c2");
|
|
|
|
#endif
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
#if defined(SOC_N32G45X) || defined(SOC_N32WB452)
|
2022-07-13 19:56:14 +08:00
|
|
|
#ifdef BSP_USING_I2C3
|
|
|
|
#define I2C3_SPEED 100000
|
|
|
|
|
|
|
|
static struct rt_i2c_bus i2c_bus3;
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
|
2022-07-13 19:56:14 +08:00
|
|
|
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_I2C3, ENABLE);
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_InitStruct(&GPIO_InitStructure);
|
2022-07-13 19:56:14 +08:00
|
|
|
/* connect PC0 to I2C3_SCL, PC1 to I2C3_SDA */
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1;
|
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
|
|
|
|
GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure);
|
2022-07-23 11:53:42 +08:00
|
|
|
|
2022-07-13 19:56:14 +08:00
|
|
|
I2C_DeInit(I2C3);
|
|
|
|
I2C_InitStructure.BusMode = I2C_BUSMODE_I2C;
|
|
|
|
I2C_InitStructure.FmDutyCycle = I2C_FMDUTYCYCLE_2;
|
|
|
|
I2C_InitStructure.OwnAddr1 = 0xff;
|
|
|
|
I2C_InitStructure.AckEnable = I2C_ACKEN;
|
|
|
|
I2C_InitStructure.AddrMode = I2C_ADDR_MODE_7BIT;
|
|
|
|
I2C_InitStructure.ClkSpeed = I2C3_SPEED; // 100000 100K
|
|
|
|
|
|
|
|
I2C_Init(I2C3, &I2C_InitStructure);
|
|
|
|
|
|
|
|
rt_memset((void *)&i2c_bus3, 0, sizeof(struct rt_i2c_bus));
|
|
|
|
i2c_bus3.parent.ops = &i2c_ops;
|
|
|
|
i2c_bus3.i2c_periph = (rt_uint32_t)I2C3;
|
|
|
|
rt_i2c_bus_device_register(&i2c_bus3.parent, "i2c3");
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef BSP_USING_I2C4
|
|
|
|
#define I2C4_SPEED 100000
|
|
|
|
|
|
|
|
static struct rt_i2c_bus i2c_bus4;
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_GPIOC, ENABLE);
|
2022-07-13 19:56:14 +08:00
|
|
|
RCC_EnableAPB2PeriphClk(RCC_APB2_PERIPH_I2C4, ENABLE);
|
|
|
|
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_InitStruct(&GPIO_InitStructure);
|
2022-07-13 19:56:14 +08:00
|
|
|
/* connect PC6 to I2C4_SCL, PC7 to I2C4_SDA */
|
2022-10-20 09:40:14 +08:00
|
|
|
GPIO_InitStructure.Pin = GPIO_PIN_6 | GPIO_PIN_7;
|
|
|
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
|
|
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_OD;
|
|
|
|
GPIO_InitPeripheral(GPIOC, &GPIO_InitStructure);
|
2022-07-13 19:56:14 +08:00
|
|
|
|
|
|
|
I2C_DeInit(I2C4);
|
|
|
|
I2C_InitStructure.BusMode = I2C_BUSMODE_I2C;
|
|
|
|
I2C_InitStructure.FmDutyCycle = I2C_FMDUTYCYCLE_2;
|
|
|
|
I2C_InitStructure.OwnAddr1 = 0xff;
|
|
|
|
I2C_InitStructure.AckEnable = I2C_ACKEN;
|
|
|
|
I2C_InitStructure.AddrMode = I2C_ADDR_MODE_7BIT;
|
|
|
|
I2C_InitStructure.ClkSpeed = I2C4_SPEED; // 100000 100K
|
|
|
|
|
|
|
|
I2C_Init(I2C4, &I2C_InitStructure);
|
|
|
|
|
|
|
|
rt_memset((void *)&i2c_bus4, 0, sizeof(struct rt_i2c_bus));
|
|
|
|
i2c_bus4.parent.ops = &i2c_ops;
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i2c_bus4.i2c_periph = (rt_uint32_t)I2C4;
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rt_i2c_bus_device_register(&i2c_bus4.parent, "i2c4");
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#endif
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2022-10-20 09:40:14 +08:00
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#endif
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2022-07-15 13:36:32 +08:00
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#endif /* RT_USING_HARDWARE_I2C */
|
2022-07-13 19:56:14 +08:00
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|
|
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2022-07-15 13:36:32 +08:00
|
|
|
return RT_EOK;
|
2022-07-13 19:56:14 +08:00
|
|
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}
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|
|
|
INIT_DEVICE_EXPORT(rt_hw_i2c_init);
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|
|
|
|
|
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#endif
|
|
|
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/* end of i2c driver */
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