270 lines
9.7 KiB
C
270 lines
9.7 KiB
C
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/**************************************************************************//**
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* @file nu_dac.h
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* @version V1.00
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* @brief M480 series DAC driver header file
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*
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* SPDX-License-Identifier: Apache-2.0
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* @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved.
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*****************************************************************************/
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#ifndef __NU_DAC_H__
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#define __NU_DAC_H__
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** @addtogroup Standard_Driver Standard Driver
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@{
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*/
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/** @addtogroup DAC_Driver DAC Driver
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@{
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*/
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/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
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@{
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*/
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/*---------------------------------------------------------------------------------------------------------*/
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/* DAC_CTL Constant Definitions */
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/*---------------------------------------------------------------------------------------------------------*/
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#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. \hideinitializer */
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#define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment \hideinitializer */
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#define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger \hideinitializer */
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#define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger \hideinitializer */
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#define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger \hideinitializer */
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#define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger \hideinitializer */
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#define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger \hideinitializer */
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#define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger \hideinitializer */
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#define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger \hideinitializer */
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#define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger \hideinitializer */
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#define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger \hideinitializer */
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#define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger \hideinitializer */
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#define DAC_EPWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM0 trigger \hideinitializer */
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#define DAC_EPWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< EPWM1 trigger \hideinitializer */
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#define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable \hideinitializer */
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#define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable \hideinitializer */
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/*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */
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/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
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@{
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*/
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/**
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* @brief Start the D/A conversion.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.
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* \hideinitializer
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*/
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#define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)
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/**
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* @brief Enable DAC data left-aligned.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
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* \hideinitializer
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*/
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#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
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/**
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* @brief Enable DAC data right-aligned.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
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* \hideinitializer
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*/
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#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
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/**
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* @brief Enable output voltage buffer.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
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* drive external loads directly without having to add an external operational amplifier.
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* \hideinitializer
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*/
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#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
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/**
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* @brief Disable output voltage buffer.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details This macro is used to disable output voltage buffer.
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* \hideinitializer
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*/
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#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
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/**
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* @brief Enable the interrupt.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch Not used in M480 DAC.
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* @return None
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* @details This macro is used to enable DAC interrupt.
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* \hideinitializer
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*/
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#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
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/**
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* @brief Disable the interrupt.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch Not used in M480 DAC.
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* @return None
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* @details This macro is used to disable DAC interrupt.
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* \hideinitializer
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*/
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#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
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/**
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* @brief Enable DMA under-run interrupt.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details This macro is used to enable DMA under-run interrupt.
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* \hideinitializer
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*/
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#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
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/**
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* @brief Disable DMA under-run interrupt.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details This macro is used to disable DMA under-run interrupt.
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* \hideinitializer
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*/
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#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
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/**
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* @brief Enable PDMA mode.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
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* \hideinitializer
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*/
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#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
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/**
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* @brief Disable PDMA mode.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details This macro is used to disable DMA mode.
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* \hideinitializer
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*/
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#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
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/**
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* @brief Write data for conversion.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch Not used in M480 DAC.
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* @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
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* @return None
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* @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
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* 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
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* \hideinitializer
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*/
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#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
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/**
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* @brief Read DAC 12-bit holding data.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch Not used in M480 DAC.
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* @return Return DAC 12-bit holding data.
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* @details This macro is used to read DAC_DAT register.
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* \hideinitializer
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*/
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#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
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/**
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* @brief Get the busy state of DAC.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch Not used in M480 DAC.
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* @retval 0 Idle state.
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* @retval 1 Busy state.
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* @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
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* \hideinitializer
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*/
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#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
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/**
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* @brief Get the interrupt flag.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch Not used in M480 DAC.
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* @retval 0 DAC is in conversion state.
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* @retval 1 DAC conversion finish.
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* @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
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* \hideinitializer
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*/
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#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
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/**
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* @brief Get the DMA under-run flag.
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* @param[in] dac Base address of DAC module.
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* @retval 0 No DMA under-run error condition occurred.
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* @retval 1 DMA under-run error condition occurred.
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* @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
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* \hideinitializer
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*/
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#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
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/**
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* @brief This macro clear the interrupt status bit.
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* @param[in] dac Base address of DAC module.
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* @param[in] u32Ch Not used in M480 DAC.
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* @return None
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* @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
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* \hideinitializer
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*/
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#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
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/**
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* @brief This macro clear the DMA under-run flag.
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* @param[in] dac Base address of DAC module.
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* @return None
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* @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
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* \hideinitializer
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*/
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#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
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/**
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* @brief Enable DAC group mode
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* @param[in] dac Base address of DAC module.
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* @return None
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* \hideinitializer
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*/
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#define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk)
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/**
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* @brief Disable DAC group mode
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* @param[in] dac Base address of DAC module.
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* @return None
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* \hideinitializer
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*/
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#define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk)
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void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
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void DAC_Close(DAC_T *dac, uint32_t u32Ch);
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uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
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/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
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/*@}*/ /* end of group DAC_Driver */
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/*@}*/ /* end of group Standard_Driver */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __NU_DAC_H__ */
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/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
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