90 lines
4.0 KiB
Python
90 lines
4.0 KiB
Python
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from building import *
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import rtconfig
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Import('RTT_ROOT')
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# get current directory
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cwd = GetCurrentDir()
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src = []
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# The set of source files associated with this SConscript file.
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src = Split('''
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mtb-hal-cat1/source/cyhal_clock.c
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mtb-hal-cat1/source/cyhal_hwmgr.c
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mtb-hal-cat1/source/cyhal_syspm.c
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mtb-hal-cat1/source/cyhal_system.c
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mtb-hal-cat1/source/cyhal_uart.c
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mtb-hal-cat1/source/cyhal_gpio.c
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mtb-hal-cat1/source/cyhal_scb_common.c
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mtb-hal-cat1/source/cyhal_interconnect.c
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mtb-hal-cat1/source/cyhal_utils_psoc.c
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mtb-hal-cat1/source/cyhal_utils.c
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mtb-hal-cat1/source/cyhal_lptimer.c
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mtb-hal-cat1/source/cyhal_irq_psoc.c
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mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_02.c
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mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c
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mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c
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mtb-pdl-cat1/drivers/source/cy_scb_common.c
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mtb-pdl-cat1/drivers/source/cy_sysclk.c
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mtb-pdl-cat1/drivers/source/cy_systick.c
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mtb-pdl-cat1/drivers/source/cy_gpio.c
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mtb-pdl-cat1/drivers/source/cy_sysint.c
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mtb-pdl-cat1/drivers/source/cy_syslib.c
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mtb-pdl-cat1/drivers/source/cy_scb_i2c.c
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mtb-pdl-cat1/drivers/source/cy_syspm.c
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mtb-pdl-cat1/drivers/source/cy_mcwdt.c
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mtb-pdl-cat1/drivers/source/cy_ipc_pipe.c
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mtb-pdl-cat1/drivers/source/cy_ipc_sema.c
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mtb-pdl-cat1/drivers/source/cy_ipc_drv.c
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mtb-pdl-cat1/drivers/source/cy_trigmux.c
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mtb-pdl-cat1/drivers/source/cy_prot.c
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mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.s
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TARGET_CY8CKIT-062S2-43012/cybsp.c
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TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c
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TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
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TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
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TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
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TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
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TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
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TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
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lib/cy_capsense.lib
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''')
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src += Glob(cwd + '/psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
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if GetDepend(['RT_USING_SERIAL']):
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src += ['retarget-io/cy_retarget_io.c']
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src += ['mtb-hal-cat1/source/cyhal_uart.c']
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src += ['mtb-pdl-cat1/drivers/source/cy_scb_uart.c']
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if GetDepend(['RT_USING_ADC']):
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src += ['mtb-hal-cat1/source/cyhal_dma_dw.c']
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src += ['mtb-hal-cat1/source/cyhal_dma_dmac.c']
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src += ['mtb-hal-cat1/source/cyhal_dma.c']
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src += ['mtb-hal-cat1/source/cyhal_analog_common.c']
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src += ['mtb-hal-cat1/source/cyhal_adc_sar.c']
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src += ['mtb-pdl-cat1/drivers/source/cy_dma.c']
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src += ['mtb-pdl-cat1/drivers/source/cy_sar.c']
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src += ['mtb-pdl-cat1/drivers/source/cy_dmac.c']
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src += ['mtb-pdl-cat1/drivers/source/cy_sysanalog.c']
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path = [cwd + '/capsense',
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cwd + '/psoc6cm0p',
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cwd + '/retarget-io',
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cwd + '/core-lib/include',
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cwd + '/mtb-hal-cat1/include',
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cwd + '/mtb-hal-cat1/include_pvt',
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cwd + '/mtb-pdl-cat1/cmsis/include',
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cwd + '/mtb-pdl-cat1/drivers/include',
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cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include',
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cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include',
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cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include',
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cwd + '/TARGET_CY8CKIT-062S2-43012',
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cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
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if rtconfig.PLATFORM == 'gcc':
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group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
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else:
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group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
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Return('group')
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