2022-07-18 11:43:07 +08:00
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/*
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2024-10-14 11:30:00 +08:00
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* Copyright (c) 2006-2024 RT-Thread Development Team
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2022-07-18 11:43:07 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-07-13 Rbb666 first version
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*/
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#include "drv_pwm.h"
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#ifdef RT_USING_PWM
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2024-08-24 06:15:09 +08:00
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#include <drivers/dev_pwm.h>
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2022-07-18 11:43:07 +08:00
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#include "drv_gpio.h"
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2024-10-14 11:30:00 +08:00
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/*#define DRV_DEBUG*/
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2022-07-28 15:16:35 +08:00
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#define LOG_TAG "drv.pwm"
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2022-07-18 11:43:07 +08:00
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#include <drv_log.h>
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struct rt_device_pwm pwm_device;
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struct ifx_pwm
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{
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struct rt_device_pwm pwm_device;
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cyhal_pwm_t *pwm_obj;
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rt_uint8_t channel;
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char *name;
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rt_uint8_t gpio;
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};
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static struct ifx_pwm ifx_pwm_obj[] =
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{
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2024-08-22 17:00:51 +08:00
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#ifdef BSP_USING_PWM0_CH0_PORT0
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2023-03-30 15:23:55 +08:00
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PWM0_CH0_PORT0_CONFIG,
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2022-07-28 15:16:35 +08:00
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#endif
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2022-07-18 11:43:07 +08:00
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2024-08-22 17:00:51 +08:00
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#ifdef BSP_USING_PWM0_CH2_PORT11_COMPL
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PWM0_CH2_PORT11_COMPL_CONFIG,
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#endif
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#ifdef BSP_USING_PWM0_CH3_PORT11
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PWM0_CH3_PORT11_CONFIG,
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#endif
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#ifdef BSP_USING_PWM0_CH4_PORT5_COMPL
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PWM0_CH4_PORT5_COMPL_CONFIG,
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#endif
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#ifdef BSP_USING_PWM0_CH7_PORT2
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2022-07-28 15:16:35 +08:00
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PWM0_CH7_PORT2_CONFIG,
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#endif
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2022-07-18 11:43:07 +08:00
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2024-08-22 17:00:51 +08:00
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#ifdef BSP_USING_PWM0_CH7_PORT5
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2022-07-28 15:16:35 +08:00
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PWM0_CH7_PORT5_CONFIG,
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#endif
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2024-08-22 17:00:51 +08:00
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#ifdef BSP_USING_PWM0_CH7_PORT5_COMPL
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PWM0_CH7_PORT5_COMPL_CONFIG,
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#endif
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#ifdef BSP_USING_PWM0_CH7_PORT7
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2022-07-28 15:16:35 +08:00
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PWM0_CH7_PORT7_CONFIG,
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#endif
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2024-08-22 17:00:51 +08:00
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#ifdef BSP_USING_PWM0_CH7_PORT9
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2022-07-28 15:16:35 +08:00
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PWM0_CH7_PORT9_CONFIG,
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#endif
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2024-08-22 17:00:51 +08:00
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#ifdef BSP_USING_PWM0_CH7_PORT10
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2022-07-28 15:16:35 +08:00
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PWM0_CH7_PORT10_CONFIG,
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#endif
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2024-08-22 17:00:51 +08:00
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#ifdef BSP_USING_PWM0_CH7_PORT12
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2022-07-28 15:16:35 +08:00
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PWM0_CH7_PORT12_CONFIG,
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#endif
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2023-03-30 15:23:55 +08:00
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2024-08-22 17:00:51 +08:00
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#ifdef BSP_USING_PWM0_CH7_PORT13
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2023-03-30 15:23:55 +08:00
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PWM0_CH3_PORT13_CONFIG,
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#endif
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2022-07-28 15:16:35 +08:00
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};
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2022-07-18 11:43:07 +08:00
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static rt_err_t drv_pwm_enable(cyhal_pwm_t *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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{
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/* get the value of channel */
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rt_uint32_t channel = configuration->channel;
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if (!configuration->complementary || configuration->complementary)
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{
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if (!enable)
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{
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2024-10-14 11:30:00 +08:00
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htim->tcpwm.resource.channel_num = channel;
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2022-07-28 15:16:35 +08:00
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cyhal_pwm_stop(htim);
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2022-07-18 11:43:07 +08:00
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}
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else
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{
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2024-10-14 11:30:00 +08:00
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htim->tcpwm.resource.channel_num = channel;
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2022-07-28 15:16:35 +08:00
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cyhal_pwm_start(htim);
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2022-07-18 11:43:07 +08:00
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}
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}
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return RT_EOK;
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}
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static rt_err_t drv_pwm_set(cyhal_pwm_t *htim, struct rt_pwm_configuration *configuration)
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{
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rt_uint64_t tim_clock;
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rt_uint32_t period, pulse;
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tim_clock = (rt_uint32_t)(htim->tcpwm.clock_hz);
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2022-07-28 15:16:35 +08:00
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htim->tcpwm.resource.channel_num = configuration->channel;
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2022-07-18 11:43:07 +08:00
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period = (unsigned long long)configuration->period / 1000ULL;
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pulse = (unsigned long long)configuration->pulse / 1000ULL;
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cyhal_pwm_set_period(htim, period, pulse);
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return RT_EOK;
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}
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static rt_err_t drv_pwm_get(cyhal_pwm_t *htim, struct rt_pwm_configuration *configuration)
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{
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uint32_t Period = Cy_TCPWM_PWM_GetPeriod0(htim->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(htim->tcpwm.resource));
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uint32_t Compare = Cy_TCPWM_PWM_GetCounter(htim->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(htim->tcpwm.resource));
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configuration->period = Period;
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configuration->pulse = Compare;
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return RT_EOK;
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}
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static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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{
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struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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cyhal_pwm_t *htim = (cyhal_pwm_t *)device->parent.user_data;
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switch (cmd)
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{
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2022-07-28 15:16:35 +08:00
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case PWMN_CMD_ENABLE:
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configuration->complementary = RT_TRUE;
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2022-07-27 15:41:25 +08:00
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2022-07-28 15:16:35 +08:00
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case PWM_CMD_ENABLE:
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return drv_pwm_enable(htim, configuration, RT_TRUE);
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2022-07-27 15:41:25 +08:00
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2022-07-28 15:16:35 +08:00
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case PWMN_CMD_DISABLE:
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configuration->complementary = RT_FALSE;
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2022-07-27 15:41:25 +08:00
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2022-07-28 15:16:35 +08:00
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case PWM_CMD_DISABLE:
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return drv_pwm_enable(htim, configuration, RT_FALSE);
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2022-07-27 15:41:25 +08:00
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2022-07-28 15:16:35 +08:00
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case PWM_CMD_SET:
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return drv_pwm_set(htim, configuration);
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2022-07-27 15:41:25 +08:00
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2022-07-28 15:16:35 +08:00
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case PWM_CMD_GET:
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return drv_pwm_get(htim, configuration);
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2022-07-27 15:41:25 +08:00
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2022-07-28 15:16:35 +08:00
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default:
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2023-03-16 12:44:05 +08:00
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return -RT_EINVAL;
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2022-07-18 11:43:07 +08:00
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}
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}
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2022-07-28 15:16:35 +08:00
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static struct rt_pwm_ops drv_ops = {drv_pwm_control};
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2022-07-18 11:43:07 +08:00
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static rt_err_t ifx_hw_pwm_init(struct ifx_pwm *device)
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{
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rt_err_t result = RT_EOK;
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RT_ASSERT(device != RT_NULL);
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2023-03-30 15:23:55 +08:00
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if (cyhal_pwm_init_adv(device->pwm_obj, device->gpio, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, false, RT_NULL) != RT_EOK)
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2022-07-28 15:16:35 +08:00
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{
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2023-03-30 15:23:55 +08:00
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LOG_E("%s channel%d config failed", device->name, device->channel);
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result = -RT_ERROR;
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goto __exit;
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2022-07-18 11:43:07 +08:00
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}
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2023-03-30 15:23:55 +08:00
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2022-07-18 11:43:07 +08:00
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__exit:
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return result;
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}
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static int rt_hw_pwm_init(void)
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{
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2022-07-20 12:39:42 +08:00
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int i;
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2022-07-18 11:43:07 +08:00
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int result = RT_EOK;
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for (i = 0; i < sizeof(ifx_pwm_obj) / sizeof(ifx_pwm_obj[0]); i++)
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{
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ifx_pwm_obj[i].pwm_obj = rt_malloc(sizeof(cyhal_pwm_t));
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2022-07-20 12:39:42 +08:00
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RT_ASSERT(ifx_pwm_obj[i].pwm_obj != RT_NULL);
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2022-07-18 11:43:07 +08:00
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/* pwm init */
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if (ifx_hw_pwm_init(&ifx_pwm_obj[i]) != RT_EOK)
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{
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LOG_E("%s init failed", ifx_pwm_obj[i].name);
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result = -RT_ERROR;
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goto __exit;
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}
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else
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{
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if (rt_device_pwm_register(&ifx_pwm_obj[i].pwm_device, ifx_pwm_obj[i].name, &drv_ops, ifx_pwm_obj[i].pwm_obj) == RT_EOK)
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{
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LOG_D("%s register success", ifx_pwm_obj[i].name);
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}
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else
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{
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LOG_D("%s register failed", ifx_pwm_obj[i].name);
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result = -RT_ERROR;
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}
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}
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}
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__exit:
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_pwm_init);
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2022-07-28 15:16:35 +08:00
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#define PWM_DEV_NAME "pwm0"
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2024-08-22 17:00:51 +08:00
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#define PWM_DEV_CHANNEL 4
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2022-07-18 11:43:07 +08:00
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struct rt_device_pwm *pwm_dev;
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static int pwm_sample(int argc, char *argv[])
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{
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rt_uint32_t period, pulse, dir;
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2022-07-28 15:16:35 +08:00
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period = 1 * 1000 * 1000;
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2022-07-18 11:43:07 +08:00
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dir = 1;
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pulse = 0;
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pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
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2022-07-27 15:41:25 +08:00
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2022-07-18 11:43:07 +08:00
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if (pwm_dev == RT_NULL)
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{
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rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
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2023-03-17 12:12:16 +08:00
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return -RT_ERROR;
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2022-07-18 11:43:07 +08:00
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}
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rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
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rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
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2022-07-28 15:16:35 +08:00
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rt_kprintf("Now PWM[%s] Channel[%d] Period[%d] Pulse[%d]\n", PWM_DEV_NAME, PWM_DEV_CHANNEL, period, pulse);
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2022-07-18 11:43:07 +08:00
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while (1)
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{
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rt_thread_mdelay(50);
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if (dir)
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{
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2022-07-28 15:16:35 +08:00
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pulse += 100000;
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2022-07-18 11:43:07 +08:00
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}
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else
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{
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2022-07-28 15:16:35 +08:00
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pulse -= 100000;
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2022-07-18 11:43:07 +08:00
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}
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2022-07-27 15:41:25 +08:00
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2022-07-18 11:43:07 +08:00
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if (pulse >= period)
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{
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dir = 0;
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}
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2022-07-27 15:41:25 +08:00
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2022-07-18 11:43:07 +08:00
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if (0 == pulse)
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{
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dir = 1;
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}
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rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
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}
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}
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MSH_CMD_EXPORT(pwm_sample, <pwm0> channel7 sample);
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#endif
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