229 lines
8.3 KiB
C
229 lines
8.3 KiB
C
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/**
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*******************************************************************************
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* @file hc32f4a0_wdt.h
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* @brief This file contains all the functions prototypes of the WDT driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Yangjp First version
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_WDT_H__
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#define __HC32F4A0_WDT_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_WDT
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* @{
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*/
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#if (DDL_WDT_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup WDT_Global_Types WDT Global Types
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* @{
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*/
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/**
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* @brief WDT Init structure definition
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*/
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typedef struct
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{
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uint32_t u32CountCycle; /*!< Specifies the WDT Count Cycle.
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This parameter can be a value of @ref WDT_Counter_Cycle */
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uint32_t u32ClockDivision; /*!< Specifies the WDT Clock Division.
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This parameter can be a value of @ref WDT_Clock_Division */
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uint32_t u32RefreshRange; /*!< Specifies the WDT Allow Refresh Range.
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This parameter can be a value of @ref WDT_Refresh_Percent_Range */
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uint32_t u32LPModeCountEn; /*!< Specifies the WDT Count Enable/Disable In Low Power Mode(Sleep Mode).
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This parameter can be a value of @ref WDT_LPW_Mode_Count */
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uint32_t u32TrigType; /*!< Specifies the WDT Refresh Error or Count Underflow trigger event Type.
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This parameter can be a value of @ref WDT_Trigger_Event_Type */
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} stc_wdt_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup WDT_Global_Macros WDT Global Macros
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* @{
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*/
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/**
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* @defgroup WDT_Counter_Cycle WDT Counter Cycle
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* @{
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*/
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#define WDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */
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#define WDT_COUNTER_CYCLE_4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */
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#define WDT_COUNTER_CYCLE_16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */
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#define WDT_COUNTER_CYCLE_65536 (WDT_CR_PERI) /*!< 65536 clock cycle */
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/**
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* @}
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*/
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/**
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* @defgroup WDT_Clock_Division WDT Clock Division
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* @{
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*/
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#define WDT_CLOCK_DIV4 (WDT_CR_CKS_1) /*!< PLCK3/4 */
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#define WDT_CLOCK_DIV64 (WDT_CR_CKS_2 | WDT_CR_CKS_1) /*!< PLCK3/64 */
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#define WDT_CLOCK_DIV128 (WDT_CR_CKS_2 | WDT_CR_CKS_1 | WDT_CR_CKS_0) /*!< PLCK3/128 */
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#define WDT_CLOCK_DIV256 (WDT_CR_CKS_3) /*!< PLCK3/256 */
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#define WDT_CLOCK_DIV512 (WDT_CR_CKS_3 | WDT_CR_CKS_0) /*!< PLCK3/512 */
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#define WDT_CLOCK_DIV1024 (WDT_CR_CKS_3 | WDT_CR_CKS_1) /*!< PLCK3/1024 */
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#define WDT_CLOCK_DIV2048 (WDT_CR_CKS_3 | WDT_CR_CKS_1 | WDT_CR_CKS_0) /*!< PLCK3/2048 */
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#define WDT_CLOCK_DIV8192 (WDT_CR_CKS_3 | WDT_CR_CKS_2 | WDT_CR_CKS_0) /*!< PLCK3/8192 */
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/**
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* @}
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*/
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/**
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* @defgroup WDT_Refresh_Percent_Range WDT Refresh Percent Range
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* @{
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*/
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#define WDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */
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#define WDT_RANGE_0TO25PCT (WDT_CR_WDPT_0) /*!< 0%~25% */
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#define WDT_RANGE_25TO50PCT (WDT_CR_WDPT_1) /*!< 25%~50% */
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#define WDT_RANGE_0TO50PCT (WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~50% */
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#define WDT_RANGE_50TO75PCT (WDT_CR_WDPT_2) /*!< 50%~75% */
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#define WDT_RANGE_0TO25PCT_50TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_0) /*!< 0%~25% & 50%~75% */
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#define WDT_RANGE_25TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_1) /*!< 25%~75% */
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#define WDT_RANGE_0TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~75% */
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#define WDT_RANGE_75TO100PCT (WDT_CR_WDPT_3) /*!< 75%~100% */
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#define WDT_RANGE_0TO25PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_0) /*!< 0%~25% & 75%~100% */
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#define WDT_RANGE_25TO50PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_1) /*!< 25%~50% & 75%~100% */
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#define WDT_RANGE_0TO50PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~50% & 75%~100% */
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#define WDT_RANGE_50TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2) /*!< 50%~100% */
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#define WDT_RANGE_0TO25PCT_50TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2 | WDT_CR_WDPT_0) /*!< 0%~25% & 50%~100% */
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#define WDT_RANGE_25TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2 | WDT_CR_WDPT_1) /*!< 25%~100% */
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/**
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* @}
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*/
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/**
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* @defgroup WDT_LPW_Mode_Count WDT Low Power Mode Count
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* @brief WDT count control in the sleep mode
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* @{
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*/
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#define WDT_LPM_COUNT_CONTINUE (0UL) /*!< WDT count continue in the sleep mode */
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#define WDT_LPM_COUNT_STOP (WDT_CR_SLPOFF) /*!< WDT count stop in the sleep mode */
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/**
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* @}
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*/
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/**
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* @defgroup WDT_Trigger_Event_Type WDT Trigger Event Type
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* @{
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*/
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#define WDT_TRIG_EVENT_INT (0UL) /*!< WDT trigger interrupt */
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#define WDT_TRIG_EVENT_RESET (WDT_CR_ITS) /*!< WDT trigger reset */
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/**
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* @}
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*/
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/**
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* @defgroup WDT_Flag WDT Flag
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* @{
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*/
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#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */
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#define WDT_FLAG_REF (WDT_SR_REF) /*!< Refresh error flag */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup WDT_Global_Functions
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* @{
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*/
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/**
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* @brief Get WDT count value.
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* @param None
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* @retval Count value
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*/
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__STATIC_INLINE uint16_t WDT_GetCountValue(void)
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{
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return (uint16_t)(READ_REG32(M4_WDT->SR) & WDT_SR_CNT);
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}
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/* Initialization and configuration functions */
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en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit);
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void WDT_Feed(void);
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uint16_t WDT_GetCountValue(void);
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/* Flags management functions */
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en_flag_status_t WDT_GetStatus(uint32_t u32Flag);
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en_result_t WDT_ClearStatus(uint32_t u32Flag);
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/**
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* @}
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*/
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#endif /* DDL_WDT_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4A0_WDT_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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