380 lines
13 KiB
C
380 lines
13 KiB
C
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/**
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*******************************************************************************
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* @file hc32f4a0_smc.h
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* @brief This file contains all the functions prototypes of the EXMC SMC
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* (External Memory Controller: Static Memory Controller) driver library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Hongjh First version
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2020-07-14 Hongjh Merge API from EXMC_SMC_Enable/Disable to EXMC_SMC_Cmd
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_SMC_H__
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#define __HC32F4A0_SMC_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_EXMC_SMC
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* @{
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*/
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#if (DDL_SMC_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup EXMC_SMC_Global_Types Static Memory Controller Global Types
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* @{
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*/
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/**
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* @brief EXMC SMC Chip Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t u32ReadMode; /*!< Defines the read sync enable.
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This parameter can be a value of @ref EXMC_SMC_Memory_Read_Mode */
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uint32_t u32WriteMode; /*!< Defines the write sync enable.
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This parameter can be a value of @ref EXMC_SMC_Memory_Write_Mode */
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uint32_t u32ReadBurstLen; /*!< Defines the number of read data access.
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This parameter can be a value of @ref EXMC_SMC_Memory_Read_Burst_Length. */
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uint32_t u32WriteBurstLen; /*!< Defines the number of write data access.
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This parameter can be a value of @ref EXMC_SMC_Memory_Write_Burst_Length. */
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uint32_t u32SmcMemWidth; /*!< Defines the SMC memory width.
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This parameter can be a value of @ref EXMC_SMC_Memory_Width. */
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uint32_t u32BAA; /*!< Defines the SMC BAA signal enable.
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This parameter can be a value of @ref EXMC_SMC_BAA_Port_Selection. */
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uint32_t u32ADV; /*!< Defines the SMC ADVS signal enable.
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This parameter can be a value of @ref EXMC_SMC_ADV_Port_Selection. */
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uint32_t u32BLS; /*!< Defines the SMC BLS signal selection.
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This parameter can be a value of @ref EXMC_SMC_BLS_Synchronization_Selection. */
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uint32_t u32AddressMask; /*!< Defines the address mask.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */
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uint32_t u32AddressMatch; /*!< Defines the address match.
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This parameter can be a value between Min_Data = 0x60 and Max_Data = 0x7F */
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}stc_exmc_smc_chip_cfg_t;
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/**
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* @brief EXMC SMC Timing Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t u32RC; /*!< Defines the RC in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
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uint32_t u32WC; /*!< Defines the WC in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */
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uint32_t u32CEOE; /*!< Defines the CEOE in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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uint32_t u32WP; /*!< Defines the WP in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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uint32_t u32PC; /*!< Defines the PC in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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uint32_t u32TR; /*!< Defines the TR in memory clock cycles.
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This parameter can be a value between Min_Data = 0 and Max_Data = 7 */
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} stc_exmc_smc_timing_cfg_t;
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/**
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* @brief EXMC SMC Initialization Structure definition
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*/
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typedef struct
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{
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stc_exmc_smc_chip_cfg_t stcChipCfg; /*!< SMC memory chip configure.
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This structure details refer @ref stc_exmc_smc_chip_cfg_t. */
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stc_exmc_smc_timing_cfg_t stcTimingCfg; /*!< SMC memory timing configure.
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This structure details refer @ref stc_exmc_smc_timing_cfg_t. */
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} stc_exmc_smc_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup EXMC_SMC_Global_Macros Static Memory Controller Global Macros
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* @{
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*/
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/**
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* @defgroup EXMC_SMC_Chip EXMC SMC Chip
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* @{
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*/
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#define EXMC_SMC_CHIP_0 (0UL) /*!< Chip 0 */
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#define EXMC_SMC_CHIP_1 (1UL) /*!< Chip 1 */
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#define EXMC_SMC_CHIP_2 (2UL) /*!< Chip 2 */
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#define EXMC_SMC_CHIP_3 (3UL) /*!< Chip 3 */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_Memory_Read_Mode EXMC SMC Memory Read Mode
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* @{
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*/
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#define EXMC_SMC_MEM_READ_ASYNC (0UL)
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#define EXMC_SMC_MEM_READ_SYNC (SMC_CPCR_RSYN)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_Memory_Write_Mode EXMC SMC Memory Write Mode
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* @{
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*/
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#define EXMC_SMC_MEM_WRITE_ASYNC (0UL)
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#define EXMC_SMC_MEM_WRITE_SYNC (SMC_CPCR_WSYN)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_Memory_Read_Burst_Length EXMC SMC Memory Read Burst Length
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* @{
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*/
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#define EXMC_SMC_MEM_READ_BURST_1 (0UL) /*!< 1 beat */
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#define EXMC_SMC_MEM_READ_BURST_4 (SMC_CPCR_RBL_0) /*!< 4 beats */
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#define EXMC_SMC_MEM_READ_BURST_8 (SMC_CPCR_RBL_1) /*!< 8 beats */
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#define EXMC_SMC_MEM_READ_BURST_16 (SMC_CPCR_RBL_1 | \
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SMC_CPCR_RBL_0) /*!< 16 beats */
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#define EXMC_SMC_MEM_READ_BURST_32 (SMC_CPCR_RBL_2) /*!< 32 beats */
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#define EXMC_SMC_MEM_READ_BURST_CONTINUOUS (SMC_CPCR_RBL_2 | \
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SMC_CPCR_RBL_0) /*!< continuous */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_Memory_Write_Burst_Length EXMC SMC Memory Write Burst Length
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* @{
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*/
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#define EXMC_SMC_MEM_WRITE_BURST_1 (0UL) /*!< 1 beat */
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#define EXMC_SMC_MEM_WRITE_BURST_4 (SMC_CPCR_WBL_0) /*!< 4 beats */
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#define EXMC_SMC_MEM_WRITE_BURST_8 (SMC_CPCR_WBL_1) /*!< 8 beats */
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#define EXMC_SMC_MEM_WRITE_BURST_16 (SMC_CPCR_WBL_1 | \
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SMC_CPCR_WBL_0) /*!< 16 beats */
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#define EXMC_SMC_MEM_WRITE_BURST_32 (SMC_CPCR_WBL_2) /*!< 32 beats */
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#define EXMC_SMC_MEM_WRITE_BURST_CONTINUOUS (SMC_CPCR_WBL_2 | \
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SMC_CPCR_WBL_0) /*!< continuous */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_Memory_Width EXMC SMC Memory Width
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* @{
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*/
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#define EXMC_SMC_MEMORY_WIDTH_16BIT (SMC_CPCR_MW_0)
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#define EXMC_SMC_MEMORY_WIDTH_32BIT (SMC_CPCR_MW_1)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_BAA_Port_Selection EXMC SMC BAA Port Selection
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* @{
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*/
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#define EXMC_SMC_BAA_PORT_DISABLE (0UL)
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#define EXMC_SMC_BAA_PORT_ENABLE (SMC_CPCR_BAAS)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_ADV_Port_Selection EXMC SMC ADV Port Selection
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* @{
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*/
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#define EXMC_SMC_ADV_PORT_DISABLE (0UL)
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#define EXMC_SMC_ADV_PORT_ENABLE (SMC_CPCR_ADVS)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_BLS_Synchronization_Selection EXMC SMC BLS Synchronization Selection
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* @{
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*/
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#define EXMC_SMC_BLS_SYNC_CS (0UL)
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#define EXMC_SMC_BLS_SYNC_WE (SMC_CPCR_BLSS)
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_Command EXMC SMC Command
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* @{
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*/
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#define EXMC_SMC_CMD_MDREGCONFIG (SMC_CMDR_CMD_0) /*!< Command: MdRetConfig */
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#define EXMC_SMC_CMD_UPDATEREGS (SMC_CMDR_CMD_1) /*!< Command: UpdateRegs */
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#define EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS (SMC_CMDR_CMD) /*!< Command: MdRetConfig & UpdateRegs */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_CRE_Polarity EXMC SMC CRE Polarity
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* @{
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*/
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#define EXMC_SMC_CRE_POLARITY_LOW (0UL) /*!< CRE is LOW */
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#define EXMC_SMC_CRE_POLARITY_HIGH (SMC_CMDR_CRES) /*!< CRE is HIGH when ModeReg write occurs */
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/**
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* @}
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*/
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/**
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* @defgroup EXMC_SMC_Status EXMC SMC Status
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* @{
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*/
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#define EXMC_SMC_READY (0UL) /*!< SMC is ready */
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#define EXMC_SMC_LOWPOWER (SMC_STSR_STATUS) /*!< SMC is low power */
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/**
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* @}
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*/
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/**
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* @brief SMC device memory address shifting.
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* @param [in] mem_base_address SMC base address
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* @param [in] mem_width SMC memory width
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* @param [in] address SMC device memory address
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* @retval SMC device shifted address value
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*/
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#define SMC_ADDR_SHIFT(mem_base_address, mem_width, address) \
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( ((EXMC_SMC_MEMORY_WIDTH_16BIT == (mem_width))? (((mem_base_address) + ((address) << 1UL))):\
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(((mem_base_address) + ((address) << 2UL)))))
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup EXMC_SMC_Global_Functions
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* @{
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*/
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/**
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* @brief SMC entry low power state
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void EXMC_SMC_EntryLowPower(void)
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{
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WRITE_REG32(M4_SMC->STCR0, SMC_STCR0_LPWIR);
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}
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/**
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* @brief SMC exit low power state
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* @param None
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* @retval None
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*/
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__STATIC_INLINE void EXMC_SMC_ExitLowPower(void)
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{
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WRITE_REG32(M4_SMC->STCR1, SMC_STCR1_LPWOR);
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}
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/**
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* @brief Get SMC status
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* @param None
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* @retval Returned value can be one of the following values:
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* @arg EXMC_SMC_READY: SMC is ready
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* @arg EXMC_SMC_LOWPOWER: SMC is low power
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*/
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__STATIC_INLINE uint32_t EXMC_SMC_GetStatus(void)
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{
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return READ_REG32_BIT(M4_SMC->STSR, SMC_STSR_STATUS);
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}
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/* Initialization and configuration EXMC SMC functions */
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en_result_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcInit);
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void EXMC_SMC_DeInit(void);
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en_result_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcInit);
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void EXMC_SMC_Cmd(en_functional_state_t enNewState);
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void EXMC_SMC_SetCommand(uint32_t u32Chip,
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uint32_t u32Cmd,
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uint32_t u32CrePolarity,
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uint32_t u32Address);
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uint32_t EXMC_SMC_ChipStartAddress(uint32_t u32Chip);
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uint32_t EXMC_SMC_ChipEndAddress(uint32_t u32Chip);
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en_result_t EXMC_SMC_CheckChipStatus(uint32_t u32Chip,
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const stc_exmc_smc_chip_cfg_t *pstcChipCfg);
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en_result_t EXMC_SMC_CheckTimingStatus(uint32_t u32Chip,
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const stc_exmc_smc_timing_cfg_t *pstcTimingCfg);
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void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState);
|
||
|
|
void EXMC_SMC_SetRefreshPeriod(uint32_t u32PeriodVal);
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#endif /* DDL_SMC_ENABLE */
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __HC32F4A0_SMC_H__ */
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* EOF (not truncated)
|
||
|
|
******************************************************************************/
|