308 lines
8.9 KiB
C
308 lines
8.9 KiB
C
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/**
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*******************************************************************************
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* @file hc32f4a0_fcm.h
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* @brief This file contains all the functions prototypes of the FCM driver
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* library.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Zhangxl First version
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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#ifndef __HC32F4A0_FCM_H__
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#define __HC32F4A0_FCM_H__
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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#include "ddl_config.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @addtogroup DDL_FCM
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* @{
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*/
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#if (DDL_FCM_ENABLE == DDL_ON)
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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* @defgroup FCM_Global_Types FCM Global Types
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* @{
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*/
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/**
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* @brief FCM Init structure definition
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*/
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typedef struct
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{
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uint16_t u16LowerLimit; /*!< FCM lower limit value*/
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uint16_t u16UpperLimit; /*!< FCM upper limit value*/
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uint32_t u32TarClk; /*!< FCM target clock source selection, \
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@ref FCM_Init_Config for details */
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uint32_t u32TarClkDiv; /*!< FCM target clock source division selection,\
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@ref FCM_Init_Config for details */
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uint32_t u32ExRefClkEn; /*!< FCM external reference clock function config, \
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@ref FCM_Init_Config for details */
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uint32_t u32RefClkEdge; /*!< FCM reference clock trigger edge selection,\
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@ref FCM_Init_Config for details */
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uint32_t u32DigFilter; /*!< FCM digital filter function config, \
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@ref FCM_Init_Config for details */
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uint32_t u32RefClk; /*!< FCM reference clock source selection, \
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@ref FCM_Init_Config for details */
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uint32_t u32RefClkDiv; /*!< FCM reference clock source division selection, \
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@ref FCM_Init_Config for details */
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uint32_t u32RstEn; /*!< FCM abnormal reset function config, \
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@ref FCM_Init_Config for details */
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uint32_t u32IntRstSel; /*!< FCM abnormal detecting behavior selection, \
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@ref FCM_Init_Config */
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uint32_t u32IntType; /*!< FCM interrupt type selection, \
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@ref FCM_Init_Config for details. */
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} stc_fcm_init_t;
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/**
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* @}
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*/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup FCM_Global_Macros FCM Global Macros
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* @{
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*/
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/**
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* @defgroup FCM_Registers_Reset_Value FCM Registers Reset Value
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* @{
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*/
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#define FCM_REG_RESET_VALUE (0x00000000UL)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Init_Config FCM init config
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* @{
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*/
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/**
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* @brief FCM target clock source selection
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*/
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#define FCM_TAR_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_PLLAP (0x06UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_PLLHP (0x08UL << FCM_MCCR_MCKS_POS)
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#define FCM_TAR_CLK_RTCLRC (0x09UL << FCM_MCCR_MCKS_POS)
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/**
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* @brief FCM target clock division
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*/
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#define FCM_TAR_CLK_DIV1 (0x00UL)
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#define FCM_TAR_CLK_DIV4 (0x01UL)
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#define FCM_TAR_CLK_DIV8 (0x02UL)
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#define FCM_TAR_CLK_DIV32 (0x03UL)
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/**
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* @brief FCM external reference clock function config
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*/
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#define FCM_EX_REF_OFF (0x00UL)
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#define FCM_EX_REF_ON (FCM_RCCR_EXREFE)
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/**
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* @brief FCM reference clock edge config
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*/
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#define FCM_REF_CLK_RISING (0x00UL)
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#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0)
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#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1)
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/**
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* @brief FCM digital filter function config
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*/
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#define FCM_DF_OFF (0x00UL)
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#define FCM_DF_MCKS_DIV1 (FCM_RCCR_DNFS_0)
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#define FCM_DF_MCKS_DIV4 (FCM_RCCR_DNFS_1)
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#define FCM_DF_MCKS_DIV16 (FCM_RCCR_DNFS)
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/**
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* @brief FCM reference clock source selection
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*/
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#define FCM_REF_CLK_EXINPUT (0x00UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_PCLKAP (0x16UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_PLLHP (0x18UL << FCM_RCCR_RCKS_POS)
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#define FCM_REF_CLK_RTCLRC (0x19UL << FCM_RCCR_RCKS_POS)
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/**
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* @brief FCM reference clock division
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*/
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#define FCM_REF_CLK_DIV32 (0x00UL)
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#define FCM_REF_CLK_DIV128 (0x01UL)
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#define FCM_REF_CLK_DIV1024 (0x02UL)
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#define FCM_REF_CLK_DIV8192 (0x03UL)
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/**
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* @brief FCM abnormal reset function config
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*/
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#define FCM_RST_OFF (0x00UL)
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#define FCM_RST_ON (FCM_RIER_ERRE)
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/**
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* @brief FCM abnormal behavior selection
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*/
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#define FCM_ERR_INT (0x00UL)
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#define FCM_ERR_RESET (FCM_RIER_ERRINTRS)
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/**
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* @brief FCM counter overflow interrupt config
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*/
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#define FCM_OVF_INT_OFF (0x00UL)
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#define FCM_OVF_INT_ON (FCM_RIER_OVFIE)
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/**
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* @brief FCM measure completed interrupt config
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*/
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#define FCM_END_INT_OFF (0x00UL)
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#define FCM_END_INT_ON (FCM_RIER_MENDIE)
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/**
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* @brief FCM error interrupt config
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*/
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#define FCM_ERR_INT_OFF (0x00UL)
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#define FCM_ERR_INT_ON (FCM_RIER_ERRIE)
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/**
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* @brief FCM interrupt mask
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*/
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#define FCM_INT_MSK (FCM_OVF_INT_ON | FCM_END_INT_ON | FCM_ERR_INT_ON)
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/**
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* @}
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*/
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/**
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* @defgroup FCM_Flag_Sel FCM status flag selection
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* @{
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*/
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#define FCM_FLAG_ERR (FCM_SR_ERRF)
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#define FCM_FLAG_END (FCM_SR_MENDF)
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#define FCM_FLAG_OVF (FCM_SR_OVF)
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#define FCM_FLAG_MSK (FCM_SR_ERRF | FCM_SR_MENDF | FCM_SR_OVF)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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Global function prototypes (definition in C source)
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******************************************************************************/
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/**
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* @addtogroup FCM_Global_Functions
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* @{
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*/
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/**
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* @brief Set FCM upper limit value.
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* @param [in] u16Lmt
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* @retval None.
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*/
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__STATIC_INLINE void FCM_SetUpLimit(uint16_t u16Lmt)
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{
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WRITE_REG32(M4_FCM->UVR, u16Lmt);
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}
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/**
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* @brief Set FCM lower limit value.
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* @param u16Lmt
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* @retval None
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*/
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__STATIC_INLINE void FCM_SetLowLimit(uint16_t u16Lmt)
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{
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WRITE_REG32(M4_FCM->LVR, u16Lmt);
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}
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en_result_t FCM_Init(const stc_fcm_init_t *pstcFcmInit);
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en_result_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit);
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void FCM_DeInit(void);
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uint16_t FCM_GetCounter(void);
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void FCM_SetUpLimit(uint16_t u16Lmt);
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void FCM_SetLowLimit(uint16_t u16Lmt);
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void FCM_SetTarClk(uint32_t u32Tar, uint32_t u32Div);
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void FCM_SetRefClk(uint32_t u32Ref, uint32_t u32Div);
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en_flag_status_t FCM_GetStatus(uint32_t u32Flag);
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void FCM_ClearStatus(uint32_t u32Flag);
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void FCM_Cmd(en_functional_state_t enNewState);
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/**
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* @}
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*/
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#endif /* DDL_FCM_ENABLE */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F4A0_FCM_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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