170 lines
4.6 KiB
NASM
170 lines
4.6 KiB
NASM
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;/*
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; * File : context_rvds.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2009-01-20 Bernard first version
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; * 2011-07-22 Bernard added thumb mode porting
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; * 2013-05-24 Grissiom port to CCS
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; */
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.text
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.arm
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.ref rt_thread_switch_interrupt_flag
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.ref rt_interrupt_from_thread
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.ref rt_interrupt_to_thread
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.ref rt_interrupt_enter
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.ref rt_interrupt_leave
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.ref rt_hw_trap_irq
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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.def rt_hw_interrupt_disable
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rt_hw_interrupt_disable
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MRS r0, cpsr
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ORR r1, r0, #0xc0 ; disable irq and fiq in psr
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MSR cpsr_c, r1
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BX lr
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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.def rt_hw_interrupt_enable
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rt_hw_interrupt_enable
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MSR cpsr_c, r0
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BX lr
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; * r0 --> from
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; * r1 --> to
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; */
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.def rt_hw_context_switch
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rt_hw_context_switch
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DSB
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STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
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STMFD sp!, {r0-r12, lr} ; push lr & register file
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MRS r4, cpsr
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TST lr, #0x01
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BEQ _ARM_MODE
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ORR r4, r4, #0x20 ; it's thumb code
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_ARM_MODE
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STMFD sp!, {r4} ; push cpsr
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STR sp, [r0] ; store sp in preempted tasks TCB
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LDR sp, [r1] ; get new task stack pointer
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LDMFD sp!, {r4} ; pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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BIC r4, r4, #0x20 ; must be ARM mode
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MSR cpsr_cxsf, r4
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DSB
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LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * r0 --> to
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; */
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.def rt_hw_context_switch_to
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rt_hw_context_switch_to
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LDR sp, [r0] ; get new task stack pointer
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LDMFD sp!, {r4} ; pop new task cpsr to spsr
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MSR spsr_cxsf, r4
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BIC r4, r4, #0x20 ; must be ARM mode
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MSR spsr_cxsf, r4
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LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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; */
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.def rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt
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LDR r2, pintflag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1
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STR r3, [r2]
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LDR r2, pfromthread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch
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LDR r2, ptothread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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.def IRQ_Handler
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IRQ_Handler
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STMFD sp!, {r0-r12,lr}
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
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; if rt_thread_switch_interrupt_flag set, jump to
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; rt_hw_context_switch_interrupt_do and don't return
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LDR r0, pintflag
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LDR r1, [r0]
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CMP r1, #1
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BEQ rt_hw_context_switch_interrupt_do
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LDMFD sp!, {r0-r12,lr}
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SUBS pc, lr, #4
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; /*
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; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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; */
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.def rt_hw_context_switch_interrupt_do
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rt_hw_context_switch_interrupt_do
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MOV r1, #0 ; clear flag
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STR r1, [r0]
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LDMFD sp!, {r0-r12,lr} ; reload saved registers
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STMFD sp!, {r0-r3} ; save r0-r3
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MOV r1, sp
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ADD sp, sp, #16 ; restore sp
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SUB r2, lr, #4 ; save old task's pc to r2
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MRS r3, spsr ; get cpsr of interrupt thread
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; switch to SVC mode and no interrupt
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MSR cpsr_c, #0xD3
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STMFD sp!, {r2} ; push old task's pc
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STMFD sp!, {r4-r12,lr} ; push old task's lr,r12-r4
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MOV r4, r1 ; Special optimised code below
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MOV r5, r3
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LDMFD r4!, {r0-r3}
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STMFD sp!, {r0-r3} ; push old task's r3-r0
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STMFD sp!, {r5} ; push old task's cpsr
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LDR r4, pfromthread
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LDR r5, [r4]
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STR sp, [r5] ; store sp in preempted tasks's TCB
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LDR r6, ptothread
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LDR r6, [r6]
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LDR sp, [r6] ; get new task's stack pointer
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LDMFD sp!, {r4} ; pop new task's cpsr to spsr
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MSR spsr_cxsf, r4
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BIC r4, r4, #0x20 ; must be ARM mode
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MSR cpsr_cxsf, r4
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LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
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pintflag .word rt_thread_switch_interrupt_flag
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pfromthread .word rt_interrupt_from_thread
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ptothread .word rt_interrupt_to_thread
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