231 lines
14 KiB
C
231 lines
14 KiB
C
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/*!
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\file gd32vf103.h
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\brief general definitions for GD32VF103
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\version 2019-6-5, V1.0.0, firmware for GD32VF103
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*/
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/*
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Copyright (c) 2019, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32VF103_H
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#define GD32VF103_H
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#ifdef cplusplus
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extern "C" {
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#endif
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/* IO definitions (access restrictions to peripheral registers) */
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/**
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<strong>IO Type Qualifiers</strong> are used
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\li to specify the access to peripheral variables.
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\li for automatic generation of peripheral register debug information.
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*/
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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#define HXTAL_VALUE ((uint32_t)8000000) /*!< value of the external oscillator in Hz */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
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#if !defined (IRC8M_VALUE)
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#define IRC8M_VALUE ((uint32_t)8000000)
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#endif /* internal 8MHz RC oscillator value */
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/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
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#if !defined (IRC8M_STARTUP_TIMEOUT)
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#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 8MHz RC oscillator startup timeout */
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/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
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#if !defined (IRC40K_VALUE)
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#define IRC40K_VALUE ((uint32_t)40000)
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#endif /* internal 40KHz RC oscillator value */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* define interrupt number */
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typedef enum IRQn
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{
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CLIC_INT_RESERVED = 0, /*!< RISC-V reserved */
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CLIC_INT_SFT = 3, /*!< Software interrupt */
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CLIC_INT_TMR = 7, /*!< CPU Timer interrupt */
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CLIC_INT_BWEI = 17, /*!< Bus Error interrupt */
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CLIC_INT_PMOVI = 18, /*!< Performance Monitor */
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/* interruput numbers */
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WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */
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LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */
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TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */
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RTC_IRQn = 22, /*!< RTC alarm interrupt */
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FMC_IRQn = 23, /*!< FMC interrupt */
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RCU_CTC_IRQn = 24, /*!< RCU and CTC interrupt */
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EXTI0_IRQn = 25, /*!< EXTI line 0 interrupts */
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EXTI1_IRQn = 26, /*!< EXTI line 1 interrupts */
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EXTI2_IRQn = 27, /*!< EXTI line 2 interrupts */
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EXTI3_IRQn = 28, /*!< EXTI line 3 interrupts */
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EXTI4_IRQn = 29, /*!< EXTI line 4 interrupts */
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DMA0_Channel0_IRQn = 30, /*!< DMA0 channel0 interrupt */
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DMA0_Channel1_IRQn = 31, /*!< DMA0 channel1 interrupt */
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DMA0_Channel2_IRQn = 32, /*!< DMA0 channel2 interrupt */
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DMA0_Channel3_IRQn = 33, /*!< DMA0 channel3 interrupt */
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DMA0_Channel4_IRQn = 34, /*!< DMA0 channel4 interrupt */
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DMA0_Channel5_IRQn = 35, /*!< DMA0 channel5 interrupt */
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DMA0_Channel6_IRQn = 36, /*!< DMA0 channel6 interrupt */
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ADC0_1_IRQn = 37, /*!< ADC0 and ADC1 interrupt */
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CAN0_TX_IRQn = 38, /*!< CAN0 TX interrupts */
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CAN0_RX0_IRQn = 39, /*!< CAN0 RX0 interrupts */
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CAN0_RX1_IRQn = 40, /*!< CAN0 RX1 interrupts */
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CAN0_EWMC_IRQn = 41, /*!< CAN0 EWMC interrupts */
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EXTI5_9_IRQn = 42, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_IRQn = 43, /*!< TIMER0 break interrupts */
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TIMER0_UP_IRQn = 44, /*!< TIMER0 update interrupts */
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TIMER0_TRG_CMT_IRQn = 45, /*!< TIMER0 trigger and commutation interrupts */
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TIMER0_Channel_IRQn = 46, /*!< TIMER0 channel capture compare interrupts */
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TIMER1_IRQn = 47, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 48, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 49, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 50, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 51, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 52, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 53, /*!< I2C1 error interrupt */
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SPI0_IRQn = 54, /*!< SPI0 interrupt */
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SPI1_IRQn = 55, /*!< SPI1 interrupt */
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USART0_IRQn = 56, /*!< USART0 interrupt */
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USART1_IRQn = 57, /*!< USART1 interrupt */
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USART2_IRQn = 58, /*!< USART2 interrupt */
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EXTI10_15_IRQn = 59, /*!< EXTI[15:10] interrupts */
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RTC_ALARM_IRQn = 60, /*!< RTC alarm interrupt EXTI */
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USBFS_WKUP_IRQn = 61, /*!< USBFS wakeup interrupt */
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EXMC_IRQn = 67, /*!< EXMC global interrupt */
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TIMER4_IRQn = 69, /*!< TIMER4 global interrupt */
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SPI2_IRQn = 70, /*!< SPI2 global interrupt */
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UART3_IRQn = 71, /*!< UART3 global interrupt */
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UART4_IRQn = 72, /*!< UART4 global interrupt */
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TIMER5_IRQn = 73, /*!< TIMER5 global interrupt */
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TIMER6_IRQn = 74, /*!< TIMER6 global interrupt */
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DMA1_Channel0_IRQn = 75, /*!< DMA1 channel0 global interrupt */
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DMA1_Channel1_IRQn = 76, /*!< DMA1 channel1 global interrupt */
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DMA1_Channel2_IRQn = 77, /*!< DMA1 channel2 global interrupt */
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DMA1_Channel3_IRQn = 78, /*!< DMA1 channel3 global interrupt */
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DMA1_Channel4_IRQn = 79, /*!< DMA1 channel3 global interrupt */
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CAN1_TX_IRQn = 82, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 83, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 84, /*!< CAN1 RX1 interrupt */
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CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */
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USBFS_IRQn = 86, /*!< USBFS global interrupt */
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ECLIC_NUM_INTERRUPTS
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} IRQn_Type;
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/* includes */
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#include "system_gd32vf103.h"
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#include <stdint.h>
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/* enum definitions */
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
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typedef enum {FALSE = 0, TRUE = !FALSE} bool;
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typedef enum {RESET = 0, SET = 1,MAX = 0X7FFFFFFF} FlagStatus;
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
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/* bit operations */
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#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
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#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
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#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
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#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
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#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
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#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
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/* main flash and SRAM memory map */
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#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
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#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
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#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
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#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
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#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
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/* peripheral memory map */
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#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
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#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
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#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
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#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
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/* advanced peripheral bus 1 memory map */
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#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
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#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
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#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
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#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
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#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
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#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
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#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
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#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
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#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
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#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
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/* advanced peripheral bus 2 memory map */
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#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
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#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
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#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
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#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
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/* advanced high performance bus 1 memory map */
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#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
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#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
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#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
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#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
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#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
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/* define marco USE_STDPERIPH_DRIVER */
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#if !defined USE_STDPERIPH_DRIVER
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#define USE_STDPERIPH_DRIVER
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#endif
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#ifdef USE_STDPERIPH_DRIVER
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#include "gd32vf103_libopt.h"
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#endif /* USE_STDPERIPH_DRIVER */
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#ifdef cplusplus
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}
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#endif
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#endif
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