189 lines
5.2 KiB
ArmAsm
189 lines
5.2 KiB
ArmAsm
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/*
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* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/03/26 Huaqi First Nuclei RISC-V porting implementation
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*/
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#include "riscv_encoding.h"
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#ifndef __riscv_32e
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#define RT_SAVED_REGNUM 30
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#else
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#define RT_SAVED_REGNUM 14
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#endif
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#define RT_CONTEXT_SIZE (RT_SAVED_REGNUM * REGBYTES)
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.extern rt_interrupt_from_thread
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.extern rt_interrupt_to_thread
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.section .text
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/*
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* void rt_hw_context_switch_to(rt_ubase_t to);
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* a0 --> to_thread
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*/
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.globl rt_hw_context_switch_to
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/* Start the first task. This also clears the bit that indicates the FPU is
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in use in case the FPU was used before the scheduler was started - which
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would otherwise result in the unnecessary leaving of space in the stack
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for lazy saving of FPU registers. */
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.align 3
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rt_hw_context_switch_to:
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/* Setup Interrupt Stack using
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The stack that was used by main()
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before the scheduler is started is
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no longer required after the scheduler is started.
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Interrupt stack pointer is stored in CSR_MSCRATCH */
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la t0, _sp
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csrw CSR_MSCRATCH, t0
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LOAD sp, 0x0(a0) /* Read sp from first TCB member(a0) */
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/* Pop PC from stack and set MEPC */
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LOAD t0, 0 * REGBYTES(sp)
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csrw CSR_MEPC, t0
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/* Pop mstatus from stack and set it */
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LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
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csrw CSR_MSTATUS, t0
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/* Interrupt still disable here */
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/* Restore Registers from Stack */
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LOAD x1, 1 * REGBYTES(sp) /* RA */
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LOAD x5, 2 * REGBYTES(sp)
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LOAD x6, 3 * REGBYTES(sp)
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LOAD x7, 4 * REGBYTES(sp)
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LOAD x8, 5 * REGBYTES(sp)
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LOAD x9, 6 * REGBYTES(sp)
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LOAD x10, 7 * REGBYTES(sp)
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LOAD x11, 8 * REGBYTES(sp)
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LOAD x12, 9 * REGBYTES(sp)
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LOAD x13, 10 * REGBYTES(sp)
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LOAD x14, 11 * REGBYTES(sp)
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LOAD x15, 12 * REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 13 * REGBYTES(sp)
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LOAD x17, 14 * REGBYTES(sp)
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LOAD x18, 15 * REGBYTES(sp)
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LOAD x19, 16 * REGBYTES(sp)
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LOAD x20, 17 * REGBYTES(sp)
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LOAD x21, 18 * REGBYTES(sp)
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LOAD x22, 19 * REGBYTES(sp)
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LOAD x23, 20 * REGBYTES(sp)
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LOAD x24, 21 * REGBYTES(sp)
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LOAD x25, 22 * REGBYTES(sp)
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LOAD x26, 23 * REGBYTES(sp)
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LOAD x27, 24 * REGBYTES(sp)
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LOAD x28, 25 * REGBYTES(sp)
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LOAD x29, 26 * REGBYTES(sp)
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LOAD x30, 27 * REGBYTES(sp)
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LOAD x31, 28 * REGBYTES(sp)
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#endif
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addi sp, sp, RT_CONTEXT_SIZE
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mret
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.align 2
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.global eclic_msip_handler
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eclic_msip_handler:
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addi sp, sp, -RT_CONTEXT_SIZE
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STORE x1, 1 * REGBYTES(sp) /* RA */
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STORE x5, 2 * REGBYTES(sp)
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STORE x6, 3 * REGBYTES(sp)
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STORE x7, 4 * REGBYTES(sp)
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STORE x8, 5 * REGBYTES(sp)
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STORE x9, 6 * REGBYTES(sp)
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STORE x10, 7 * REGBYTES(sp)
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STORE x11, 8 * REGBYTES(sp)
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STORE x12, 9 * REGBYTES(sp)
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STORE x13, 10 * REGBYTES(sp)
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STORE x14, 11 * REGBYTES(sp)
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STORE x15, 12 * REGBYTES(sp)
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#ifndef __riscv_32e
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STORE x16, 13 * REGBYTES(sp)
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STORE x17, 14 * REGBYTES(sp)
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STORE x18, 15 * REGBYTES(sp)
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STORE x19, 16 * REGBYTES(sp)
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STORE x20, 17 * REGBYTES(sp)
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STORE x21, 18 * REGBYTES(sp)
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STORE x22, 19 * REGBYTES(sp)
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STORE x23, 20 * REGBYTES(sp)
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STORE x24, 21 * REGBYTES(sp)
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STORE x25, 22 * REGBYTES(sp)
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STORE x26, 23 * REGBYTES(sp)
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STORE x27, 24 * REGBYTES(sp)
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STORE x28, 25 * REGBYTES(sp)
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STORE x29, 26 * REGBYTES(sp)
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STORE x30, 27 * REGBYTES(sp)
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STORE x31, 28 * REGBYTES(sp)
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#endif
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/* Push mstatus to stack */
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csrr t0, CSR_MSTATUS
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STORE t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
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/* Push additional registers */
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/* Store sp to task stack */
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LOAD t0, rt_interrupt_from_thread
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STORE sp, 0(t0)
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csrr t0, CSR_MEPC
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STORE t0, 0(sp)
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jal rt_hw_taskswitch
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/* Switch task context */
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LOAD t0, rt_interrupt_to_thread
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LOAD sp, 0x0(t0)
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/* Pop PC from stack and set MEPC */
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LOAD t0, 0 * REGBYTES(sp)
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csrw CSR_MEPC, t0
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/* Pop additional registers */
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/* Pop mstatus from stack and set it */
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LOAD t0, (RT_SAVED_REGNUM - 1) * REGBYTES(sp)
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csrw CSR_MSTATUS, t0
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/* Interrupt still disable here */
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/* Restore Registers from Stack */
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LOAD x1, 1 * REGBYTES(sp) /* RA */
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LOAD x5, 2 * REGBYTES(sp)
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LOAD x6, 3 * REGBYTES(sp)
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LOAD x7, 4 * REGBYTES(sp)
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LOAD x8, 5 * REGBYTES(sp)
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LOAD x9, 6 * REGBYTES(sp)
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LOAD x10, 7 * REGBYTES(sp)
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LOAD x11, 8 * REGBYTES(sp)
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LOAD x12, 9 * REGBYTES(sp)
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LOAD x13, 10 * REGBYTES(sp)
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LOAD x14, 11 * REGBYTES(sp)
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LOAD x15, 12 * REGBYTES(sp)
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#ifndef __riscv_32e
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LOAD x16, 13 * REGBYTES(sp)
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LOAD x17, 14 * REGBYTES(sp)
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LOAD x18, 15 * REGBYTES(sp)
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LOAD x19, 16 * REGBYTES(sp)
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LOAD x20, 17 * REGBYTES(sp)
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LOAD x21, 18 * REGBYTES(sp)
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LOAD x22, 19 * REGBYTES(sp)
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LOAD x23, 20 * REGBYTES(sp)
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LOAD x24, 21 * REGBYTES(sp)
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LOAD x25, 22 * REGBYTES(sp)
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LOAD x26, 23 * REGBYTES(sp)
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LOAD x27, 24 * REGBYTES(sp)
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LOAD x28, 25 * REGBYTES(sp)
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LOAD x29, 26 * REGBYTES(sp)
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LOAD x30, 27 * REGBYTES(sp)
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LOAD x31, 28 * REGBYTES(sp)
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#endif
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addi sp, sp, RT_CONTEXT_SIZE
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mret
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