517 lines
14 KiB
C
517 lines
14 KiB
C
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/*
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* @brief usart registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "usart_001.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/* Initializes the UARTx peripheral according to the specified parameters in
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the UART_ConfigStruct */
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void IP_UART_Init(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort)
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{
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volatile uint32_t tmp;
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/* FIFOs are empty */
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LPC_UART->FCR = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
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/* Disable FIFO */
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// LPC_UART->FCR = 0;
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/* Dummy reading */
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while (LPC_UART->LSR & UART_LSR_RDR) {
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tmp = LPC_UART->RBR;
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}
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#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
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switch (UARTPort) {
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#if defined(CHIP_LPC177X_8X)
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case 4:
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#else
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case 0:
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case 2:
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case 3:
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#endif
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LPC_UART->TER2 = UART_TER2_TXEN;
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/* Wait for current transmit complete */
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while (!(LPC_UART->LSR & UART_LSR_THRE)) {}
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/* Disable Tx */
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LPC_UART->TER2 = 0;
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break;
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default:
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break;
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}
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#else
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LPC_UART->TER1 = UART_TER1_TXEN;
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/* Wait for current transmit complete */
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while (!(LPC_UART->LSR & UART_LSR_THRE)) {}
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/* Disable Tx */
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LPC_UART->TER1 = 0;
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#endif
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/* Disable interrupt */
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LPC_UART->IER = 0;
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/* Set LCR to default state */
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LPC_UART->LCR = 0;
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/* Set ACR to default state */
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LPC_UART->ACR = 0;
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#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X)
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if ((UARTPort == 1) || (UARTPort == 4)) {
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/* Set RS485 control to default state */
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LPC_UART->RS485CTRL = 0;
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/* Set RS485 delay timer to default state */
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LPC_UART->RS485DLY = 0;
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/* Set RS485 addr match to default state */
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LPC_UART->RS485ADRMATCH = 0;
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}
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#else
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/* Set RS485 control to default state */
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LPC_UART->RS485CTRL = 0;
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/* Set RS485 delay timer to default state */
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LPC_UART->RS485DLY = 0;
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/* Set RS485 addr match to default state */
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LPC_UART->RS485ADRMATCH = 0;
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#endif
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#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
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if (UARTPort == 1) {
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#endif
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/* Set Modem Control to default state */
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LPC_UART->MCR = 0;
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/*Dummy Reading to Clear Status */
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tmp = LPC_UART->MSR;
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#if defined(CHIP_LPC175X_6X) || defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
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}
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#endif
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/* Dummy reading */
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tmp = LPC_UART->LSR;
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/* Set Line Control register ---------------------------- */
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// LPC_UART->LCR = UART_DATABIT_8 | /* Default: 8N1 */
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// UART_STOPBIT_1 |
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// UART_PARITY_NONE;
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LPC_UART->FDR = 0x10; /* No fractional divider */
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}
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/* De-initializes the UARTx peripheral registers to their default reset values */
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void IP_UART_DeInit(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort)
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{
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/* For debug mode */
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IP_UART_TxCmd(LPC_UART, UARTPort, DISABLE);
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switch (UARTPort) {
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default:
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break;
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}
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}
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/* Determines best dividers to get a target clock rate */
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Status IP_UART_SetBaud(IP_USART_001_Type *LPC_UART, uint32_t baudrate, uint32_t uClk)
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{
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Status errorStatus = ERROR;
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uint32_t d, m, bestd, bestm, tmp;
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uint64_t best_divisor, divisor;
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uint32_t current_error, best_error;
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uint32_t recalcbaud;
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/* In the Uart IP block, baud rate is calculated using FDR and DLL-DLM registers
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* The formula is :
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* BaudRate= uClk * (mulFracDiv/(mulFracDiv+dividerAddFracDiv) / (16 * (DLL)
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* It involves floating point calculations. That's the reason the formulae are adjusted with
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* Multiply and divide method.*/
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/* The value of mulFracDiv and dividerAddFracDiv should comply to the following expressions:
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* 0 < mulFracDiv <= 15, 0 <= dividerAddFracDiv <= 15 */
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best_error = 0xFFFFFFFF;/* Worst case */
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bestd = 0;
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bestm = 0;
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best_divisor = 0;
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for (m = 1; m <= 15; m++) {
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for (d = 0; d < m; d++) {
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divisor = ((uint64_t) uClk << 28) * m / (baudrate * (m + d));
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current_error = divisor & 0xFFFFFFFF;
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tmp = divisor >> 32;
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/* Adjust error */
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if (current_error > ((uint32_t) 1 << 31)) {
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current_error = -current_error;
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tmp++;
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}
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if (( tmp < 1) || ( tmp > 65536) ) {/* Out of range */
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continue;
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}
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if ( current_error < best_error) {
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best_error = current_error;
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best_divisor = tmp;
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bestd = d;
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bestm = m;
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if (best_error == 0) {
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break;
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}
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}
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} /* end of inner for loop */
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if (best_error == 0) {
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break;
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}
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} /* end of outer for loop */
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if (best_divisor == 0) {
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return ERROR; /* can not find best match */
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}
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recalcbaud = (uClk >> 4) * bestm / (best_divisor * (bestm + bestd));
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/* reuse best_error to evaluate baud error */
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if (baudrate > recalcbaud) {
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best_error = baudrate - recalcbaud;
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}
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else {best_error = recalcbaud - baudrate; }
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best_error = best_error * 100 / baudrate;
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if (best_error < UART_ACCEPTED_BAUDRATE_ERROR) {
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LPC_UART->LCR |= UART_LCR_DLAB_EN;
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LPC_UART->DLM = UART_LOAD_DLM(best_divisor);
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LPC_UART->DLL = UART_LOAD_DLL(best_divisor);
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/* Then reset DLAB bit */
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LPC_UART->LCR &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
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LPC_UART->FDR = (UART_FDR_MULVAL(bestm) \
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| UART_FDR_DIVADDVAL(bestd)) & UART_FDR_BITMASK;
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errorStatus = SUCCESS;
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}
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return errorStatus;
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}
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/* Configure data width, parity mode and stop bits */
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void IP_UART_ConfigData(IP_USART_001_Type *LPC_UART,
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UART_DATABIT_Type Databits,
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UART_PARITY_Type Parity,
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UART_STOPBIT_Type Stopbits)
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{
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uint32_t tmp = (LPC_UART->LCR & (UART_LCR_DLAB_EN | UART_LCR_BREAK_EN)) & UART_LCR_BITMASK;
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tmp |= (uint32_t) Databits | (uint32_t) Parity | (uint32_t) Stopbits;
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LPC_UART->LCR = (uint8_t) (tmp & UART_LCR_BITMASK);
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}
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/* UART Send/Recieve functions -------------------------------------------------*/
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/* Transmit a single data through UART peripheral */
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Status IP_UART_SendByte(IP_USART_001_Type *LPC_UART, uint8_t Data)
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{
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if (!(LPC_UART->LSR & UART_LSR_THRE)) {
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return ERROR;
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}
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LPC_UART->THR = Data & UART_THR_MASKBIT;
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return SUCCESS;
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}
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/* Receive a single data from UART peripheral */
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Status IP_UART_ReceiveByte(IP_USART_001_Type *LPC_UART, uint8_t *Data)
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{
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if (!(LPC_UART->LSR & UART_LSR_RDR)) {
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return ERROR;
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}
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*Data = (uint8_t) (LPC_UART->RBR & UART_RBR_MASKBIT);
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return SUCCESS;
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}
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/* Send a block of data via UART peripheral */
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uint32_t IP_UART_Send(IP_USART_001_Type *LPC_UART, uint8_t *txbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
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{
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uint32_t bToSend, bSent, timeOut; // , fifo_cnt;
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uint8_t *pChar = txbuf;
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bToSend = buflen;
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/* blocking mode */
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if (flag == BLOCKING) {
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bSent = 0;
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while (bToSend) {
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timeOut = UART_BLOCKING_TIMEOUT;
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/* Wait for THR empty with timeout */
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while (!(IP_UART_SendByte(LPC_UART, *pChar))) {
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if (timeOut == 0) {
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break;
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}
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timeOut--;
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}
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/* Time out! */
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if (timeOut == 0) {
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break;
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}
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pChar++;
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bToSend--;
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bSent++;
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}
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}
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/* None blocking mode */
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else {
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bSent = 0;
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while (bToSend) {
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if (!(IP_UART_SendByte(LPC_UART, *pChar))) {
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break;
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}
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pChar++;
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bToSend--;
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bSent++;
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}
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}
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return bSent;
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}
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/* Receive a block of data via UART peripheral */
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uint32_t IP_UART_Receive(IP_USART_001_Type *LPC_UART, uint8_t *rxbuf, uint32_t buflen, TRANSFER_BLOCK_Type flag)
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{
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uint32_t bToRecv, bRecv, timeOut;
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uint8_t *pChar = rxbuf;
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bToRecv = buflen;
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/* Blocking mode */
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if (flag == BLOCKING) {
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bRecv = 0;
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while (bToRecv) {
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timeOut = UART_BLOCKING_TIMEOUT;
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while (!(IP_UART_ReceiveByte(LPC_UART, pChar))) {
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if (timeOut == 0) {
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break;
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}
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timeOut--;
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}
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/* Time out! */
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if (timeOut == 0) {
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break;
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}
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pChar++;
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bToRecv--;
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bRecv++;
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}
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}
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/* None blocking mode */
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else {
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bRecv = 0;
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while (bToRecv) {
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if (!(IP_UART_ReceiveByte(LPC_UART, pChar))) {
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break;
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}
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else {
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pChar++;
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bRecv++;
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bToRecv--;
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}
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}
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}
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return bRecv;
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}
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/* Enable or disable specified UART interrupt */
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void IP_UART_IntConfig(IP_USART_001_Type *LPC_UART, UART_INT_Type UARTIntCfg, FunctionalState NewState)
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{
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uint32_t tmp = 0;
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switch (UARTIntCfg) {
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case UART_INTCFG_RBR:
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tmp = UART_IER_RBRINT_EN;
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break;
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case UART_INTCFG_THRE:
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tmp = UART_IER_THREINT_EN;
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break;
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case UART_INTCFG_RLS:
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tmp = UART_IER_RLSINT_EN;
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break;
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case UART_INTCFG_MS:
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|
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tmp = UART_IER_MSINT_EN;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case UART_INTCFG_CTS:
|
||
|
|
tmp = UART_IER_CTSINT_EN;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case UART_INTCFG_ABEO:
|
||
|
|
tmp = UART_IER_ABEOINT_EN;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case UART_INTCFG_ABTO:
|
||
|
|
tmp = UART_IER_ABTOINT_EN;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (NewState == ENABLE) {
|
||
|
|
LPC_UART->IER |= tmp;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
|
||
|
|
LPC_UART->IER &= (~tmp) & UART_IER_BITMASK;
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get Source Interrupt */
|
||
|
|
uint32_t IP_UART_IntGetStatus(IP_USART_001_Type *LPC_UART)
|
||
|
|
{
|
||
|
|
return (LPC_UART->IIR) & UART_IIR_BITMASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Force BREAK character on UART line, output pin UARTx TXD is forced to logic 0 */
|
||
|
|
void IP_UART_ForceBreak(IP_USART_001_Type *LPC_UART)
|
||
|
|
{
|
||
|
|
LPC_UART->LCR |= UART_LCR_BREAK_EN;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get current value of Line Status register in UART peripheral */
|
||
|
|
uint8_t IP_UART_GetLineStatus(IP_USART_001_Type *LPC_UART)
|
||
|
|
{
|
||
|
|
return (LPC_UART->LSR) & UART_LSR_BITMASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Check whether if UART is busy or not */
|
||
|
|
FlagStatus IP_UART_CheckBusy(IP_USART_001_Type *LPC_UART)
|
||
|
|
{
|
||
|
|
if (LPC_UART->LSR & UART_LSR_TEMT) {
|
||
|
|
return RESET;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
return SET;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Enable/Disable transmission on UART TxD pin */
|
||
|
|
void IP_UART_TxCmd(IP_USART_001_Type *LPC_UART, UART_ID_Type UARTPort, FunctionalState NewState)
|
||
|
|
{
|
||
|
|
if (NewState == ENABLE) {
|
||
|
|
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
|
||
|
|
switch (UARTPort) {
|
||
|
|
#if defined(CHIP_LPC177X_8X)
|
||
|
|
case 4:
|
||
|
|
#else
|
||
|
|
case 0:
|
||
|
|
case 2:
|
||
|
|
case 3:
|
||
|
|
#endif
|
||
|
|
LPC_UART->TER2 = UART_TER2_TXEN;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
LPC_UART->TER1 = UART_TER1_TXEN;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
#if defined(CHIP_LPC177X_8X) || defined(CHIP_LPC18XX) || defined(CHIP_LPC43XX)
|
||
|
|
switch (UARTPort) {
|
||
|
|
#if defined(CHIP_LPC177X_8X)
|
||
|
|
case 4:
|
||
|
|
#else
|
||
|
|
case 0:
|
||
|
|
case 2:
|
||
|
|
case 3:
|
||
|
|
#endif
|
||
|
|
LPC_UART->TER2 &= (~UART_TER2_TXEN) & UART_TER2_BITMASK;
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
LPC_UART->TER1 &= (~UART_TER1_TXEN) & UART_TER1_BITMASK;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* UART FIFO functions ----------------------------------------------------------*/
|
||
|
|
/* Configure FIFO function on selected UART peripheral */
|
||
|
|
void IP_UART_FIFOConfig(IP_USART_001_Type *LPC_UART, UART_FIFO_CFG_Type *FIFOCfg)
|
||
|
|
{
|
||
|
|
uint8_t tmp = 0;
|
||
|
|
|
||
|
|
tmp |= UART_FCR_FIFO_EN;
|
||
|
|
switch (FIFOCfg->FIFO_Level) {
|
||
|
|
case UART_FIFO_TRGLEV0:
|
||
|
|
tmp |= UART_FCR_TRG_LEV0;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case UART_FIFO_TRGLEV1:
|
||
|
|
tmp |= UART_FCR_TRG_LEV1;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case UART_FIFO_TRGLEV2:
|
||
|
|
tmp |= UART_FCR_TRG_LEV2;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case UART_FIFO_TRGLEV3:
|
||
|
|
default:
|
||
|
|
tmp |= UART_FCR_TRG_LEV3;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (FIFOCfg->FIFO_ResetTxBuf == ENABLE) {
|
||
|
|
tmp |= UART_FCR_TX_RS;
|
||
|
|
}
|
||
|
|
if (FIFOCfg->FIFO_ResetRxBuf == ENABLE) {
|
||
|
|
tmp |= UART_FCR_RX_RS;
|
||
|
|
}
|
||
|
|
if (FIFOCfg->FIFO_DMAMode == ENABLE) {
|
||
|
|
tmp |= UART_FCR_DMAMODE_SEL;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* write to FIFO control register */
|
||
|
|
LPC_UART->FCR = tmp & UART_FCR_BITMASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Fills each UART_FIFOInitStruct member with its default value */
|
||
|
|
void IP_UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct)
|
||
|
|
{
|
||
|
|
UART_FIFOInitStruct->FIFO_DMAMode = DISABLE;
|
||
|
|
UART_FIFOInitStruct->FIFO_Level = UART_FIFO_TRGLEV0;
|
||
|
|
UART_FIFOInitStruct->FIFO_ResetRxBuf = ENABLE;
|
||
|
|
UART_FIFOInitStruct->FIFO_ResetTxBuf = ENABLE;
|
||
|
|
}
|