613 lines
20 KiB
C
613 lines
20 KiB
C
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/*
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* Copyright 2017-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_qtmr.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.qtmr"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address to be used to gate or ungate the module clock
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*
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* @param base Quad Timer peripheral base address
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*
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* @return The Quad Timer instance
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*/
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static uint32_t QTMR_GetInstance(TMR_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to Quad Timer bases for each instance. */
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static TMR_Type *const s_qtmrBases[] = TMR_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to Quad Timer clocks for each instance. */
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static const clock_ip_name_t s_qtmrClocks[] = TMR_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t QTMR_GetInstance(TMR_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_qtmrBases); instance++)
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{
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if (s_qtmrBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_qtmrBases));
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return instance;
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}
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/*!
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* brief Ungates the Quad Timer clock and configures the peripheral for basic operation.
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*
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* note This API should be called at the beginning of the application using the Quad Timer driver.
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*
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* param base Quad Timer peripheral base address
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* param channel Quad Timer channel number
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* param config Pointer to user's Quad Timer config structure
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*/
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void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config)
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{
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assert(NULL != config);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the module clock */
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CLOCK_EnableClock(s_qtmrClocks[QTMR_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Setup the counter sources */
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base->CHANNEL[channel].CTRL = (TMR_CTRL_PCS(config->primarySource) | TMR_CTRL_SCS(config->secondarySource));
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/* Setup the master mode operation */
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base->CHANNEL[channel].SCTRL =
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(TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode));
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/* Setup debug mode */
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base->CHANNEL[channel].CSCTRL = TMR_CSCTRL_DBG_EN(config->debugMode);
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base->CHANNEL[channel].FILT &= (uint16_t)(~(TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK));
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/* Setup input filter */
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base->CHANNEL[channel].FILT =
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(TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod));
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}
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/*!
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* brief Stops the counter and gates the Quad Timer clock
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*
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* param base Quad Timer peripheral base address
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* param channel Quad Timer channel number
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*/
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void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)
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{
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/* Stop the counter */
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base->CHANNEL[channel].CTRL &= (uint16_t)(~TMR_CTRL_CM_MASK);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the module clock */
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CLOCK_DisableClock(s_qtmrClocks[QTMR_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Fill in the Quad Timer config struct with the default settings
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*
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* The default values are:
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* code
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* config->debugMode = kQTMR_RunNormalInDebug;
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* config->enableExternalForce = false;
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* config->enableMasterMode = false;
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* config->faultFilterCount = 0;
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* config->faultFilterPeriod = 0;
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* config->primarySource = kQTMR_ClockDivide_2;
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* config->secondarySource = kQTMR_Counter0InputPin;
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* endcode
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* param config Pointer to user's Quad Timer config structure.
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*/
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void QTMR_GetDefaultConfig(qtmr_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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/* Halt counter during debug mode */
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config->debugMode = kQTMR_RunNormalInDebug;
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/* Another counter cannot force state of OFLAG signal */
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config->enableExternalForce = false;
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/* Compare function's output from this counter is not broadcast to other counters */
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config->enableMasterMode = false;
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/* Fault filter count is set to 0 */
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config->faultFilterCount = 0;
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/* Fault filter period is set to 0 which disables the fault filter */
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config->faultFilterPeriod = 0;
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/* Primary count source is IP bus clock divide by 2 */
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config->primarySource = kQTMR_ClockDivide_2;
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/* Secondary count source is counter 0 input pin */
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config->secondarySource = kQTMR_Counter0InputPin;
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}
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/*!
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* brief Sets up Quad timer module for PWM signal output.
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*
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* The function initializes the timer module according to the parameters passed in by the user. The
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* function also sets up the value compare registers to match the PWM signal requirements.
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*
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* param base Quad Timer peripheral base address
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* param channel Quad Timer channel number
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* param pwmFreqHz PWM signal frequency in Hz
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* param dutyCyclePercent PWM pulse width, value should be between 0 to 100
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* 0=inactive signal(0% duty cycle)...
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* 100=active signal (100% duty cycle)
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* param outputPolarity true: invert polarity of the output signal, false: no inversion
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* param srcClock_Hz Main counter clock in Hz.
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*
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* return Returns an error if there was error setting up the signal.
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*/
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status_t QTMR_SetupPwm(TMR_Type *base,
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qtmr_channel_selection_t channel,
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uint32_t pwmFreqHz,
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uint8_t dutyCyclePercent,
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bool outputPolarity,
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uint32_t srcClock_Hz)
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{
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uint32_t periodCount, highCount, lowCount;
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uint16_t reg;
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status_t status;
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if (dutyCyclePercent <= 100U)
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{
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/* Set OFLAG pin for output mode and force out a low on the pin */
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base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK);
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/* Counter values to generate a PWM signal */
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periodCount = srcClock_Hz / pwmFreqHz;
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highCount = periodCount * dutyCyclePercent / 100U;
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lowCount = periodCount - highCount;
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if (highCount > 0U)
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{
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highCount -= 1U;
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}
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if (lowCount > 0U)
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{
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lowCount -= 1U;
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}
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/* This should not be a 16-bit overflow value. If it is, change to a larger divider for clock source. */
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assert(highCount <= 0xFFFFU);
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assert(lowCount <= 0xFFFFU);
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/* Setup the compare registers for PWM output */
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base->CHANNEL[channel].COMP1 = (uint16_t)lowCount;
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base->CHANNEL[channel].COMP2 = (uint16_t)highCount;
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/* Setup the pre-load registers for PWM output */
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base->CHANNEL[channel].CMPLD1 = (uint16_t)lowCount;
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base->CHANNEL[channel].CMPLD2 = (uint16_t)highCount;
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reg = base->CHANNEL[channel].CSCTRL;
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/* Setup the compare load control for COMP1 and COMP2.
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* Load COMP1 when CSCTRL[TCF2] is asserted, load COMP2 when CSCTRL[TCF1] is asserted
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*/
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reg &= (uint16_t)(~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK));
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reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1));
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base->CHANNEL[channel].CSCTRL = reg;
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if (outputPolarity)
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{
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/* Invert the polarity */
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base->CHANNEL[channel].SCTRL |= TMR_SCTRL_OPS_MASK;
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}
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else
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{
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/* True polarity, no inversion */
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base->CHANNEL[channel].SCTRL &= ~(uint16_t)TMR_SCTRL_OPS_MASK;
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}
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reg = base->CHANNEL[channel].CTRL;
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reg &= ~(uint16_t)TMR_CTRL_OUTMODE_MASK;
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/* Count until compare value is reached and re-initialize the counter, toggle OFLAG output
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* using alternating compare register
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*/
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reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg));
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base->CHANNEL[channel].CTRL = reg;
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status = kStatus_Success;
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}
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else
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{
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/* Invalid dutycycle */
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status = kStatus_Fail;
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}
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return status;
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}
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/*!
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* brief Allows the user to count the source clock cycles until a capture event arrives.
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*
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* The count is stored in the capture register.
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*
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* param base Quad Timer peripheral base address
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* param channel Quad Timer channel number
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* param capturePin Pin through which we receive the input signal to trigger the capture
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* param inputPolarity true: invert polarity of the input signal, false: no inversion
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* param reloadOnCapture true: reload the counter when an input capture occurs, false: no reload
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* param captureMode Specifies which edge of the input signal triggers a capture
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*/
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void QTMR_SetupInputCapture(TMR_Type *base,
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qtmr_channel_selection_t channel,
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qtmr_input_source_t capturePin,
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bool inputPolarity,
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bool reloadOnCapture,
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qtmr_input_capture_edge_t captureMode)
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{
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uint16_t reg;
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/* Clear the prior value for the input source for capture */
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reg = base->CHANNEL[channel].CTRL & (uint16_t)(~TMR_CTRL_SCS_MASK);
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/* Set the new input source */
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reg |= TMR_CTRL_SCS(capturePin);
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base->CHANNEL[channel].CTRL = reg;
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/* Clear the prior values for input polarity, capture mode. Set the external pin as input */
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reg = base->CHANNEL[channel].SCTRL &
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(uint16_t)(~(TMR_SCTRL_IPS_MASK | TMR_SCTRL_CAPTURE_MODE_MASK | TMR_SCTRL_OEN_MASK));
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/* Set the new values */
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reg |= (TMR_SCTRL_IPS(inputPolarity) | TMR_SCTRL_CAPTURE_MODE(captureMode));
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base->CHANNEL[channel].SCTRL = reg;
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/* Setup if counter should reload when a capture occurs */
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if (reloadOnCapture)
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{
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base->CHANNEL[channel].CSCTRL |= TMR_CSCTRL_ROC_MASK;
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}
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else
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{
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base->CHANNEL[channel].CSCTRL &= (uint16_t)(~TMR_CSCTRL_ROC_MASK);
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}
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}
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/*!
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* brief Enables the selected Quad Timer interrupts
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*
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* param base Quad Timer peripheral base address
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* param channel Quad Timer channel number
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* param mask The interrupts to enable. This is a logical OR of members of the
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* enumeration ::qtmr_interrupt_enable_t
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*/
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void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
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{
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uint16_t reg;
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reg = base->CHANNEL[channel].SCTRL;
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/* Compare interrupt */
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if ((mask & (uint16_t)kQTMR_CompareInterruptEnable) != 0UL)
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{
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reg |= TMR_SCTRL_TCFIE_MASK;
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}
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/* Overflow interrupt */
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if ((mask & (uint16_t)kQTMR_OverflowInterruptEnable) != 0UL)
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{
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reg |= TMR_SCTRL_TOFIE_MASK;
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}
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/* Input edge interrupt */
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if ((mask & (uint16_t)kQTMR_EdgeInterruptEnable) != 0UL)
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{
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/* Restriction: Do not set both SCTRL[IEFIE] and DMA[IEFDE] */
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base->CHANNEL[channel].DMA &= ~(uint16_t)TMR_DMA_IEFDE_MASK;
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reg |= TMR_SCTRL_IEFIE_MASK;
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}
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base->CHANNEL[channel].SCTRL = reg;
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reg = base->CHANNEL[channel].CSCTRL;
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/* Compare 1 interrupt */
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if ((mask & (uint16_t)kQTMR_Compare1InterruptEnable) != 0UL)
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{
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reg |= TMR_CSCTRL_TCF1EN_MASK;
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}
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/* Compare 2 interrupt */
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if ((mask & (uint16_t)kQTMR_Compare2InterruptEnable) != 0UL)
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{
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reg |= TMR_CSCTRL_TCF2EN_MASK;
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}
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base->CHANNEL[channel].CSCTRL = reg;
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}
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/*!
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* brief Disables the selected Quad Timer interrupts
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*
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* param base Quad Timer peripheral base addres
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* param channel Quad Timer channel number
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* param mask The interrupts to enable. This is a logical OR of members of the
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* enumeration ::qtmr_interrupt_enable_t
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*/
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void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
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{
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uint16_t reg;
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reg = base->CHANNEL[channel].SCTRL;
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/* Compare interrupt */
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if ((mask & (uint16_t)kQTMR_CompareInterruptEnable) != 0UL)
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{
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reg &= (uint16_t)(~TMR_SCTRL_TCFIE_MASK);
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}
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/* Overflow interrupt */
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if ((mask & (uint16_t)kQTMR_OverflowInterruptEnable) != 0UL)
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{
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reg &= (uint16_t)(~TMR_SCTRL_TOFIE_MASK);
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||
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|
}
|
||
|
|
/* Input edge interrupt */
|
||
|
|
if ((mask & (uint16_t)kQTMR_EdgeInterruptEnable) != 0UL)
|
||
|
|
{
|
||
|
|
reg &= (uint16_t)(~TMR_SCTRL_IEFIE_MASK);
|
||
|
|
}
|
||
|
|
base->CHANNEL[channel].SCTRL = reg;
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].CSCTRL;
|
||
|
|
/* Compare 1 interrupt */
|
||
|
|
if ((mask & (uint16_t)kQTMR_Compare1InterruptEnable) != 0UL)
|
||
|
|
{
|
||
|
|
reg &= ~(uint16_t)TMR_CSCTRL_TCF1EN_MASK;
|
||
|
|
}
|
||
|
|
/* Compare 2 interrupt */
|
||
|
|
if ((mask & (uint16_t)kQTMR_Compare2InterruptEnable) != 0UL)
|
||
|
|
{
|
||
|
|
reg &= ~(uint16_t)TMR_CSCTRL_TCF2EN_MASK;
|
||
|
|
}
|
||
|
|
base->CHANNEL[channel].CSCTRL = reg;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Gets the enabled Quad Timer interrupts
|
||
|
|
*
|
||
|
|
* param base Quad Timer peripheral base address
|
||
|
|
* param channel Quad Timer channel number
|
||
|
|
*
|
||
|
|
* return The enabled interrupts. This is the logical OR of members of the
|
||
|
|
* enumeration ::qtmr_interrupt_enable_t
|
||
|
|
*/
|
||
|
|
uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel)
|
||
|
|
{
|
||
|
|
uint32_t enabledInterrupts = 0;
|
||
|
|
uint16_t reg;
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].SCTRL;
|
||
|
|
/* Compare interrupt */
|
||
|
|
if ((reg & TMR_SCTRL_TCFIE_MASK) != 0U)
|
||
|
|
{
|
||
|
|
enabledInterrupts |= (uint32_t)kQTMR_CompareFlag;
|
||
|
|
}
|
||
|
|
/* Overflow interrupt */
|
||
|
|
if ((reg & TMR_SCTRL_TOFIE_MASK) != 0U)
|
||
|
|
{
|
||
|
|
enabledInterrupts |= (uint32_t)kQTMR_OverflowInterruptEnable;
|
||
|
|
}
|
||
|
|
/* Input edge interrupt */
|
||
|
|
if ((reg & TMR_SCTRL_IEFIE_MASK) != 0U)
|
||
|
|
{
|
||
|
|
enabledInterrupts |= (uint32_t)kQTMR_EdgeInterruptEnable;
|
||
|
|
}
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].CSCTRL;
|
||
|
|
/* Compare 1 interrupt */
|
||
|
|
if ((reg & TMR_CSCTRL_TCF1EN_MASK) != 0U)
|
||
|
|
{
|
||
|
|
enabledInterrupts |= (uint32_t)kQTMR_Compare1InterruptEnable;
|
||
|
|
}
|
||
|
|
/* Compare 2 interrupt */
|
||
|
|
if ((reg & TMR_CSCTRL_TCF2EN_MASK) != 0U)
|
||
|
|
{
|
||
|
|
enabledInterrupts |= (uint32_t)kQTMR_Compare2InterruptEnable;
|
||
|
|
}
|
||
|
|
|
||
|
|
return enabledInterrupts;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Gets the Quad Timer status flags
|
||
|
|
*
|
||
|
|
* param base Quad Timer peripheral base address
|
||
|
|
* param channel Quad Timer channel number
|
||
|
|
*
|
||
|
|
* return The status flags. This is the logical OR of members of the
|
||
|
|
* enumeration ::qtmr_status_flags_t
|
||
|
|
*/
|
||
|
|
uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)
|
||
|
|
{
|
||
|
|
uint32_t statusFlags = 0;
|
||
|
|
uint16_t reg;
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].SCTRL;
|
||
|
|
/* Timer compare flag */
|
||
|
|
if ((reg & TMR_SCTRL_TCF_MASK) != 0U)
|
||
|
|
{
|
||
|
|
statusFlags |= (uint32_t)kQTMR_CompareFlag;
|
||
|
|
}
|
||
|
|
/* Timer overflow flag */
|
||
|
|
if ((reg & TMR_SCTRL_TOF_MASK) != 0U)
|
||
|
|
{
|
||
|
|
statusFlags |= (uint32_t)kQTMR_OverflowFlag;
|
||
|
|
}
|
||
|
|
/* Input edge flag */
|
||
|
|
if ((reg & TMR_SCTRL_IEF_MASK) != 0U)
|
||
|
|
{
|
||
|
|
statusFlags |= (uint32_t)kQTMR_EdgeFlag;
|
||
|
|
}
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].CSCTRL;
|
||
|
|
/* Compare 1 flag */
|
||
|
|
if ((reg & TMR_CSCTRL_TCF1_MASK) != 0U)
|
||
|
|
{
|
||
|
|
statusFlags |= (uint32_t)kQTMR_Compare1Flag;
|
||
|
|
}
|
||
|
|
/* Compare 2 flag */
|
||
|
|
if ((reg & TMR_CSCTRL_TCF2_MASK) != 0U)
|
||
|
|
{
|
||
|
|
statusFlags |= (uint32_t)kQTMR_Compare2Flag;
|
||
|
|
}
|
||
|
|
|
||
|
|
return statusFlags;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Clears the Quad Timer status flags.
|
||
|
|
*
|
||
|
|
* param base Quad Timer peripheral base address
|
||
|
|
* param channel Quad Timer channel number
|
||
|
|
* param mask The status flags to clear. This is a logical OR of members of the
|
||
|
|
* enumeration ::qtmr_status_flags_t
|
||
|
|
*/
|
||
|
|
void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
|
||
|
|
{
|
||
|
|
uint16_t reg;
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].SCTRL;
|
||
|
|
/* Timer compare flag */
|
||
|
|
if ((mask & (uint32_t)kQTMR_CompareFlag) != 0U)
|
||
|
|
{
|
||
|
|
reg &= (uint16_t)(~TMR_SCTRL_TCF_MASK);
|
||
|
|
}
|
||
|
|
/* Timer overflow flag */
|
||
|
|
if ((mask & (uint32_t)kQTMR_OverflowFlag) != 0U)
|
||
|
|
{
|
||
|
|
reg &= (uint16_t)(~TMR_SCTRL_TOF_MASK);
|
||
|
|
}
|
||
|
|
/* Input edge flag */
|
||
|
|
if ((mask & (uint32_t)kQTMR_EdgeFlag) != 0U)
|
||
|
|
{
|
||
|
|
reg &= (uint16_t)(~TMR_SCTRL_IEF_MASK);
|
||
|
|
}
|
||
|
|
base->CHANNEL[channel].SCTRL = reg;
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].CSCTRL;
|
||
|
|
/* Compare 1 flag */
|
||
|
|
if ((mask & (uint32_t)kQTMR_Compare1Flag) != 0U)
|
||
|
|
{
|
||
|
|
reg &= ~(uint16_t)TMR_CSCTRL_TCF1_MASK;
|
||
|
|
}
|
||
|
|
/* Compare 2 flag */
|
||
|
|
if ((mask & (uint32_t)kQTMR_Compare2Flag) != 0U)
|
||
|
|
{
|
||
|
|
reg &= ~(uint16_t)TMR_CSCTRL_TCF2_MASK;
|
||
|
|
}
|
||
|
|
base->CHANNEL[channel].CSCTRL = reg;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Sets the timer period in ticks.
|
||
|
|
*
|
||
|
|
* Timers counts from initial value till it equals the count value set here. The counter
|
||
|
|
* will then reinitialize to the value specified in the Load register.
|
||
|
|
*
|
||
|
|
* note
|
||
|
|
* 1. This function will write the time period in ticks to COMP1 or COMP2 register
|
||
|
|
* depending on the count direction
|
||
|
|
* 2. User can call the utility macros provided in fsl_common.h to convert to ticks
|
||
|
|
* 3. This function supports cases, providing only primary source clock without secondary source clock.
|
||
|
|
*
|
||
|
|
* param base Quad Timer peripheral base address
|
||
|
|
* param channel Quad Timer channel number
|
||
|
|
* param ticks Timer period in units of ticks
|
||
|
|
*/
|
||
|
|
void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)
|
||
|
|
{
|
||
|
|
/* Set the length bit to reinitialize the counters on a match */
|
||
|
|
base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK;
|
||
|
|
|
||
|
|
if ((base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK) != 0U)
|
||
|
|
{
|
||
|
|
/* Counting down */
|
||
|
|
base->CHANNEL[channel].COMP2 = ticks;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* Counting up */
|
||
|
|
base->CHANNEL[channel].COMP1 = ticks;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Enable the Quad Timer DMA.
|
||
|
|
*
|
||
|
|
* param base Quad Timer peripheral base address
|
||
|
|
* param channel Quad Timer channel number
|
||
|
|
* param mask The DMA to enable. This is a logical OR of members of the
|
||
|
|
* enumeration ::qtmr_dma_enable_t
|
||
|
|
*/
|
||
|
|
void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
|
||
|
|
{
|
||
|
|
uint16_t reg;
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].DMA;
|
||
|
|
/* Input Edge Flag DMA Enable */
|
||
|
|
if ((mask & (uint32_t)kQTMR_InputEdgeFlagDmaEnable) != 0U)
|
||
|
|
{
|
||
|
|
/* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */
|
||
|
|
base->CHANNEL[channel].SCTRL &= (uint16_t)(~TMR_SCTRL_IEFIE_MASK);
|
||
|
|
reg |= TMR_DMA_IEFDE_MASK;
|
||
|
|
}
|
||
|
|
/* Comparator Preload Register 1 DMA Enable */
|
||
|
|
if ((mask & (uint32_t)kQTMR_ComparatorPreload1DmaEnable) != 0U)
|
||
|
|
{
|
||
|
|
reg |= TMR_DMA_CMPLD1DE_MASK;
|
||
|
|
}
|
||
|
|
/* Comparator Preload Register 2 DMA Enable */
|
||
|
|
if ((mask & (uint32_t)kQTMR_ComparatorPreload2DmaEnable) != 0U)
|
||
|
|
{
|
||
|
|
reg |= TMR_DMA_CMPLD2DE_MASK;
|
||
|
|
}
|
||
|
|
base->CHANNEL[channel].DMA = reg;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* brief Disable the Quad Timer DMA.
|
||
|
|
*
|
||
|
|
* param base Quad Timer peripheral base address
|
||
|
|
* param channel Quad Timer channel number
|
||
|
|
* param mask The DMA to enable. This is a logical OR of members of the
|
||
|
|
* enumeration ::qtmr_dma_enable_t
|
||
|
|
*/
|
||
|
|
void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
|
||
|
|
{
|
||
|
|
uint16_t reg;
|
||
|
|
|
||
|
|
reg = base->CHANNEL[channel].DMA;
|
||
|
|
/* Input Edge Flag DMA Enable */
|
||
|
|
if ((mask & (uint32_t)kQTMR_InputEdgeFlagDmaEnable) != 0U)
|
||
|
|
{
|
||
|
|
reg &= ~(uint16_t)TMR_DMA_IEFDE_MASK;
|
||
|
|
}
|
||
|
|
/* Comparator Preload Register 1 DMA Enable */
|
||
|
|
if ((mask & (uint32_t)kQTMR_ComparatorPreload1DmaEnable) != 0U)
|
||
|
|
{
|
||
|
|
reg &= ~(uint16_t)TMR_DMA_CMPLD1DE_MASK;
|
||
|
|
}
|
||
|
|
/* Comparator Preload Register 2 DMA Enable */
|
||
|
|
if ((mask & (uint32_t)kQTMR_ComparatorPreload2DmaEnable) != 0U)
|
||
|
|
{
|
||
|
|
reg &= ~(uint16_t)TMR_DMA_CMPLD2DE_MASK;
|
||
|
|
}
|
||
|
|
base->CHANNEL[channel].DMA = reg;
|
||
|
|
}
|