353 lines
14 KiB
C
353 lines
14 KiB
C
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/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_ADC_ETC_H_
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#define _FSL_ADC_ETC_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup adc_etc
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief ADC_ETC driver version */
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#define FSL_ADC_ETC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
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/*! @brief The mask of status flags cleared by writing 1. */
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#define ADC_ETC_DMA_CTRL_TRGn_REQ_MASK 0xFF0000U
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/*!
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* @brief ADC_ETC customized status flags mask.
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*/
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enum _adc_etc_status_flag_mask
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{
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kADC_ETC_Done0StatusFlagMask = 1U << 0U,
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kADC_ETC_Done1StatusFlagMask = 1U << 1U,
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kADC_ETC_Done2StatusFlagMask = 1U << 2U,
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#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
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kADC_ETC_Done3StatusFlagMask = 1U << 3U,
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kADC_ETC_ErrorStatusFlagMask = 1U << 4U,
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#else
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kADC_ETC_ErrorStatusFlagMask = 1U << 3U,
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#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
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};
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/*!
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* @brief External triggers sources.
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*/
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typedef enum _adc_etc_external_trigger_source
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{
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/* External XBAR sources. Support HW or SW mode. */
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kADC_ETC_Trg0TriggerSource = 0U, /* External XBAR trigger0 source. */
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kADC_ETC_Trg1TriggerSource = 1U, /* External XBAR trigger1 source. */
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kADC_ETC_Trg2TriggerSource = 2U, /* External XBAR trigger2 source. */
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kADC_ETC_Trg3TriggerSource = 3U, /* External XBAR trigger3 source. */
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kADC_ETC_Trg4TriggerSource = 4U, /* External XBAR trigger4 source. */
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kADC_ETC_Trg5TriggerSource = 5U, /* External XBAR trigger5 source. */
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kADC_ETC_Trg6TriggerSource = 6U, /* External XBAR trigger6 source. */
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kADC_ETC_Trg7TriggerSource = 7U, /* External XBAR trigger7 source. */
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/* External TSC sources. Only support HW mode. */
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kADC_ETC_TSC0TriggerSource = 8U, /* External TSC trigger0 source. */
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kADC_ETC_TSC1TriggerSource = 9U, /* External TSC trigger1 source. */
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} adc_etc_external_trigger_source_t;
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/*!
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* @brief Interrupt enable/disable mask.
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*/
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typedef enum _adc_etc_interrupt_enable
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{
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#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
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kADC_ETC_Done0InterruptEnable = 0U, /* Enable the DONE0 interrupt when ADC conversions complete. */
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kADC_ETC_Done1InterruptEnable = 1U, /* Enable the DONE1 interrupt when ADC conversions complete. */
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kADC_ETC_Done2InterruptEnable = 2U, /* Enable the DONE2 interrupt when ADC conversions complete. */
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kADC_ETC_Done3InterruptEnable = 3U, /* Enable the DONE3 interrupt when ADC conversions complete. */
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#else
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kADC_ETC_InterruptDisable = 0U, /* Disable the ADC_ETC interrupt. */
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kADC_ETC_Done0InterruptEnable = 1U, /* Enable the DONE0 interrupt when ADC conversions complete. */
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kADC_ETC_Done1InterruptEnable = 2U, /* Enable the DONE1 interrupt when ADC conversions complete. */
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kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
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#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
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} adc_etc_interrupt_enable_t;
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#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
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/*!
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* @brief DMA mode selection.
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*/
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typedef enum _adc_etc_dma_mode_selection
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{
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kADC_ETC_TrigDMAWithLatchedSignal =
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0U, /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
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kADC_ETC_TrigDMAWithPulsedSignal = 1U, /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
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} adc_etc_dma_mode_selection_t;
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#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
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/*!
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* @brief ADC_ETC configuration.
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*/
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typedef struct _adc_etc_config
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{
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#if ((!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)) || \
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(!(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)))
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bool enableTSCBypass; /* If bypass TSC, TSC would trigger ADC directly.
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Otherwise TSC would trigger ADC through ADC_ETC. */
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#endif
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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bool enableTSC0Trigger; /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
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bool enableTSC1Trigger; /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
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#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
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adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */
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#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG)
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uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG */
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#if !(defined(FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG) && FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG)
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uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
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#endif /* FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG */
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uint32_t clockPreDivider; /* Pre-divider for trig delay and interval. Available range is 0-255.
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Clock would be divided by (clockPreDivider+1). */
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uint32_t XBARtriggerMask; /* Enable the corresponding trigger source. Available range is trigger0:0x01 to
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trigger7:0x80
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For example, XBARtriggerMask = 0x7U, which means trigger0, trigger1 and trigger2 is
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enabled. */
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} adc_etc_config_t;
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/*!
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* @brief ADC_ETC trigger chain configuration.
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*/
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typedef struct _adc_etc_trigger_chain_config
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{
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bool enableB2BMode; /* Enable ADC_ETC BackToBack mode. when not enabled B2B mode,
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wait until interval delay is reached. */
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uint32_t ADCHCRegisterSelect; /* Select relevant ADC_HCx register to trigger. 1U : HC0, 2U: HC1, 4U: HC2 ... */
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uint32_t ADCChannelSelect; /* Select ADC sample channel. */
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adc_etc_interrupt_enable_t InterruptEnable; /* Enable/disable Interrupt. */
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#if defined(FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN) && FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN
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bool enableIrq; /* Enable IRQ for selected interrupt enable choice in "InterruptEnable" */
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#endif /* FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN */
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} adc_etc_trigger_chain_config_t;
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/*!
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* @brief ADC_ETC trigger configuration.
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*/
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typedef struct _adc_etc_trigger_config
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{
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bool enableSyncMode; /* Enable the sync Mode, In SyncMode ADC1 and ADC2 are controlled by the same trigger source.
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In AsyncMode ADC1 and ADC2 are controlled by separate trigger source. */
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bool enableSWTriggerMode; /* Enable the sofware trigger mode. */
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uint32_t triggerChainLength; /* TRIG chain length to the ADC. 0: Trig length is 1. ... 7: Trig length is 8. */
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uint32_t triggerPriority; /* External trigger priority, 7 is highest, 0 is lowest. */
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uint32_t sampleIntervalDelay; /* Set sampling interval delay. */
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uint32_t initialDelay; /* Set trigger initial delay. */
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} adc_etc_trigger_config_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Initialization
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* @{
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*/
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/*!
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* @brief Initialize the ADC_ETC module.
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*
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* @param base ADC_ETC peripheral base address.
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* @param config Pointer to "adc_etc_config_t" structure.
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*/
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void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config);
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/*!
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* @brief De-Initialize the ADC_ETC module.
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*
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* @param base ADC_ETC peripheral base address.
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*/
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void ADC_ETC_Deinit(ADC_ETC_Type *base);
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/*!
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* @brief Gets an available pre-defined settings for the ADC_ETC's configuration.
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* This function initializes the ADC_ETC's configuration structure with available settings. The default values are:
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* @code
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* config->enableTSCBypass = true;
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* config->enableTSC0Trigger = false;
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* config->enableTSC1Trigger = false;
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* config->TSC0triggerPriority = 0U;
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* config->TSC1triggerPriority = 0U;
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* config->clockPreDivider = 0U;
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* config->XBARtriggerMask = 0U;
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* @endcode
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*
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* @param config Pointer to "adc_etc_config_t" structure.
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*/
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void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config);
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/*!
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* @brief Set the external XBAR trigger configuration.
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*
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* @param base ADC_ETC peripheral base address.
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* @param triggerGroup Trigger group index.
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* @param config Pointer to "adc_etc_trigger_config_t" structure.
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*/
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void ADC_ETC_SetTriggerConfig(ADC_ETC_Type *base, uint32_t triggerGroup, const adc_etc_trigger_config_t *config);
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/*!
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* @brief Set the external XBAR trigger chain configuration.
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* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means Trigger0 source's chain1 would be
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* configurated.
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*
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* @param base ADC_ETC peripheral base address.
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* @param triggerGroup Trigger group index. Available number is 0~7.
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* @param chainGroup Trigger chain group index. Available number is 0~7.
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* @param config Pointer to "adc_etc_trigger_chain_config_t" structure.
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*/
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void ADC_ETC_SetTriggerChainConfig(ADC_ETC_Type *base,
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uint32_t triggerGroup,
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uint32_t chainGroup,
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const adc_etc_trigger_chain_config_t *config);
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/*!
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* @brief Gets the interrupt status flags of external XBAR and TSC triggers.
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*
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* @param base ADC_ETC peripheral base address.
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* @param sourceIndex trigger source index.
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*
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* @return Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
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*/
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uint32_t ADC_ETC_GetInterruptStatusFlags(ADC_ETC_Type *base, adc_etc_external_trigger_source_t sourceIndex);
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/*!
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* @brief Clears the ADC_ETC's interrupt status falgs.
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*
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* @param base ADC_ETC peripheral base address.
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* @param sourceIndex trigger source index.
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* @param mask Status flags mask of trigger. Refer to "_adc_etc_status_flag_mask".
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*/
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void ADC_ETC_ClearInterruptStatusFlags(ADC_ETC_Type *base,
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adc_etc_external_trigger_source_t sourceIndex,
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uint32_t mask);
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/*!
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* @brief Enable the DMA corresponding to each trigger source.
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*
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* @param base ADC_ETC peripheral base address.
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* @param triggerGroup Trigger group index. Available number is 0~7.
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*/
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static inline void ADC_ETC_EnableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
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{
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/* Avoid clearing status flags at the same time. */
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base->DMA_CTRL = (base->DMA_CTRL | ((uint32_t)ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << (uint32_t)triggerGroup)) &
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~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
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}
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/*!
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* @brief Disable the DMA corresponding to each trigger sources.
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*
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* @param base ADC_ETC peripheral base address.
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* @param triggerGroup Trigger group index. Available number is 0~7.
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*/
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static inline void ADC_ETC_DisableDMA(ADC_ETC_Type *base, uint32_t triggerGroup)
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{
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/* Avoid clearing status flags at the same time. */
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base->DMA_CTRL = (base->DMA_CTRL & ~((uint32_t)ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK << (uint32_t)triggerGroup)) &
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~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK;
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}
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/*!
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* @brief Get the DMA request status falgs. Only external XBAR sources support DMA request.
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*
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* @param base ADC_ETC peripheral base address.
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* @return Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
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* trigger7:0x80.
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*/
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static inline uint32_t ADC_ETC_GetDMAStatusFlags(ADC_ETC_Type *base)
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{
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return (((base->DMA_CTRL) & ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) >> ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
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}
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/*!
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* @brief Clear the DMA request status falgs. Only external XBAR sources support DMA request.
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*
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* @param base ADC_ETC peripheral base address.
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* @param mask Mask of external XBAR tirgger's DMA request asserted flags. Available range is trigger0:0x01 to
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* trigger7:0x80.
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*/
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static inline void ADC_ETC_ClearDMAStatusFlags(ADC_ETC_Type *base, uint32_t mask)
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{
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base->DMA_CTRL = ((base->DMA_CTRL) & ~ADC_ETC_DMA_CTRL_TRGn_REQ_MASK) | (mask << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT);
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}
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/*!
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* @brief When enable, all logical will be reset.
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*
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* @param base ADC_ETC peripheral base address.
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* @param enable Enable/Disable the software reset.
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*/
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static inline void ADC_ETC_DoSoftwareReset(ADC_ETC_Type *base, bool enable)
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{
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if (enable)
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||
|
|
{
|
||
|
|
base->CTRL |= ADC_ETC_CTRL_SOFTRST_MASK;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
base->CTRL &= ~ADC_ETC_CTRL_SOFTRST_MASK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Do software trigger corresponding to each XBAR trigger sources.
|
||
|
|
* Each XBAR trigger sources can be configured as HW or SW trigger mode. In hardware trigger mode,
|
||
|
|
* trigger source is from XBAR. In software mode, trigger source is from software tigger. TSC trigger sources
|
||
|
|
* can only work in hardware trigger mode.
|
||
|
|
*
|
||
|
|
* @param base ADC_ETC peripheral base address.
|
||
|
|
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||
|
|
*/
|
||
|
|
static inline void ADC_ETC_DoSoftwareTrigger(ADC_ETC_Type *base, uint32_t triggerGroup)
|
||
|
|
{
|
||
|
|
assert(triggerGroup < ADC_ETC_TRIGn_CTRL_COUNT);
|
||
|
|
|
||
|
|
base->TRIG[triggerGroup].TRIGn_CTRL |= ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*!
|
||
|
|
* @brief Get ADC conversion result from external XBAR sources.
|
||
|
|
* For example, if triggerGroup is set to 0U and chainGroup is set to 1U, which means the API would
|
||
|
|
* return Trigger0 source's chain1 conversion result.
|
||
|
|
*
|
||
|
|
* @param base ADC_ETC peripheral base address.
|
||
|
|
* @param triggerGroup Trigger group index. Available number is 0~7.
|
||
|
|
* @param chainGroup Trigger chain group index. Available number is 0~7.
|
||
|
|
* @return ADC conversion result value.
|
||
|
|
*/
|
||
|
|
uint32_t ADC_ETC_GetADCConversionValue(ADC_ETC_Type *base, uint32_t triggerGroup, uint32_t chainGroup);
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
#if defined(__cplusplus)
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* @} */
|
||
|
|
|
||
|
|
#endif /* _FSL_ADC_ETC_H_ */
|