298 lines
8.2 KiB
C
298 lines
8.2 KiB
C
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/*
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* File : spi.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2017-12-04 Haley the first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "am_mcu_apollo.h"
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#include "board.h"
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#include "spi.h"
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/* SPI1 */
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#define AM_SPI0_IOM_INST 0
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#define SPI0_GPIO_SCK 5
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#define SPI0_GPIO_CFG_SCK AM_HAL_PIN_5_M0SCK
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#define SPI0_GPIO_MISO 6
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#define SPI0_GPIO_CFG_MISO AM_HAL_PIN_6_M0MISO
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#define SPI0_GPIO_MOSI 7
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#define SPI0_GPIO_CFG_MOSI AM_HAL_PIN_7_M0MOSI
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/* SPI2 */
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#define AM_SPI1_IOM_INST 1
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static am_hal_iom_config_t g_sIOMConfig =
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{
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AM_HAL_IOM_SPIMODE, // ui32InterfaceMode
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AM_HAL_IOM_8MHZ, // ui32ClockFrequency
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0, // bSPHA
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0, // bSPOL
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4, // ui8WriteThreshold
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60, // ui8ReadThreshold
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};
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/* AM spi driver */
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struct am_spi_bus
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{
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struct rt_spi_bus parent;
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rt_uint32_t u32Module;
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};
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//connect am drv to rt drv.
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static rt_err_t configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration)
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{
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struct am_spi_bus * am_spi_bus = (struct am_spi_bus *)device->bus;
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rt_uint32_t max_hz = configuration->max_hz;
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if(max_hz >= 8000000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_8MHZ;
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}
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else if(max_hz >= 6000000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_6MHZ;
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}
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else if(max_hz >= 4000000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_4MHZ;
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}
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else if(max_hz >= 3000000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_3MHZ;
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}
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else if(max_hz >= 2000000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_2MHZ;
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}
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else if(max_hz >= 1500000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_1_5MHZ;
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}
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else if(max_hz >= 1000000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_1MHZ;
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}
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else if(max_hz >= 750000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_750KHZ;
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}
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else if(max_hz >= 500000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_500KHZ;
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}
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else if(max_hz >= 400000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_400KHZ;
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}
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else if(max_hz >= 375000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_375KHZ;
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}
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else if(max_hz >= 250000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_250KHZ;
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}
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else if(max_hz >= 100000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_100KHZ;
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}
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else if(max_hz >= 50000)
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_50KHZ;
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}
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else
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{
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g_sIOMConfig.ui32ClockFrequency = AM_HAL_IOM_10KHZ;
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}
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/* CPOL */
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if(configuration->mode & RT_SPI_CPOL)
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{
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g_sIOMConfig.bSPOL = 1;
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}
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else
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{
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g_sIOMConfig.bSPOL = 0;
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}
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/* CPHA */
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if(configuration->mode & RT_SPI_CPHA)
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{
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g_sIOMConfig.bSPHA= 1;
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}
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else
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{
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g_sIOMConfig.bSPHA= 0;
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}
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/* init SPI */
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am_hal_iom_disable(am_spi_bus->u32Module);
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am_hal_iom_pwrctrl_enable(am_spi_bus->u32Module);
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am_hal_iom_config(am_spi_bus->u32Module, &g_sIOMConfig);
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am_hal_iom_enable(am_spi_bus->u32Module);
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return RT_EOK;
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};
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static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* message)
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{
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struct am_spi_bus * am_spi_bus = (struct am_spi_bus *)device->bus;
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//struct rt_spi_configuration * config = &device->config;
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struct am_spi_cs * am_spi_cs = device->parent.user_data;
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rt_uint32_t * send_ptr = (rt_uint32_t *)message->send_buf;
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rt_uint32_t * recv_ptr = message->recv_buf;
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rt_uint32_t u32BytesRemaining = message->length;
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rt_uint32_t u32TransferSize = 0;
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/* take CS */
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if (message->cs_take)
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{
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;
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}
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// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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if (recv_ptr != RT_NULL)
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{
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u32TransferSize = u32BytesRemaining;
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while (u32BytesRemaining)
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{
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/* Set the transfer size to either 64, or the number of remaining
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bytes, whichever is smaller */
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if (u32BytesRemaining > 64)
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{
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u32TransferSize = 64;
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am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select,
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(uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW);
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}
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else
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{
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u32TransferSize = u32BytesRemaining;
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/* release CS */
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if(message->cs_release)
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{
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am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select,
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(uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_RAW);
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}
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else
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{
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am_hal_iom_spi_read(am_spi_bus->u32Module, am_spi_cs->chip_select,
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(uint32_t *)recv_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW);
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}
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}
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u32BytesRemaining -= u32TransferSize;
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recv_ptr = (rt_uint32_t *)((rt_uint32_t)recv_ptr + u32TransferSize);
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}
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}
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// д<><D0B4><EFBFBD><EFBFBD>
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else if (send_ptr != RT_NULL)
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{
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while (u32BytesRemaining)
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{
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/* Set the transfer size to either 32, or the number of remaining
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bytes, whichever is smaller */
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if (u32BytesRemaining > 32)
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{
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u32TransferSize = 32;
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am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
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(uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW);
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}
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else
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{
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u32TransferSize = u32BytesRemaining;
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/* release CS */
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if (message->cs_release)
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{
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am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
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(uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW);
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}
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else
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{
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am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
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(uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_CS_LOW | AM_HAL_IOM_RAW);
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}
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}
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u32BytesRemaining -= u32TransferSize;
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send_ptr = (rt_uint32_t *)((rt_uint32_t)send_ptr + u32TransferSize);
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}
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}
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return message->length;
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}
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static const struct rt_spi_ops am_spi_ops =
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{
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configure,
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xfer
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};
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#ifdef RT_USING_SPI1
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static struct am_spi_bus am_spi_bus_1 =
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{
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{0},
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AM_SPI0_IOM_INST
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};
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#endif /* #ifdef RT_USING_SPI1 */
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#ifdef RT_USING_SPI2
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static struct ambiq_spi_bus ambiq_spi_bus_2 =
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{
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{1},
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AM_SPI1_IOM_INST
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};
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#endif /* #ifdef RT_USING_SPI2 */
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int yr_hw_spi_init(void)
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{
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struct am_spi_bus* am_spi;
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#ifdef RT_USING_SPI1
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/* init spi gpio */
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am_hal_gpio_pin_config(SPI0_GPIO_SCK, SPI0_GPIO_CFG_SCK);
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am_hal_gpio_pin_config(SPI0_GPIO_MISO, SPI0_GPIO_CFG_MISO);
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am_hal_gpio_pin_config(SPI0_GPIO_MOSI, SPI0_GPIO_CFG_MOSI);
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/* Initialize IOM 0 in SPI mode at 100KHz */
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am_hal_iom_pwrctrl_enable(AM_SPI0_IOM_INST);
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am_hal_iom_config(AM_SPI0_IOM_INST, &g_sIOMConfig);
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am_hal_iom_enable(AM_SPI0_IOM_INST);
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//init spi bus device
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am_spi = &am_spi_bus_1;
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rt_spi_bus_register(&am_spi->parent, "spi1", &am_spi_ops);
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#endif
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rt_kprintf("spi init!\n");
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return 0;
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}
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#ifdef RT_USING_COMPONENTS_INIT
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INIT_BOARD_EXPORT(yr_hw_spi_init);
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#endif
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/*@}*/
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