114 lines
3.3 KiB
C
114 lines
3.3 KiB
C
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-02-20 CDT first version
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*/
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#include "board.h"
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#include "board_config.h"
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/* unlock/lock peripheral */
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#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
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LL_PERIPH_PWC_CLK_RMU)
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#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG)
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/** System Base Configuration
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*/
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void SystemBase_Config(void)
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{
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#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
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EFM_ICacheCmd(ENABLE);
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#endif
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#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
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EFM_DCacheCmd(ENABLE);
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#endif
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#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
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EFM_PrefetchCmd(ENABLE);
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#endif
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}
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/** System Clock Configuration
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*/
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void SystemClock_Config(void)
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{
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stc_clock_xtal_init_t stcXtalInit;
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stc_clock_pll_init_t stcPLLHInit;
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#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
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stc_clock_xtal32_init_t stcXtal32Init;
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#endif
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/* PCLK0, HCLK Max 200MHz */
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/* PCLK1, PCLK4 Max 100MHz */
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/* PCLK2, EXCLK Max 60MHz */
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/* PCLK3 Max 50MHz */
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CLK_SetClockDiv(CLK_BUS_CLK_ALL,
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(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
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CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 |
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CLK_HCLK_DIV1));
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GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
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(void)CLK_XtalStructInit(&stcXtalInit);
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/* Config Xtal and enable Xtal */
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stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
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stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
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stcXtalInit.u8State = CLK_XTAL_ON;
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stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
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(void)CLK_XtalInit(&stcXtalInit);
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(void)CLK_PLLStructInit(&stcPLLHInit);
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/* VCO = (12/1)*40 = 480MHz*/
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stcPLLHInit.u8PLLState = CLK_PLL_ON;
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stcPLLHInit.PLLCFGR = 0UL;
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stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLN = 40UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
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(void)CLK_PLLInit(&stcPLLHInit);
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/* 0-wait @ 40MHz */
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(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE2);
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/* 2 cycles for 100 ~ 150MHz */
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GPIO_SetReadWaitCycle(GPIO_RD_WAIT2);
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CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
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#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
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/* Xtal32 config */
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GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
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(void)CLK_Xtal32StructInit(&stcXtal32Init);
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stcXtal32Init.u8State = CLK_XTAL32_ON;
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stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
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stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
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(void)CLK_Xtal32Init(&stcXtal32Init);
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#endif
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}
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/** Peripheral Clock Configuration
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*/
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void PeripheralClock_Config(void)
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{
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#if defined(BSP_USING_CAN1)
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CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
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#endif
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#if defined(BSP_USING_CAN2)
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CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
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#endif
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#if defined(RT_USING_ADC)
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CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
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#endif
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}
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/** Peripheral Registers Unlock
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*/
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void PeripheralRegister_Unlock(void)
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{
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LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
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}
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