2022-01-14 18:10:27 +08:00
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-11-03 mazhiyuan first version
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*/
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#include <drv_sdhi.h>
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struct ra_sdhi sdhi;
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#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
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#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
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struct rthw_sdio
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{
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struct rt_mmcsd_host *host;
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struct ra_sdhi sdhi_des;
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struct rt_event event;
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struct rt_mutex mutex;
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};
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static struct rt_mmcsd_host *host;
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2022-12-12 02:12:03 +08:00
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rt_align(SDIO_ALIGN_LEN)
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2022-01-14 18:10:27 +08:00
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static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
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rt_err_t command_send(sdhi_instance_ctrl_t *p_ctrl, struct rt_mmcsd_cmd *cmd)
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{
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uint32_t wait_bit;
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uint32_t timeout = BUSY_TIMEOUT_US;
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volatile sdhi_event_t event;
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struct rt_mmcsd_data *data = cmd->data;
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while (SD_INFO2_CBSY_SDD0MON_IDLE_VAL !=
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(p_ctrl->p_reg->SD_INFO2 & SD_INFO2_CBSY_SDD0MON_IDLE_MASK))
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{
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if (timeout == 0)
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{
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return RT_ETIMEOUT;
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}
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R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS);
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timeout--;
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}
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p_ctrl->p_reg->SD_INFO1 = 0U;
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p_ctrl->p_reg->SD_INFO2 = 0U;
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p_ctrl->sdhi_event.word = 0U;
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/* Enable response end interrupt. */
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/* Disable access end interrupt and enable response end interrupt. */
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uint32_t mask = p_ctrl->p_reg->SD_INFO1_MASK;
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mask &= (~SDHI_INFO1_RESPONSE_END);
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mask |= SDHI_INFO1_ACCESS_END;
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p_ctrl->p_reg->SD_INFO1_MASK = mask;
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p_ctrl->p_reg->SD_INFO2_MASK = SDHI_INFO2_MASK_CMD_SEND;
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/* Write argument, then command to the SDHI peripheral. */
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p_ctrl->p_reg->SD_ARG = cmd->arg & UINT16_MAX;
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p_ctrl->p_reg->SD_ARG1 = cmd->arg >> 16;
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if ((cmd->flags & CMD_MASK) == CMD_ADTC)
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{
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cmd->cmd_code |= SDHI_CMD_ADTC_EN;
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switch (cmd->flags & RESP_MASK)
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{
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case RESP_R1:
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case RESP_R5:
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case RESP_R6:
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case RESP_R7:
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cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_R1_R5_R6_R7;
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break;
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case RESP_R1B:
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cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_R1B;
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break;
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case RESP_R2:
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cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_R2;
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break;
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case RESP_R3:
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case RESP_R4:
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cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_R3_R4;
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break;
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case RESP_NONE:
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cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_NONE;
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break;
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}
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if (data != RT_NULL)
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{
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if ((data->flags & 7) == DATA_DIR_WRITE)
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{
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cmd->cmd_code &= ~SDHI_CMD_DATA_DIR_READ;
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}
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else if ((data->flags & 7) == DATA_DIR_READ)
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{
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cmd->cmd_code |= SDHI_CMD_DATA_DIR_READ;
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}
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}
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}
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p_ctrl->p_reg->SD_CMD = cmd->cmd_code;
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timeout = 100000;
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while (true)
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{
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/* Check for updates to the event status. */
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event.word = p_ctrl->sdhi_event.word;
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/* Return an error if a hardware error occurred. */
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if (event.bit.event_error)
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{
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cmd->err = -RT_ERROR;
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if ((event.word & HW_SDHI_ERR_CRCE) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
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{
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if ((cmd->flags & RESP_MASK) == RESP_R2)
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{
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cmd->resp[0] = (p_ctrl->p_reg->SD_RSP76 << 8) | (p_ctrl->p_reg->SD_RSP54 >> 24);
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cmd->resp[1] = (p_ctrl->p_reg->SD_RSP54 << 8) | (p_ctrl->p_reg->SD_RSP32 >> 24);
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cmd->resp[2] = (p_ctrl->p_reg->SD_RSP32 << 8) | (p_ctrl->p_reg->SD_RSP10 >> 24);
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cmd->resp[3] = (p_ctrl->p_reg->SD_RSP10 << 8);
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}
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else
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{
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cmd->resp[0] = p_ctrl->p_reg->SD_RSP10;
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}
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cmd->err = RT_EOK;
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}
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if (event.word & HW_SDHI_ERR_RTIMEOUT)
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{
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cmd->err = -RT_ETIMEOUT;
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}
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if (event.word & HW_SDHI_ERR_DTIMEOUT)
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{
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data->err = -RT_ETIMEOUT;
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}
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return -RT_ERROR;
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}
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if (data != RT_NULL)
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{
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wait_bit = SDHI_WAIT_ACCESS_BIT;
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}
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else
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{
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wait_bit = SDHI_WAIT_RESPONSE_BIT;
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}
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/* If the requested bit is set, return success. */
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if (event.word & (1U << wait_bit))
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{
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cmd->err = RT_EOK;
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if ((cmd->flags & RESP_MASK) == RESP_R2)
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{
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cmd->resp[0] = (p_ctrl->p_reg->SD_RSP76 << 8) | (p_ctrl->p_reg->SD_RSP54 >> 24);
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cmd->resp[1] = (p_ctrl->p_reg->SD_RSP54 << 8) | (p_ctrl->p_reg->SD_RSP32 >> 24);
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cmd->resp[2] = (p_ctrl->p_reg->SD_RSP32 << 8) | (p_ctrl->p_reg->SD_RSP10 >> 24);
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cmd->resp[3] = (p_ctrl->p_reg->SD_RSP10 << 8);
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}
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else
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{
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cmd->resp[0] = p_ctrl->p_reg->SD_RSP10;
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}
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return RT_EOK;
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}
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/* Check for timeout. */
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timeout--;
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if (0U == timeout)
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{
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cmd->err = -RT_ETIMEOUT;
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return RT_ERROR;
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}
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/* Wait 1 us for consistent loop timing. */
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R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS);
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}
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}
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rt_err_t transfer_write(sdhi_instance_ctrl_t *const p_ctrl,
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uint32_t block_count,
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uint32_t bytes,
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const uint8_t *p_data)
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{
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transfer_info_t *p_info = p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info;
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/* When the SD_DMAEN.DMAEN bit is 1, set the SD_INFO2_MASK.BWEM bit to 1 and the SD_INFO2_MASK.BREM bit to 1. */
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p_ctrl->p_reg->SD_INFO2_MASK |= 0x300U;
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p_ctrl->p_reg->SD_DMAEN = 0x2U;
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uint32_t transfer_settings = (uint32_t)TRANSFER_MODE_BLOCK << TRANSFER_SETTINGS_MODE_BITS;
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transfer_settings |= TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS;
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transfer_settings |= TRANSFER_SIZE_4_BYTE << TRANSFER_SETTINGS_SIZE_BITS;
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#if SDMMC_CFG_UNALIGNED_ACCESS_ENABLE
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if ((0U != ((uint32_t)p_data & 0x3U)) || (0U != (bytes & 3U)))
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{
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transfer_settings |= TRANSFER_IRQ_EACH << TRANSFER_SETTINGS_IRQ_BITS;
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transfer_settings |= TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS;
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/* If the pointer is not 4-byte aligned or the number of bytes is not a multiple of 4, use a temporary buffer.
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* Transfer the first block to the temporary buffer before enabling the transfer. Subsequent blocks will be
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* transferred from the user buffer to the temporary buffer in an interrupt after each block transfer. */
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rt_memcpy((void *)&p_ctrl->aligned_buff[0], p_data, bytes);
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p_info->p_src = &p_ctrl->aligned_buff[0];
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p_ctrl->transfer_block_current = 1U;
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p_ctrl->transfer_blocks_total = block_count;
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p_ctrl->p_transfer_data = (uint8_t *)&p_data[bytes];
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p_ctrl->transfer_dir = SDHI_TRANSFER_DIR_WRITE;
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p_ctrl->transfer_block_size = bytes;
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}
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else
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#endif
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{
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p_info->p_src = p_data;
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}
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p_info->transfer_settings_word = transfer_settings;
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p_info->p_dest = (uint32_t *)(&p_ctrl->p_reg->SD_BUF0);
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p_info->num_blocks = (uint16_t)block_count;
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/* Round up to the nearest multiple of 4 bytes for the transfer. */
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uint32_t words = (bytes + (sizeof(uint32_t) - 1U)) / sizeof(uint32_t);
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p_info->length = (uint16_t)words;
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/* Configure the transfer driver to write to the SD buffer. */
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fsp_err_t err = p_ctrl->p_cfg->p_lower_lvl_transfer->p_api->reconfigure(p_ctrl->p_cfg->p_lower_lvl_transfer->p_ctrl,
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p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info);
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if (FSP_SUCCESS != err)
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return RT_ERROR;
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return RT_EOK;
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}
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rt_err_t transfer_read(sdhi_instance_ctrl_t *const p_ctrl,
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uint32_t block_count,
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uint32_t bytes,
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void *p_data)
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{
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transfer_info_t *p_info = p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info;
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/* When the SD_DMAEN.DMAEN bit is 1, set the SD_INFO2_MASK.BWEM bit to 1 and the SD_INFO2_MASK.BREM bit to 1. */
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p_ctrl->p_reg->SD_INFO2_MASK |= 0X300U;
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p_ctrl->p_reg->SD_DMAEN = 0x2U;
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uint32_t transfer_settings = (uint32_t)TRANSFER_MODE_BLOCK << TRANSFER_SETTINGS_MODE_BITS;
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transfer_settings |= TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS;
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transfer_settings |= TRANSFER_SIZE_4_BYTE << TRANSFER_SETTINGS_SIZE_BITS;
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#if SDMMC_CFG_UNALIGNED_ACCESS_ENABLE
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/* If the pointer is not 4-byte aligned or the number of bytes is not a multiple of 4, use a temporary buffer.
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* Data will be transferred from the temporary buffer into the user buffer in an interrupt after each block transfer. */
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if ((0U != ((uint32_t)p_data & 0x3U)) || (0U != (bytes & 3U)))
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{
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transfer_settings |= TRANSFER_IRQ_EACH << TRANSFER_SETTINGS_IRQ_BITS;
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p_info->p_dest = &p_ctrl->aligned_buff[0];
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p_ctrl->transfer_block_current = 0U;
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p_ctrl->transfer_blocks_total = block_count;
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p_ctrl->p_transfer_data = (uint8_t *)p_data;
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p_ctrl->transfer_dir = SDHI_TRANSFER_DIR_READ;
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p_ctrl->transfer_block_size = bytes;
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}
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else
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#endif
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{
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transfer_settings |= TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS;
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p_info->p_dest = p_data;
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}
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p_info->transfer_settings_word = transfer_settings;
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p_info->p_src = (uint32_t *)(&p_ctrl->p_reg->SD_BUF0);
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p_info->num_blocks = (uint16_t)block_count;
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/* Round up to the nearest multiple of 4 bytes for the transfer. */
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uint32_t words = (bytes + (sizeof(uint32_t) - 1U)) / sizeof(uint32_t);
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p_info->length = (uint16_t)words;
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/* Configure the transfer driver to read from the SD buffer. */
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fsp_err_t err = p_ctrl->p_cfg->p_lower_lvl_transfer->p_api->reconfigure(p_ctrl->p_cfg->p_lower_lvl_transfer->p_ctrl,
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p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info);
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if (err != FSP_SUCCESS)
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return RT_ERROR;
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return RT_EOK;
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}
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void ra_sdhi_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct rthw_sdio *sdio = host->private_data;
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struct rt_mmcsd_data *data;
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static rt_uint8_t *buffer;
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RTHW_SDIO_LOCK(sdio);
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if (req->cmd != RT_NULL)
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{
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data = req->cmd->data;
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if (data != RT_NULL)
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{
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rt_uint32_t size = data->blks * data->blksize;
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RT_ASSERT(size <= SDIO_BUFF_SIZE);
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buffer = (rt_uint8_t *)data->buf;
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if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
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{
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buffer = cache_buf;
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if (data->flags & DATA_DIR_WRITE)
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{
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rt_memcpy(cache_buf, data->buf, size);
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}
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}
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if (data->flags & DATA_DIR_WRITE)
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{
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transfer_write(sdio->sdhi_des.instance->p_ctrl, data->blks, data->blksize, buffer);
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}
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else if (data->flags & DATA_DIR_READ)
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{
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transfer_read(sdio->sdhi_des.instance->p_ctrl, data->blks, data->blksize, buffer);
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}
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/* Set the sector count. */
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if (data->blks > 1U)
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{
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((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_STOP = 0x100U;
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((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_SECCNT = data->blks;
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}
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else
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{
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((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_STOP = 0U;
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|
|
|
}
|
|
|
|
((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_SIZE = data->blksize;
|
|
|
|
}
|
|
|
|
rt_enter_critical();
|
|
|
|
command_send(sdio->sdhi_des.instance->p_ctrl, req->cmd);
|
|
|
|
rt_exit_critical();
|
|
|
|
if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
|
|
|
|
{
|
|
|
|
rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (req->stop != RT_NULL)
|
|
|
|
{
|
|
|
|
rt_enter_critical();
|
|
|
|
command_send(sdio->sdhi_des.instance->p_ctrl, req->stop);
|
|
|
|
rt_exit_critical();
|
|
|
|
}
|
|
|
|
RTHW_SDIO_UNLOCK(sdio);
|
|
|
|
mmcsd_req_complete(sdio->host);
|
|
|
|
}
|
|
|
|
|
|
|
|
static rt_err_t clock_rate_set(sdhi_instance_ctrl_t *p_ctrl, uint32_t max_rate)
|
|
|
|
{
|
|
|
|
uint32_t setting = 0xFFU;
|
|
|
|
|
|
|
|
/* Get the runtime frequency of the source of the SD clock */
|
|
|
|
uint32_t frequency = R_FSP_SystemClockHzGet(BSP_FEATURE_SDHI_CLOCK);
|
|
|
|
|
|
|
|
/* Iterate over all possible divisors, starting with the smallest, until the resulting clock rate is less than
|
|
|
|
* or equal to the requested maximum rate. */
|
|
|
|
for (uint32_t divisor_shift = BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT;
|
|
|
|
divisor_shift <= 9U;
|
|
|
|
divisor_shift++)
|
|
|
|
{
|
|
|
|
if ((frequency >> divisor_shift) <= max_rate)
|
|
|
|
{
|
|
|
|
/* If the calculated frequency is less than or equal to the maximum supported by the device,
|
|
|
|
* select this frequency. The register setting is the divisor value divided by 4, or 0xFF for no divider. */
|
|
|
|
setting = divisor_shift ? ((1U << divisor_shift) >> 2U) : UINT8_MAX;
|
|
|
|
|
|
|
|
/* Set the clock setting. */
|
|
|
|
|
|
|
|
/* The clock register is accessible 8 SD clock counts after the last command completes. Each register access
|
|
|
|
* requires at least one PCLK count, so check the register up to 8 times the maximum PCLK divisor value (512). */
|
|
|
|
uint32_t timeout = 8U * 512U;
|
|
|
|
|
|
|
|
while (timeout > 0U)
|
|
|
|
{
|
|
|
|
/* Do not write to clock control register until this bit is set. */
|
|
|
|
if (p_ctrl->p_reg->SD_INFO2_b.SD_CLK_CTRLEN)
|
|
|
|
{
|
|
|
|
/* Set the calculated divider and enable clock output to start the 74 clocks required before
|
|
|
|
* initialization. Do not change the automatic clock control setting. */
|
|
|
|
uint32_t clkctrlen = p_ctrl->p_reg->SD_CLK_CTRL & (1U << 9);
|
|
|
|
p_ctrl->p_reg->SD_CLK_CTRL = setting | clkctrlen | (1U << 8);
|
|
|
|
p_ctrl->device.clock_rate = frequency >> divisor_shift;
|
|
|
|
|
|
|
|
return RT_EOK;
|
|
|
|
}
|
|
|
|
|
|
|
|
timeout--;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Valid setting already found, stop looking. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return RT_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ra_sdhi_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
|
|
|
|
{
|
|
|
|
struct rthw_sdio *sdio = host->private_data;
|
|
|
|
RTHW_SDIO_LOCK(sdio);
|
|
|
|
if (io_cfg->bus_width == MMCSD_BUS_WIDTH_1)
|
|
|
|
{
|
|
|
|
((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH = 1;
|
|
|
|
}
|
|
|
|
else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
|
|
|
|
{
|
|
|
|
((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH = 0;
|
|
|
|
((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH8 = 0;
|
|
|
|
}
|
|
|
|
else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
|
|
|
|
{
|
|
|
|
((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH = 0;
|
|
|
|
((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH8 = 1;
|
|
|
|
}
|
|
|
|
clock_rate_set(sdio->sdhi_des.instance->p_ctrl, io_cfg->clock);
|
|
|
|
RTHW_SDIO_UNLOCK(sdio);
|
|
|
|
}
|
|
|
|
|
|
|
|
rt_int32_t ra_sdhi_get_card_status(struct rt_mmcsd_host *host)
|
|
|
|
{
|
|
|
|
sdmmc_status_t status;
|
|
|
|
struct rthw_sdio *sdio = host->private_data;
|
|
|
|
sdio->sdhi_des.instance->p_api->statusGet(sdio->sdhi_des.instance->p_ctrl, &status);
|
|
|
|
return status.card_inserted;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ra_sdhi_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
|
|
|
|
{
|
|
|
|
struct rthw_sdio *sdio = host->private_data;
|
|
|
|
sdio->sdhi_des.instance->p_api->ioIntEnable(sdio->sdhi_des.instance->p_ctrl, en);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct rt_mmcsd_host_ops ra_sdhi_ops =
|
|
|
|
{
|
|
|
|
.request = ra_sdhi_request,
|
|
|
|
.set_iocfg = ra_sdhi_set_iocfg,
|
|
|
|
.get_card_status = ra_sdhi_get_card_status,
|
|
|
|
.enable_sdio_irq = ra_sdhi_enable_sdio_irq
|
|
|
|
};
|
|
|
|
|
|
|
|
void sdhi_callback(sdmmc_callback_args_t *p_args)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des)
|
|
|
|
{
|
|
|
|
struct rt_mmcsd_host *host;
|
|
|
|
struct rthw_sdio *sdio = RT_NULL;
|
|
|
|
|
|
|
|
if (sdhi_des == RT_NULL)
|
|
|
|
return RT_NULL;
|
|
|
|
|
|
|
|
sdio = rt_malloc(sizeof(struct rthw_sdio));
|
|
|
|
if (sdio == RT_NULL)
|
|
|
|
return RT_NULL;
|
|
|
|
rt_memset(sdio, 0, sizeof(struct rthw_sdio));
|
|
|
|
|
|
|
|
host = mmcsd_alloc_host();
|
|
|
|
if (host == RT_NULL)
|
|
|
|
{
|
|
|
|
rt_free(sdio);
|
|
|
|
return RT_NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
rt_memcpy(&sdio->sdhi_des, sdhi_des, sizeof(struct ra_sdhi));
|
|
|
|
|
|
|
|
rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
|
|
|
|
rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
|
|
|
|
|
|
|
|
/* set host defautl attributes */
|
|
|
|
host->ops = &ra_sdhi_ops;
|
|
|
|
host->freq_min = 400 * 1000;
|
|
|
|
host->freq_max = SDIO_MAX_FREQ;
|
|
|
|
host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */
|
|
|
|
#ifndef SDHI_USING_1_BIT
|
|
|
|
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
|
|
|
|
#else
|
|
|
|
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
|
|
|
|
#endif
|
|
|
|
host->max_seg_size = SDIO_BUFF_SIZE;
|
|
|
|
host->max_dma_segs = 1;
|
|
|
|
host->max_blk_size = 512;
|
|
|
|
host->max_blk_count = 512;
|
|
|
|
|
|
|
|
/* link up host and sdio */
|
|
|
|
sdio->host = host;
|
|
|
|
host->private_data = sdio;
|
|
|
|
|
|
|
|
ra_sdhi_enable_sdio_irq(host, 1);
|
|
|
|
|
|
|
|
/* ready to change */
|
|
|
|
mmcsd_change(host);
|
|
|
|
|
|
|
|
return host;
|
|
|
|
}
|
|
|
|
|
|
|
|
int rt_hw_sdhi_init(void)
|
|
|
|
{
|
|
|
|
sdhi.instance = &g_sdmmc0;
|
|
|
|
sdhi.instance->p_api->open(sdhi.instance->p_ctrl, sdhi.instance->p_cfg);
|
|
|
|
host = sdio_host_create(&sdhi);
|
|
|
|
if (host == RT_NULL)
|
|
|
|
{
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_sdhi_init);
|