rt-thread-official/bsp/stm32/stm32l4r5-st-nucleo/board/linker_scripts/link.icf

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__      = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__        = 0x08200000;
define symbol __ICFEDIT_region_RAM1_start__     = 0x20000000;
define symbol __ICFEDIT_region_RAM1_end__       = 0x20030000;
define symbol __ICFEDIT_region_RAM2_start__     = 0x20040000;
define symbol __ICFEDIT_region_RAM2_end__       = 0x200A0000;
define symbol __ICFEDIT_region_RAM3_start__     = 0x10000000;
define symbol __ICFEDIT_region_RAM3_end__       = 0x10010000;

/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x0800;
define symbol __ICFEDIT_size_heap__   = 0x000;
/**** End of ICF editor section. ###ICF###*/

define memory mem with size = 4G;
define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
define region RAM1_region     = mem:[from __ICFEDIT_region_RAM1_start__   to __ICFEDIT_region_RAM1_end__];
define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__   to __ICFEDIT_region_RAM2_end__];
define region RAM3_region     = mem:[from __ICFEDIT_region_RAM3_start__   to __ICFEDIT_region_RAM3_end__];

define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };

initialize by copy { readwrite };
do not initialize  { section .noinit };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };

place in ROM_region   { readonly };
place in RAM1_region  { readwrite,  last block CSTACK };
place in RAM2_region  { section .sram };