161 lines
4.2 KiB
C
161 lines
4.2 KiB
C
|
/*
|
||
|
|
* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
|
||
|
|
*
|
||
|
|
* SPDX-License-Identifier: Apache-2.0
|
||
|
|
*
|
||
|
|
* Change Logs:
|
||
|
|
* Date Author Notes
|
||
|
|
* 2022-04-28 CDT first version
|
||
|
|
*/
|
||
|
|
|
||
|
|
#include "board.h"
|
||
|
|
|
||
|
|
/* unlock/lock peripheral */
|
||
|
|
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
|
||
|
|
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
|
||
|
|
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief This function is executed in case of error occurrence.
|
||
|
|
* @param None
|
||
|
|
* @retval None
|
||
|
|
*/
|
||
|
|
void Error_Handler(void)
|
||
|
|
{
|
||
|
|
/* USER CODE BEGIN Error_Handler */
|
||
|
|
/* User can add his own implementation to report the HAL error return state */
|
||
|
|
while (1)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
/* USER CODE END Error_Handler */
|
||
|
|
}
|
||
|
|
|
||
|
|
/** System Clock Configuration
|
||
|
|
*/
|
||
|
|
void SystemClock_Config(void)
|
||
|
|
{
|
||
|
|
stc_clock_xtal_init_t stcXtalInit;
|
||
|
|
stc_clock_pll_init_t stcPLLHInit;
|
||
|
|
|
||
|
|
/* PCLK0, HCLK Max 240MHz */
|
||
|
|
/* PCLK1, PCLK4 Max 120MHz */
|
||
|
|
/* PCLK2, PCLK3 Max 60MHz */
|
||
|
|
/* EX BUS Max 120MHz */
|
||
|
|
CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
|
||
|
|
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
|
||
|
|
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
|
||
|
|
CLK_HCLK_DIV1));
|
||
|
|
|
||
|
|
(void)CLK_XtalStructInit(&stcXtalInit);
|
||
|
|
/* Config Xtal and enable Xtal */
|
||
|
|
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
|
||
|
|
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
|
||
|
|
stcXtalInit.u8State = CLK_XTAL_ON;
|
||
|
|
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
|
||
|
|
(void)CLK_XtalInit(&stcXtalInit);
|
||
|
|
|
||
|
|
(void)CLK_PLLStructInit(&stcPLLHInit);
|
||
|
|
/* VCO = (8/1)*120 = 960MHz*/
|
||
|
|
stcPLLHInit.u8PLLState = CLK_PLL_ON;
|
||
|
|
stcPLLHInit.PLLCFGR = 0UL;
|
||
|
|
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
|
||
|
|
stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
|
||
|
|
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
|
||
|
|
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||
|
|
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||
|
|
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
|
||
|
|
(void)CLK_PLLInit(&stcPLLHInit);
|
||
|
|
|
||
|
|
/* Highspeed SRAM set to 0 Read/Write wait cycle */
|
||
|
|
SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
|
||
|
|
|
||
|
|
/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
|
||
|
|
SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
|
||
|
|
|
||
|
|
/* 0-wait @ 40MHz */
|
||
|
|
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
|
||
|
|
|
||
|
|
/* 4 cycles for 200 ~ 250MHz */
|
||
|
|
GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
|
||
|
|
|
||
|
|
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name : SysTick_Configuration
|
||
|
|
* Description : Configures the SysTick for OS tick.
|
||
|
|
* Input : None
|
||
|
|
* Output : None
|
||
|
|
* Return : None
|
||
|
|
*******************************************************************************/
|
||
|
|
void SysTick_Configuration(void)
|
||
|
|
{
|
||
|
|
stc_clock_freq_t stcClkFreq;
|
||
|
|
rt_uint32_t cnts;
|
||
|
|
|
||
|
|
CLK_GetClockFreq(&stcClkFreq);
|
||
|
|
|
||
|
|
cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND;
|
||
|
|
|
||
|
|
SysTick_Config(cnts);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* This is the timer interrupt service routine.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void SysTick_Handler(void)
|
||
|
|
{
|
||
|
|
/* enter interrupt */
|
||
|
|
rt_interrupt_enter();
|
||
|
|
|
||
|
|
rt_tick_increase();
|
||
|
|
|
||
|
|
/* leave interrupt */
|
||
|
|
rt_interrupt_leave();
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* This function will initial GD32 board.
|
||
|
|
*/
|
||
|
|
void rt_hw_board_init()
|
||
|
|
{
|
||
|
|
/* Peripheral registers write unprotected */
|
||
|
|
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
|
||
|
|
|
||
|
|
SystemClock_Config();
|
||
|
|
/* Configure the SysTick */
|
||
|
|
SysTick_Configuration();
|
||
|
|
|
||
|
|
/* Heap initialization */
|
||
|
|
#if defined(RT_USING_HEAP)
|
||
|
|
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Board underlying hardware initialization */
|
||
|
|
#ifdef RT_USING_COMPONENTS_INIT
|
||
|
|
rt_components_board_init();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||
|
|
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void rt_hw_us_delay(rt_uint32_t us)
|
||
|
|
{
|
||
|
|
uint32_t start, now, delta, reload, us_tick;
|
||
|
|
start = SysTick->VAL;
|
||
|
|
reload = SysTick->LOAD;
|
||
|
|
us_tick = SystemCoreClock / 1000000UL;
|
||
|
|
|
||
|
|
do
|
||
|
|
{
|
||
|
|
now = SysTick->VAL;
|
||
|
|
delta = start > now ? start - now : reload + start - now;
|
||
|
|
}
|
||
|
|
while (delta < us_tick * us);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*@}*/
|