558 lines
16 KiB
C
558 lines
16 KiB
C
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/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-2-11 Wayne First version
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*
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******************************************************************************/
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#include <rtconfig.h>
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#if defined(BSP_USING_QSPI)
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#include <rtdevice.h>
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#include "NuMicro.h"
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#include <nu_bitutil.h>
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#include <drv_sys.h>
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#include <drv_qspi.h>
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#define LOG_TAG "drv.qspi"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME LOG_TAG
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#define DBG_LEVEL DBG_INFO
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#define DBG_COLOR
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#include <rtdbg.h>
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#include <rthw.h>
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#include <rtdevice.h>
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#include <rtdef.h>
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/* Private define ---------------------------------------------------------------*/
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/* fsclk = fpclk / ((div+1)*2), but div=1 is suggested. */
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#define DEF_SPI_MAX_SPEED (SPI_INPUT_CLOCK/((1)*2))
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enum
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{
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QSPI_START = -1,
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#if defined(BSP_USING_QSPI0)
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QSPI0_IDX,
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#endif
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#if defined(BSP_USING_QSPI1)
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QSPI1_IDX,
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#endif
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QSPI_CNT
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};
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/* Private typedef --------------------------------------------------------------*/
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struct nu_qspi
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{
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struct rt_spi_bus dev;
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char *name;
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uint32_t idx;
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E_SYS_IPRST rstidx;
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E_SYS_IPCLK clkidx;
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uint32_t dummy;
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struct rt_qspi_configuration configuration;
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};
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typedef struct nu_qspi *nu_qspi_t;
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/* Private functions ------------------------------------------------------------*/
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static void nu_qspi_transmission_with_poll(struct nu_qspi *spi_bus,
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uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word);
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static int nu_qspi_register_bus(struct nu_qspi *spi_bus, const char *name);
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static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message);
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static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
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/* Public functions -------------------------------------------------------------*/
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/* Private variables ------------------------------------------------------------*/
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static struct rt_spi_ops nu_qspi_poll_ops =
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{
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.configure = nu_qspi_bus_configure,
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.xfer = nu_qspi_bus_xfer,
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};
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static struct nu_qspi nu_qspi_arr [] =
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{
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#if defined(BSP_USING_QSPI0)
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{
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.name = "qspi0",
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.idx = 0,
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.rstidx = SPI0RST,
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.clkidx = SPI0CKEN,
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},
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#endif
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#if defined(BSP_USING_QSPI1)
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{
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.name = "qspi1",
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.idx = 1,
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.rstidx = SPI1RST,
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.clkidx = SPI1CKEN,
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},
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#endif
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}; /* nu_qspi */
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static rt_err_t nu_qspi_bus_configure(struct rt_spi_device *device,
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struct rt_spi_configuration *configuration)
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{
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struct nu_qspi *qspi_bus;
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uint32_t u32SPIMode;
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uint32_t u32SPISpeed;
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rt_err_t ret = RT_EOK;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(configuration != RT_NULL);
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qspi_bus = (struct nu_qspi *) device->bus;
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/* Check mode */
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switch (configuration->mode & RT_SPI_MODE_3)
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{
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case RT_SPI_MODE_0:
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u32SPIMode = SPI_MODE_0;
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break;
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case RT_SPI_MODE_1:
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u32SPIMode = SPI_MODE_1;
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break;
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case RT_SPI_MODE_2:
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u32SPIMode = SPI_MODE_2;
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break;
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case RT_SPI_MODE_3:
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u32SPIMode = SPI_MODE_3;
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break;
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default:
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ret = RT_EIO;
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goto exit_nu_qspi_bus_configure;
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}
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/* Check data width */
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if (!(configuration->data_width == 8 ||
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configuration->data_width == 16 ||
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configuration->data_width == 24 ||
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configuration->data_width == 32))
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{
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ret = RT_EINVAL;
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goto exit_nu_qspi_bus_configure;
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}
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/* Need to initialize new configuration? */
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if (rt_memcmp(configuration, &qspi_bus->configuration, sizeof(*configuration)) != 0)
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{
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rt_memcpy(&qspi_bus->configuration, configuration, sizeof(*configuration));
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/* Set mode */
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spiIoctl(qspi_bus->idx, SPI_IOC_SET_MODE, (uint32_t)u32SPIMode, 0);
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/* Set data width */
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spiIoctl(qspi_bus->idx, SPI_IOC_SET_TX_BITLEN, (uint32_t)configuration->data_width, 0);
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/* Set speed */
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u32SPISpeed = configuration->max_hz;
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if (u32SPISpeed > DEF_SPI_MAX_SPEED)
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u32SPISpeed = DEF_SPI_MAX_SPEED;
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u32SPISpeed = spiIoctl(qspi_bus->idx, SPI_IOC_SET_SPEED, u32SPISpeed, 0);
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LOG_I("Actual=%dHz, Prefer=%dHz", u32SPISpeed, configuration->max_hz);
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/* Disable auto-select */
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spiIoctl(qspi_bus->idx, SPI_IOC_SET_AUTOSS, SPI_DISABLE_AUTOSS, 0);
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if (configuration->mode & RT_SPI_CS_HIGH)
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{
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/* Set CS pin to LOW */
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spiIoctl(qspi_bus->idx, SPI_IOC_SET_SS_ACTIVE_LEVEL, SPI_SS_ACTIVE_HIGH, 0);
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}
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else
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{
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/* Set CS pin to HIGH */
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spiIoctl(qspi_bus->idx, SPI_IOC_SET_SS_ACTIVE_LEVEL, SPI_SS_ACTIVE_LOW, 0);
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}
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if (configuration->mode & RT_SPI_MSB)
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{
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/* Set sequence to MSB first */
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spiIoctl(qspi_bus->idx, SPI_IOC_SET_LSB_MSB, SPI_MSB, 0);
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}
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else
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{
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/* Set sequence to LSB first */
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spiIoctl(qspi_bus->idx, SPI_IOC_SET_LSB_MSB, SPI_LSB, 0);
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}
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}
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exit_nu_qspi_bus_configure:
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return -(ret);
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}
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static int nu_qspi_read(uint32_t idx, uint32_t buf_id, uint8_t *recv_addr, uint8_t bytes_per_word)
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{
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uint32_t val;
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// Read data from SPI RX FIFO
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switch (bytes_per_word)
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{
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case 4:
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val = spiRead(idx, buf_id);
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nu_set32_le(recv_addr, val);
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break;
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case 3:
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val = spiRead(idx, buf_id);
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nu_set24_le(recv_addr, val);
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break;
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case 2:
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val = spiRead(idx, buf_id);
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nu_set16_le(recv_addr, val);
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break;
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case 1:
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*recv_addr = spiRead(idx, buf_id);
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break;
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default:
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LOG_E("Data length is not supported.\n");
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return 0;
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}
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return bytes_per_word;
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}
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static int nu_qspi_write(uint32_t idx, uint32_t buf_id, const uint8_t *send_addr, uint8_t bytes_per_word)
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{
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// Input data to SPI TX
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switch (bytes_per_word)
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{
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case 4:
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spiWrite(idx, buf_id, nu_get32_le(send_addr));
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break;
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case 3:
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spiWrite(idx, buf_id, nu_get24_le(send_addr));
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break;
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case 2:
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spiWrite(idx, buf_id, nu_get16_le(send_addr));
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break;
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case 1:
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spiWrite(idx, buf_id, *((uint8_t *)send_addr));
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break;
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default:
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LOG_E("Data length is not supported.\n");
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return 0;
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}
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return bytes_per_word;
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}
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/**
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* @brief SPI bus polling
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* @param dev : The pointer of the specified SPI module.
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* @param send_addr : Source address
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* @param recv_addr : Destination address
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* @param length : Data length
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*/
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static void nu_qspi_transmission_with_poll(struct nu_qspi *spi_bus,
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uint8_t *send_addr, uint8_t *recv_addr, int length, uint8_t bytes_per_word)
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{
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uint32_t idx = spi_bus->idx;
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int trans_num = length / bytes_per_word;
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while (trans_num > 0)
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{
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int i;
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uint32_t u32TxNum = (trans_num > 4) ? 4 : trans_num;
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for (i = 0; i < u32TxNum; i++)
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{
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/* Write TX data into TX-buffer */
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if ((send_addr != RT_NULL))
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{
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send_addr += nu_qspi_write(idx, i, (const uint8_t *)send_addr, bytes_per_word);
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}
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else /* read-only */
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{
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spi_bus->dummy = 0;
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nu_qspi_write(idx, i, (const uint8_t *)&spi_bus->dummy, bytes_per_word);
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}
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}
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/* Set TX transacation number */
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spiIoctl(idx, SPI_IOC_SET_TX_NUM, u32TxNum - 1, 0);
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/* Trigger SPI communication. */
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spiIoctl(idx, SPI_IOC_TRIGGER, 0, 0);
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/* Wait it done. */
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while (spiGetBusyStatus(idx)) {};
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/* Read data from RX-buffer */
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if ((recv_addr != RT_NULL))
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{
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for (i = 0; i < u32TxNum; i++)
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{
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recv_addr += nu_qspi_read(idx, i, recv_addr, bytes_per_word);
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}
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}
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trans_num -= u32TxNum;
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}
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}
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void nu_qspi_transfer(struct nu_qspi *spi_bus, uint8_t *tx, uint8_t *rx, int length, uint8_t bytes_per_word)
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{
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RT_ASSERT(spi_bus != RT_NULL);
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nu_qspi_transmission_with_poll(spi_bus, tx, rx, length, bytes_per_word);
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}
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static int nu_qspi_mode_config(struct nu_qspi *spi_bus, rt_uint8_t *tx, rt_uint8_t *rx, int qspi_lines)
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{
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uint32_t idx = spi_bus->idx;
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if (qspi_lines > 1)
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{
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if (tx)
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{
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switch (qspi_lines)
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{
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case 2:
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spiIoctl(idx, SPI_IOC_SET_DUAL_QUAD_MODE, SPI_DUAL_MODE, 0);
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break;
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case 4:
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spiIoctl(idx, SPI_IOC_SET_DUAL_QUAD_MODE, SPI_QUAD_MODE, 0);
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break;
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default:
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LOG_E("Data line is not supported.\n");
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return -1;
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}
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spiIoctl(idx, SPI_IOC_SET_DUAL_QUAD_DIR, SPI_DUAL_QUAD_OUTPUT, 0);
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}
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else if (rx)
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{
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switch (qspi_lines)
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{
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case 2:
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spiIoctl(idx, SPI_IOC_SET_DUAL_QUAD_MODE, SPI_DUAL_MODE, 0);
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break;
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case 4:
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spiIoctl(idx, SPI_IOC_SET_DUAL_QUAD_MODE, SPI_QUAD_MODE, 0);
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break;
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default:
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LOG_E("Data line is not supported.\n");
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return -1;
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}
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spiIoctl(idx, SPI_IOC_SET_DUAL_QUAD_DIR, SPI_DUAL_QUAD_INPUT, 0);
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}
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}
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else
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{
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spiIoctl(idx, SPI_IOC_SET_DUAL_QUAD_MODE, SPI_DISABLE_DUAL_QUAD, 0);
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}
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return qspi_lines;
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}
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static rt_uint32_t nu_qspi_bus_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
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{
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struct nu_qspi *spi_bus;
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struct rt_qspi_configuration *qspi_configuration;
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struct rt_qspi_message *qspi_message;
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rt_uint8_t u8last = 1;
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rt_uint8_t bytes_per_word;
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uint32_t idx;
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rt_uint32_t u32len = 0;
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RT_ASSERT(device != RT_NULL);
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RT_ASSERT(message != RT_NULL);
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spi_bus = (struct nu_qspi *) device->bus;
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idx = spi_bus->idx;
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qspi_configuration = &spi_bus->configuration;
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bytes_per_word = qspi_configuration->parent.data_width / 8;
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if (message->cs_take && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
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|
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{
|
||
|
|
/* /CS: active */
|
||
|
|
/* We just use CS0 only. if you need CS1, please use pin controlling before sending message. */
|
||
|
|
spiIoctl(idx, SPI_IOC_ENABLE_SS, SPI_SS_SS0, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
qspi_message = (struct rt_qspi_message *)message;
|
||
|
|
|
||
|
|
/* Command + Address + Dummy + Data */
|
||
|
|
/* Command stage */
|
||
|
|
if (qspi_message->instruction.content != 0)
|
||
|
|
{
|
||
|
|
u8last = nu_qspi_mode_config(spi_bus, (rt_uint8_t *) &qspi_message->instruction.content, RT_NULL, qspi_message->instruction.qspi_lines);
|
||
|
|
nu_qspi_transfer((struct nu_qspi *)spi_bus,
|
||
|
|
(rt_uint8_t *) &qspi_message->instruction.content,
|
||
|
|
RT_NULL,
|
||
|
|
1,
|
||
|
|
1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Address stage */
|
||
|
|
if (qspi_message->address.size > 0)
|
||
|
|
{
|
||
|
|
rt_uint32_t u32ReversedAddr = 0;
|
||
|
|
rt_uint32_t u32AddrNumOfByte = qspi_message->address.size / 8;
|
||
|
|
switch (u32AddrNumOfByte)
|
||
|
|
{
|
||
|
|
case 1:
|
||
|
|
u32ReversedAddr = (qspi_message->address.content & 0xff);
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
nu_set16_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
nu_set24_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
nu_set32_be((rt_uint8_t *)&u32ReversedAddr, qspi_message->address.content);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
RT_ASSERT(0);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
u8last = nu_qspi_mode_config(spi_bus, (rt_uint8_t *)&u32ReversedAddr, RT_NULL, qspi_message->address.qspi_lines);
|
||
|
|
nu_qspi_transfer((struct nu_qspi *)spi_bus,
|
||
|
|
(rt_uint8_t *) &u32ReversedAddr,
|
||
|
|
RT_NULL,
|
||
|
|
u32AddrNumOfByte,
|
||
|
|
1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* alternate_bytes stage */
|
||
|
|
if ((qspi_message->alternate_bytes.size > 0) && (qspi_message->alternate_bytes.size <= 4))
|
||
|
|
{
|
||
|
|
rt_uint32_t u32AlternateByte = 0;
|
||
|
|
rt_uint32_t u32NumOfByte = qspi_message->alternate_bytes.size / 8;
|
||
|
|
switch (u32NumOfByte)
|
||
|
|
{
|
||
|
|
case 1:
|
||
|
|
u32AlternateByte = (qspi_message->alternate_bytes.content & 0xff);
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
nu_set16_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content);
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
nu_set24_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content);
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
nu_set32_be((rt_uint8_t *)&u32AlternateByte, qspi_message->alternate_bytes.content);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
RT_ASSERT(0);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
u8last = nu_qspi_mode_config(spi_bus, (rt_uint8_t *)&u32AlternateByte, RT_NULL, qspi_message->alternate_bytes.qspi_lines);
|
||
|
|
nu_qspi_transfer((struct nu_qspi *)spi_bus,
|
||
|
|
(rt_uint8_t *) &u32AlternateByte,
|
||
|
|
RT_NULL,
|
||
|
|
u32NumOfByte,
|
||
|
|
1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Dummy_cycles stage */
|
||
|
|
if (qspi_message->dummy_cycles > 0)
|
||
|
|
{
|
||
|
|
spi_bus->dummy = 0x00;
|
||
|
|
|
||
|
|
u8last = nu_qspi_mode_config(spi_bus, (rt_uint8_t *) &spi_bus->dummy, RT_NULL, u8last);
|
||
|
|
nu_qspi_transfer((struct nu_qspi *)spi_bus,
|
||
|
|
(rt_uint8_t *) &spi_bus->dummy,
|
||
|
|
RT_NULL,
|
||
|
|
qspi_message->dummy_cycles / (8 / u8last),
|
||
|
|
1);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (message->length > 0)
|
||
|
|
{
|
||
|
|
/* Data stage */
|
||
|
|
nu_qspi_mode_config(spi_bus, (rt_uint8_t *) message->send_buf, (rt_uint8_t *) message->recv_buf, qspi_message->qspi_data_lines);
|
||
|
|
nu_qspi_transfer((struct nu_qspi *)spi_bus,
|
||
|
|
(rt_uint8_t *) message->send_buf,
|
||
|
|
(rt_uint8_t *) message->recv_buf,
|
||
|
|
message->length,
|
||
|
|
bytes_per_word);
|
||
|
|
u32len = message->length;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
u32len = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (message->cs_release && !(qspi_configuration->parent.mode & RT_SPI_NO_CS))
|
||
|
|
{
|
||
|
|
/* /CS: deactive */
|
||
|
|
/* We just use CS0 only. if you need CS1, please use pin controlling before sending message. */
|
||
|
|
spiIoctl(idx, SPI_IOC_DISABLE_SS, SPI_SS_SS0, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
return u32len;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int nu_qspi_register_bus(struct nu_qspi *spi_bus, const char *name)
|
||
|
|
{
|
||
|
|
return rt_qspi_bus_register(&spi_bus->dev, name, &nu_qspi_poll_ops);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Hardware SPI Initial
|
||
|
|
*/
|
||
|
|
static int rt_hw_qspi_init(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for (i = (QSPI_START + 1); i < QSPI_CNT; i++)
|
||
|
|
{
|
||
|
|
nu_sys_ipclk_enable(nu_qspi_arr[i].clkidx);
|
||
|
|
|
||
|
|
nu_sys_ip_reset(nu_qspi_arr[i].rstidx);
|
||
|
|
|
||
|
|
spiOpen(nu_qspi_arr[i].idx);
|
||
|
|
|
||
|
|
nu_qspi_register_bus(&nu_qspi_arr[i], nu_qspi_arr[i].name);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
INIT_DEVICE_EXPORT(rt_hw_qspi_init);
|
||
|
|
|
||
|
|
rt_err_t nu_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
|
||
|
|
{
|
||
|
|
struct rt_qspi_device *qspi_device = RT_NULL;
|
||
|
|
rt_err_t result = RT_EOK;
|
||
|
|
|
||
|
|
RT_ASSERT(bus_name != RT_NULL);
|
||
|
|
RT_ASSERT(device_name != RT_NULL);
|
||
|
|
RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
|
||
|
|
|
||
|
|
qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
|
||
|
|
if (qspi_device == RT_NULL)
|
||
|
|
{
|
||
|
|
LOG_E("no memory, qspi bus attach device failed!\n");
|
||
|
|
result = -RT_ENOMEM;
|
||
|
|
goto __exit;
|
||
|
|
}
|
||
|
|
|
||
|
|
qspi_device->enter_qspi_mode = enter_qspi_mode;
|
||
|
|
qspi_device->exit_qspi_mode = exit_qspi_mode;
|
||
|
|
qspi_device->config.qspi_dl_width = data_line_width;
|
||
|
|
|
||
|
|
result = rt_spi_bus_attach_device(&qspi_device->parent, device_name, bus_name, RT_NULL);
|
||
|
|
|
||
|
|
__exit:
|
||
|
|
if (result != RT_EOK)
|
||
|
|
{
|
||
|
|
if (qspi_device)
|
||
|
|
{
|
||
|
|
rt_free(qspi_device);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif //#if defined(BSP_USING_SPI)
|