2013-01-08 21:05:02 +08:00
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#ifndef __JZ47XX_H__
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#define __JZ47XX_H__
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#include "../common/mipsregs.h"
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#define __REG8(addr) *((volatile unsigned char *)(addr))
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#define __REG16(addr) *((volatile unsigned short *)(addr))
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#define __REG32(addr) *((volatile unsigned int *)(addr))
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#define HARB_BASE 0xB3000000
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#define EMC_BASE 0xB3010000
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#define DMAC_BASE 0xB3020000
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#define UHC_BASE 0xB3030000
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#define UDC_BASE 0xB3040000
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#define LCD_BASE 0xB3050000
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#define CIM_BASE 0xB3060000
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#define ETH_BASE 0xB3100000
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#define NBM_BASE 0xB3F00000
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#define CPM_BASE 0xB0000000
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#define INTC_BASE 0xB0001000
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#define TCU_BASE 0xB0002000
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#define RTC_BASE 0xB0003000
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#define GPIO_BASE 0xB0010000
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#define AIC_BASE 0xB0020000
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#define MSC_BASE 0xB0021000
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#define UART0_BASE 0xB0030000
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#define UART1_BASE 0xB0031000
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#define UART2_BASE 0xB0032000
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#define UART3_BASE 0xB0033000
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#define FIR_BASE 0xB0040000
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#define SCC_BASE 0xB0041000
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#define SCC0_BASE 0xB0041000
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#define I2C_BASE 0xB0042000
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#define SSI_BASE 0xB0043000
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#define SCC1_BASE 0xB0044000
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#define PWM0_BASE 0xB0050000
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#define PWM1_BASE 0xB0051000
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#define DES_BASE 0xB0060000
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#define UPRT_BASE 0xB0061000
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#define KBC_BASE 0xB0062000
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/* CPM Register */
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#define CPM_CPCCR __REG32(CPM_BASE + 0x00) /* Clock Control Register */
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#define CPM_LCR __REG32(CPM_BASE + 0x04) /* Low Power Control Register */
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#define CPM_RSR __REG32(CPM_BASE + 0x08) /* Reset Status Register */
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#define CPM_CPPCR __REG32(CPM_BASE + 0x10) /* PLL Control Register */
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#define CPM_CPPSR __REG32(CPM_BASE + 0x14) /* PLL Switch and Status Register */
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#define CPM_CLKGR __REG32(CPM_BASE + 0x20) /* Clock Gate Register */
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#define CPM_OPCR __REG32(CPM_BASE + 0x24) /* Osillator and Power Control Register */
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#define CPM_I2SCDR __REG32(CPM_BASE + 0x60) /* I2S Device Clock Divider Register */
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#define CPM_LPCDR __REG32(CPM_BASE + 0x64) /* LCD Pixel Clock Divider Register */
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#define CPM_MSCCDR __REG32(CPM_BASE + 0x68) /* MSC Clock Divider Register */
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#define CPM_SSICDR __REG32(CPM_BASE + 0x74) /* SSI Clock Divider Register */
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#define CPM_CIMCDR __REG32(CPM_BASE + 0x7C) /* CIM MCLK Clock Divider Register */
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/* Interrupt Controller Regester */
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#define INTC_ISR __REG32(INTC_BASE + 0x00)
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#define INTC_IMR __REG32(INTC_BASE + 0x04)
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#define INTC_IMSR __REG32(INTC_BASE + 0x08)
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#define INTC_IMCR __REG32(INTC_BASE + 0x0c)
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#define INTC_IPR __REG32(INTC_BASE + 0x10)
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/* TCU Register */
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#define TCU_TSTR __REG32(TCU_BASE + 0xF0)
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#define TCU_TSTSR __REG32(TCU_BASE + 0xF4)
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#define TCU_TSTCR __REG32(TCU_BASE + 0xF8)
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#define TCU_TSR __REG32(TCU_BASE + 0x1C)
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#define TCU_TSSR __REG32(TCU_BASE + 0x2C)
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#define TCU_TSCR __REG32(TCU_BASE + 0x3C)
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#define TCU_TER __REG32(TCU_BASE + 0x10)
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#define TCU_TESR __REG32(TCU_BASE + 0x14)
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#define TCU_TECR __REG32(TCU_BASE + 0x18)
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#define TCU_TFR __REG32(TCU_BASE + 0x20)
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#define TCU_TFSR __REG32(TCU_BASE + 0x24)
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#define TCU_TFCR __REG32(TCU_BASE + 0x28)
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#define TCU_TMR __REG32(TCU_BASE + 0x30)
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#define TCU_TMSR __REG32(TCU_BASE + 0x34)
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#define TCU_TMCR __REG32(TCU_BASE + 0x38)
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#define TCU_TDFR0_OFFSET 0x40
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#define TCU_TDFR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TDFR0_OFFSET)
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#define TCU_TDHR0_OFFSET 0x44
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#define TCU_TDHR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TDHR0_OFFSET)
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#define TCU_TCNT0_OFFSET 0x48
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#define TCU_TCNT(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TCNT0_OFFSET)
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#define TCU_TCSR0_OFFSET 0x4C
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#define TCU_TCSR(x) __REG16(TCU_BASE + (x) * 0x10 + TCU_TCSR0_OFFSET)
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/* TCU Register Definitions */
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#define TCU_TCSR_PWM_SD (1 << 9)
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#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
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#define TCU_TCSR_PWM_EN (1 << 7)
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#define TCU_TCSR_PRESCALE_BIT 3
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#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
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#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
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#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
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#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
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#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
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#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
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#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
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#define TCU_TCSR_EXT_EN (1 << 2)
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#define TCU_TCSR_RTC_EN (1 << 1)
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#define TCU_TCSR_PCK_EN (1 << 0)
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#define TCU_TER_OSTEN (1 << 15)
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#define TCU_TER_TCEN5 (1 << 5)
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#define TCU_TER_TCEN4 (1 << 4)
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#define TCU_TER_TCEN3 (1 << 3)
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#define TCU_TER_TCEN2 (1 << 2)
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#define TCU_TER_TCEN1 (1 << 1)
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#define TCU_TER_TCEN0 (1 << 0)
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#define TCU_TESR_OSTST (1 << 15)
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#define TCU_TESR_TCST5 (1 << 5)
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#define TCU_TESR_TCST4 (1 << 4)
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#define TCU_TESR_TCST3 (1 << 3)
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#define TCU_TESR_TCST2 (1 << 2)
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#define TCU_TESR_TCST1 (1 << 1)
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#define TCU_TESR_TCST0 (1 << 0)
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#define TCU_TECR_OSTCL (1 << 15)
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#define TCU_TECR_TCCL5 (1 << 5)
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#define TCU_TECR_TCCL4 (1 << 4)
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#define TCU_TECR_TCCL3 (1 << 3)
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#define TCU_TECR_TCCL2 (1 << 2)
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#define TCU_TECR_TCCL1 (1 << 1)
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#define TCU_TECR_TCCL0 (1 << 0)
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#define TCU_TFR_HFLAG5 (1 << 21)
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#define TCU_TFR_HFLAG4 (1 << 20)
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#define TCU_TFR_HFLAG3 (1 << 19)
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#define TCU_TFR_HFLAG2 (1 << 18)
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#define TCU_TFR_HFLAG1 (1 << 17)
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#define TCU_TFR_HFLAG0 (1 << 16)
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#define TCU_TFR_FFLAG5 (1 << 5)
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#define TCU_TFR_FFLAG4 (1 << 4)
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#define TCU_TFR_FFLAG3 (1 << 3)
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#define TCU_TFR_FFLAG2 (1 << 2)
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#define TCU_TFR_FFLAG1 (1 << 1)
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#define TCU_TFR_FFLAG0 (1 << 0)
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#define TCU_TFSR_HFLAG5 (1 << 21)
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#define TCU_TFSR_HFLAG4 (1 << 20)
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#define TCU_TFSR_HFLAG3 (1 << 19)
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#define TCU_TFSR_HFLAG2 (1 << 18)
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#define TCU_TFSR_HFLAG1 (1 << 17)
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#define TCU_TFSR_HFLAG0 (1 << 16)
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#define TCU_TFSR_OSTFLAG (1 << 15)
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#define TCU_TFSR_FFLAG5 (1 << 5)
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#define TCU_TFSR_FFLAG4 (1 << 4)
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#define TCU_TFSR_FFLAG3 (1 << 3)
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#define TCU_TFSR_FFLAG2 (1 << 2)
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#define TCU_TFSR_FFLAG1 (1 << 1)
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#define TCU_TFSR_FFLAG0 (1 << 0)
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#define TCU_TFCR_HFLAG5 (1 << 21)
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#define TCU_TFCR_HFLAG4 (1 << 20)
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#define TCU_TFCR_HFLAG3 (1 << 19)
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#define TCU_TFCR_HFLAG2 (1 << 18)
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#define TCU_TFCR_HFLAG1 (1 << 17)
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#define TCU_TFCR_HFLAG0 (1 << 16)
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#define TCU_TFCR_OSTFLAG (1 << 15)
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#define TCU_TFCR_FFLAG5 (1 << 5)
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#define TCU_TFCR_FFLAG4 (1 << 4)
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#define TCU_TFCR_FFLAG3 (1 << 3)
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#define TCU_TFCR_FFLAG2 (1 << 2)
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#define TCU_TFCR_FFLAG1 (1 << 1)
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#define TCU_TFCR_FFLAG0 (1 << 0)
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#define TCU_TMR_HMASK5 (1 << 21)
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#define TCU_TMR_HMASK4 (1 << 20)
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#define TCU_TMR_HMASK3 (1 << 19)
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#define TCU_TMR_HMASK2 (1 << 18)
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#define TCU_TMR_HMASK1 (1 << 17)
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#define TCU_TMR_HMASK0 (1 << 16)
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#define TCU_TMR_OSTMASK (1 << 15)
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#define TCU_TMR_FMASK5 (1 << 5)
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#define TCU_TMR_FMASK4 (1 << 4)
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#define TCU_TMR_FMASK3 (1 << 3)
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#define TCU_TMR_FMASK2 (1 << 2)
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#define TCU_TMR_FMASK1 (1 << 1)
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#define TCU_TMR_FMASK0 (1 << 0)
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#define TCU_TMSR_HMST5 (1 << 21)
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#define TCU_TMSR_HMST4 (1 << 20)
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#define TCU_TMSR_HMST3 (1 << 19)
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#define TCU_TMSR_HMST2 (1 << 18)
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#define TCU_TMSR_HMST1 (1 << 17)
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#define TCU_TMSR_HMST0 (1 << 16)
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#define TCU_TMSR_OSTMST (1 << 15)
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#define TCU_TMSR_FMST5 (1 << 5)
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#define TCU_TMSR_FMST4 (1 << 4)
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#define TCU_TMSR_FMST3 (1 << 3)
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#define TCU_TMSR_FMST2 (1 << 2)
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#define TCU_TMSR_FMST1 (1 << 1)
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#define TCU_TMSR_FMST0 (1 << 0)
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#define TCU_TMCR_HMCL5 (1 << 21)
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#define TCU_TMCR_HMCL4 (1 << 20)
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#define TCU_TMCR_HMCL3 (1 << 19)
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#define TCU_TMCR_HMCL2 (1 << 18)
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#define TCU_TMCR_HMCL1 (1 << 17)
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#define TCU_TMCR_HMCL0 (1 << 16)
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#define TCU_TMCR_OSTMCL (1 << 15)
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#define TCU_TMCR_FMCL5 (1 << 5)
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#define TCU_TMCR_FMCL4 (1 << 4)
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#define TCU_TMCR_FMCL3 (1 << 3)
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#define TCU_TMCR_FMCL2 (1 << 2)
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#define TCU_TMCR_FMCL1 (1 << 1)
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#define TCU_TMCR_FMCL0 (1 << 0)
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#define TCU_TSR_WDTS (1 << 16)
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#define TCU_TSR_STOP5 (1 << 5)
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#define TCU_TSR_STOP4 (1 << 4)
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#define TCU_TSR_STOP3 (1 << 3)
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#define TCU_TSR_STOP2 (1 << 2)
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#define TCU_TSR_STOP1 (1 << 1)
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#define TCU_TSR_STOP0 (1 << 0)
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#define TCU_TSSR_WDTSS (1 << 16)
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#define TCU_TSSR_STPS5 (1 << 5)
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#define TCU_TSSR_STPS4 (1 << 4)
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#define TCU_TSSR_STPS3 (1 << 3)
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#define TCU_TSSR_STPS2 (1 << 2)
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#define TCU_TSSR_STPS1 (1 << 1)
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#define TCU_TSSR_STPS0 (1 << 0)
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#define TCU_TSSR_WDTSC (1 << 16)
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#define TCU_TSSR_STPC5 (1 << 5)
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#define TCU_TSSR_STPC4 (1 << 4)
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#define TCU_TSSR_STPC3 (1 << 3)
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#define TCU_TSSR_STPC2 (1 << 2)
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#define TCU_TSSR_STPC1 (1 << 1)
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#define TCU_TSSR_STPC0 (1 << 0)
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#define OST_TCSR_CNT_MD ( 1 << 15 )
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#define OST_TCSR_PWM_SHUT_ABRUPT ( 1 << 9 )
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#define OST_TCSR_PRESCALE1 ( 0x0 << 3)
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#define OST_TCSR_PRESCALE4 ( 0x1 << 3)
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#define OST_TCSR_PRESCALE16 ( 0x2 << 3)
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#define OST_TCSR_PRESCALE64 ( 0x3 << 3)
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#define OST_TCSR_PRESCALE256 ( 0x4 << 3)
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#define OST_TCSR_PRESCALE1024 ( 0x5 << 3)
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/* Uart Register */
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#define UART_RDR(base) __REG8((base) + 0x00) /* R 8b H'xx */
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#define UART_TDR(base) __REG8((base) + 0x00) /* W 8b H'xx */
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#define UART_DLLR(base) __REG8((base) + 0x00) /* RW 8b H'00 */
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#define UART_DLHR(base) __REG8((base) + 0x04) /* RW 8b H'00 */
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#define UART_IER(base) __REG8((base) + 0x04) /* RW 8b H'00 */
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#define UART_ISR(base) __REG8((base) + 0x08) /* R 8b H'01 */
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#define UART_FCR(base) __REG8((base) + 0x08) /* W 8b H'00 */
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#define UART_LCR(base) __REG8((base) + 0x0C) /* RW 8b H'00 */
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#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
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#define UART_LSR(base) __REG8((base) + 0x14) /* R 8b H'00 */
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#define UART_MSR(base) __REG8((base) + 0x18) /* R 8b H'00 */
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#define UART_SPR(base) __REG8((base) + 0x1C) /* RW 8b H'00 */
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#define UART_MCR(base) __REG8((base) + 0x10) /* RW 8b H'00 */
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#define UART_SIRCR(base) __REG8((base) + 0x20) /* RW 8b H'00 */
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#define SYSTEM_STACK 0x80003fe8 /* the kernel system stack address */
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#endif
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