469 lines
16 KiB
C
469 lines
16 KiB
C
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/*
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* @brief LPC8xx clock driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#define _CHIP_COMMON_
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#include "chip.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/* Inprecise clock rates for the watchdog oscillator */
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static const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
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0, /* WDT_OSC_ILLEGAL */
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600000, /* WDT_OSC_0_60 */
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1050000, /* WDT_OSC_1_05 */
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1400000, /* WDT_OSC_1_40 */
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1750000, /* WDT_OSC_1_75 */
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2100000, /* WDT_OSC_2_10 */
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2400000, /* WDT_OSC_2_40 */
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2700000, /* WDT_OSC_2_70 */
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3000000, /* WDT_OSC_3_00 */
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3250000, /* WDT_OSC_3_25 */
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3500000, /* WDT_OSC_3_50 */
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3750000, /* WDT_OSC_3_75 */
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4000000, /* WDT_OSC_4_00 */
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4200000, /* WDT_OSC_4_20 */
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4400000, /* WDT_OSC_4_40 */
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4600000 /* WDT_OSC_4_60 */
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};
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typedef struct {
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uint16_t freq_main; // main clock frequency in MHz
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uint16_t freq_sys; // system (CPU) clock frequency in MHz
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uint16_t freq_fcco; // FCCO clock frequency in MHz
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uint16_t msel; // MSEL (pre-decremented)
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uint16_t psel; // PSEL (pre-decremented)
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uint16_t divider; // SYSAHBCLKDIV
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} LPC_8XX_PLL_T;
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/*
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* This table contains all useful PLL configurations
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* for "integer" MHZ (e.g. 1MHz, 2MHz, etc.) frequencies.
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*
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* This table has two inputs:
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* - freq_main: This is the main frequency.
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* - freq_sys: This is the system (CPU) frequency.
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* These are used to select which table entry to use.
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*
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* There are many ways to get some frequencies. For example,
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* there are eight ways to make the CPU run at 12MHZ. If the peripheral bus
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* needs to run very fast, it's possible to set the main clock
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* up to 96MHz. If low power is a requirement, it's possible to set the main
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* clock to 12MHz.
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*
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* All the rest of the table entries are outputs.
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* - freq_fcco is simply an FYI value. It is not used for programming.
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* - MSEL / PSEL / divider are used to program the PLL.
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*/
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static const LPC_8XX_PLL_T config_tab[] = {
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{ 12, 12, 192, 0, 3, 1 }, // 12.0000MHz
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{ 12, 6, 192, 0, 3, 2 }, // 6.0000MHz
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{ 12, 4, 192, 0, 3, 3 }, // 4.0000MHz
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{ 12, 3, 192, 0, 3, 4 }, // 3.0000MHz
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{ 12, 2, 192, 0, 3, 6 }, // 2.0000MHz
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{ 12, 1, 192, 0, 3, 12 }, // 1.0000MHz
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{ 24, 24, 192, 1, 2, 1 }, // 24.0000MHz
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{ 24, 12, 192, 1, 2, 2 }, // 12.0000MHz
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{ 24, 8, 192, 1, 2, 3 }, // 8.0000MHz
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{ 24, 6, 192, 1, 2, 4 }, // 6.0000MHz
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{ 24, 4, 192, 1, 2, 6 }, // 4.0000MHz
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{ 24, 3, 192, 1, 2, 8 }, // 3.0000MHz
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{ 24, 2, 192, 1, 2, 12 }, // 2.0000MHz
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{ 24, 1, 192, 1, 2, 24 }, // 1.0000MHz
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{ 36, 18, 288, 2, 2, 2 }, // 18.0000MHz
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{ 36, 12, 288, 2, 2, 3 }, // 12.0000MHz
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{ 36, 9, 288, 2, 2, 4 }, // 9.0000MHz
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{ 36, 6, 288, 2, 2, 6 }, // 6.0000MHz
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{ 36, 4, 288, 2, 2, 9 }, // 4.0000MHz
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{ 36, 3, 288, 2, 2, 12 }, // 3.0000MHz
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{ 36, 2, 288, 2, 2, 18 }, // 2.0000MHz
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{ 36, 1, 288, 2, 2, 36 }, // 1.0000MHz
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{ 48, 24, 192, 3, 1, 2 }, // 24.0000MHz
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{ 48, 16, 192, 3, 1, 3 }, // 16.0000MHz
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{ 48, 12, 192, 3, 1, 4 }, // 12.0000MHz
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{ 48, 8, 192, 3, 1, 6 }, // 8.0000MHz
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{ 48, 6, 192, 3, 1, 8 }, // 6.0000MHz
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{ 48, 4, 192, 3, 1, 12 }, // 4.0000MHz
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{ 48, 3, 192, 3, 1, 16 }, // 3.0000MHz
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{ 48, 2, 192, 3, 1, 24 }, // 2.0000MHz
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{ 48, 1, 192, 3, 1, 48 }, // 1.0000MHz
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{ 60, 30, 240, 4, 1, 2 }, // 30.0000MHz
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{ 60, 20, 240, 4, 1, 3 }, // 20.0000MHz
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{ 60, 15, 240, 4, 1, 4 }, // 15.0000MHz
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{ 60, 12, 240, 4, 1, 5 }, // 12.0000MHz
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{ 60, 10, 240, 4, 1, 6 }, // 10.0000MHz
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{ 60, 6, 240, 4, 1, 10 }, // 6.0000MHz
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{ 60, 5, 240, 4, 1, 12 }, // 5.0000MHz
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{ 60, 4, 240, 4, 1, 15 }, // 4.0000MHz
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{ 60, 3, 240, 4, 1, 20 }, // 3.0000MHz
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{ 60, 2, 240, 4, 1, 30 }, // 2.0000MHz
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{ 60, 1, 240, 4, 1, 60 }, // 1.0000MHz
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{ 72, 24, 288, 5, 1, 3 }, // 24.0000MHz
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{ 72, 18, 288, 5, 1, 4 }, // 18.0000MHz
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{ 72, 12, 288, 5, 1, 6 }, // 12.0000MHz
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{ 72, 9, 288, 5, 1, 8 }, // 9.0000MHz
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{ 72, 8, 288, 5, 1, 9 }, // 8.0000MHz
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{ 72, 6, 288, 5, 1, 12 }, // 6.0000MHz
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{ 72, 4, 288, 5, 1, 18 }, // 4.0000MHz
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{ 72, 3, 288, 5, 1, 24 }, // 3.0000MHz
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{ 72, 2, 288, 5, 1, 36 }, // 2.0000MHz
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{ 72, 1, 288, 5, 1, 72 }, // 1.0000MHz
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{ 84, 28, 168, 6, 0, 3 }, // 28.0000MHz
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{ 84, 21, 168, 6, 0, 4 }, // 21.0000MHz
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{ 84, 14, 168, 6, 0, 6 }, // 14.0000MHz
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{ 84, 12, 168, 6, 0, 7 }, // 12.0000MHz
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{ 84, 7, 168, 6, 0, 12 }, // 7.0000MHz
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{ 84, 6, 168, 6, 0, 14 }, // 6.0000MHz
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{ 84, 4, 168, 6, 0, 21 }, // 4.0000MHz
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{ 84, 3, 168, 6, 0, 28 }, // 3.0000MHz
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{ 84, 2, 168, 6, 0, 42 }, // 2.0000MHz
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{ 84, 1, 168, 6, 0, 84 }, // 1.0000MHz
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{ 96, 24, 192, 7, 0, 4 }, // 24.0000MHz
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{ 96, 16, 192, 7, 0, 6 }, // 16.0000MHz
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{ 96, 12, 192, 7, 0, 8 }, // 12.0000MHz
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{ 96, 8, 192, 7, 0, 12 }, // 8.0000MHz
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{ 96, 6, 192, 7, 0, 16 }, // 6.0000MHz
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{ 96, 4, 192, 7, 0, 24 }, // 4.0000MHz
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{ 96, 3, 192, 7, 0, 32 }, // 3.0000MHz
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{ 96, 2, 192, 7, 0, 48 }, // 2.0000MHz
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{ 96, 1, 192, 7, 0, 96 }, // 1.0000MHz
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};
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static const uint16_t config_tab_ct = sizeof(config_tab) / sizeof(LPC_8XX_PLL_T);
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static uint16_t config_tab_idx = 0;
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/* System Clock Frequency (Core Clock) */
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uint32_t SystemCoreClock;
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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static void pll_config(const LPC_8XX_PLL_T* pll_cfg)
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{
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Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_IRC_PD); /* turn on the IRC by clearing the power down bit */
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Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC); /* select PLL input to be IRC */
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Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_IRC);
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Chip_FMC_SetFLASHAccess(FLASHTIM_30MHZ_CPU); /* setup FLASH access to 2 clocks (up to 30MHz) */
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Chip_SYSCTL_PowerDown(SYSCTL_SLPWAKE_SYSPLL_PD); /* power down PLL to change the PLL divider ratio */
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Chip_Clock_SetupSystemPLL(pll_cfg->msel, pll_cfg->psel); /* configure the PLL */
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Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_SYSPLL_PD); /* turn on the PLL by clearing the power down bit */
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while (!Chip_Clock_IsSystemPLLLocked()) {} /* wait for PLL to lock */
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Chip_Clock_SetSysClockDiv(pll_cfg->divider); /* load the divider */
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Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT); /* enable the new Frequency */
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}
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/* Compute a WDT or LFO rate */
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static uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
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{
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uint32_t div;
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CHIP_WDTLFO_OSC_T clk;
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/* Get WDT oscillator settings */
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clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
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div = reg & 0x1F;
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/* Compute clock rate and divided by divde value */
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return wdtOSCRate[clk] / ((div + 1) << 1);
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}
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/* Compute PLL frequency */
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static uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
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{
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uint32_t m_val = ((PLLReg & 0x1F) + 1);
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return (inputRate * m_val);
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}
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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bool Chip_IRC_SetFreq(uint32_t main, uint32_t sys)
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{
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uint16_t freq_m = main/1000000; /* main frequency in MHz */
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uint16_t freq_s = sys/1000000; /* system frequency in MHz */
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bool found = false; /* frequencies found */
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uint32_t i = 0;
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if (freq_s > 30) /* if system frequency is higher than 30MHz... */
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return false; /* ...don't attempt to set it */
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if (freq_m > 96) /* if main frequency is higher than 96MHz... */
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return false; /* ...don't attempt to set it */
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for (i=0; i<config_tab_ct; i++) { /* loop through table */
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if ((freq_m == config_tab[i].freq_main) && (freq_s == config_tab[i].freq_sys)) { /* attempt to find a match */
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config_tab_idx = i; /* save the data for later */
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found = true; /* set state to found */
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break; /* go config the PLL */
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}
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}
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if (found == true) { /* if a match has been found */
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pll_config(&config_tab[config_tab_idx]); /* configure the PLL */
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}
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return found; /* return operation status */
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}
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// Open this API only if ROM headers are included
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#ifdef LPC_PWRD_API
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void Chip_IRC_SetFreq_ROM(uint32_t sys)
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{
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uint32_t cmd[4], resp[2];
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Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_IRC_PD); /* Turn on the IRC by clearing the power down bit */
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Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC); /* Select PLL input to be IRC */
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Chip_FMC_SetFLASHAccess(FLASHTIM_30MHZ_CPU); /* Setup FLASH access to 2 clocks (up to 30MHz) */
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cmd[0] = Chip_Clock_GetIntOscRate() / 1000; /* in KHz */
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cmd[1] = sys / 1000; /* system clock rate in kHz */
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cmd[2] = CPU_FREQ_EQU;
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cmd[3] = sys / 10000; /* Timeout. See UM10601, section 23.4.1.3 for details */
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LPC_PWRD_API->set_pll(cmd, resp); /* Attempt to set the PLL */
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while (resp[0] != PLL_CMD_SUCCESS) {} /* Dead loop on fail */
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}
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#else
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#endif
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/* Update system core clock rate, should be called if the system has
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a clock rate change */
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void SystemCoreClockUpdate(void)
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{
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/* CPU core speed */
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SystemCoreClock = Chip_Clock_GetSystemClockRate();
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}
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/* Set System PLL clock source */
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void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
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{
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LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
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/* sequnce a 0 followed by 1 to update PLL source selection */
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LPC_SYSCTL->SYSPLLCLKUEN = 0;
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LPC_SYSCTL->SYSPLLCLKUEN = 1;
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}
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/* Bypass System Oscillator and set oscillator frequency range */
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void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
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{
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uint32_t ctrl = 0;
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if (bypass) {
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ctrl |= (1 << 0);
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}
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if (highfr) {
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ctrl |= (1 << 1);
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}
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LPC_SYSCTL->SYSOSCCTRL = ctrl;
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}
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/* Set main system clock source */
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void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
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{
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LPC_SYSCTL->MAINCLKSEL = (uint32_t) src;
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/* sequnce a 0 followed by 1 to update MAINCLK source selection */
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LPC_SYSCTL->MAINCLKUEN = 0;
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LPC_SYSCTL->MAINCLKUEN = 1;
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}
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/* Set CLKOUT clock source and divider */
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void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
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{
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LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
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/* sequnce a 0 followed by 1 to update CLKOUT source selection */
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LPC_SYSCTL->CLKOUTUEN = 0;
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LPC_SYSCTL->CLKOUTUEN = 1;
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LPC_SYSCTL->CLKOUTDIV = div;
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}
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/* Return estimated watchdog oscillator rate */
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uint32_t Chip_Clock_GetWDTOSCRate(void)
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{
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|
|
return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL & ~SYSCTL_WDTOSCCTRL_RESERVED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return System PLL input clock rate */
|
||
|
|
uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
|
||
|
|
{
|
||
|
|
uint32_t clkRate;
|
||
|
|
|
||
|
|
switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
|
||
|
|
case SYSCTL_PLLCLKSRC_IRC:
|
||
|
|
clkRate = Chip_Clock_GetIntOscRate();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case SYSCTL_PLLCLKSRC_SYSOSC:
|
||
|
|
clkRate = Chip_Clock_GetMainOscRate();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case SYSCTL_PLLCLKSRC_EXT_CLKIN:
|
||
|
|
clkRate = Chip_Clock_GetExtClockInRate();
|
||
|
|
break;
|
||
|
|
|
||
|
|
default:
|
||
|
|
clkRate = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
return clkRate;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return System PLL output clock rate */
|
||
|
|
uint32_t Chip_Clock_GetSystemPLLOutClockRate(void)
|
||
|
|
{
|
||
|
|
return Chip_Clock_GetPLLFreq((LPC_SYSCTL->SYSPLLCTRL & ~SYSCTL_SYSPLLCTRL_RESERVED),
|
||
|
|
Chip_Clock_GetSystemPLLInClockRate());
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return main clock rate */
|
||
|
|
uint32_t Chip_Clock_GetMainClockRate(void)
|
||
|
|
{
|
||
|
|
uint32_t clkRate = 0;
|
||
|
|
|
||
|
|
switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
|
||
|
|
case SYSCTL_MAINCLKSRC_IRC:
|
||
|
|
clkRate = Chip_Clock_GetIntOscRate();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case SYSCTL_MAINCLKSRC_PLLIN:
|
||
|
|
clkRate = Chip_Clock_GetSystemPLLInClockRate();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case SYSCTL_MAINCLKSRC_WDTOSC:
|
||
|
|
clkRate = Chip_Clock_GetWDTOSCRate();
|
||
|
|
break;
|
||
|
|
|
||
|
|
case SYSCTL_MAINCLKSRC_PLLOUT:
|
||
|
|
clkRate = Chip_Clock_GetSystemPLLOutClockRate();
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return clkRate;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Return system clock rate */
|
||
|
|
uint32_t Chip_Clock_GetSystemClockRate(void)
|
||
|
|
{
|
||
|
|
/* No point in checking for divide by 0 */
|
||
|
|
return Chip_Clock_GetMainClockRate() / (LPC_SYSCTL->SYSAHBCLKDIV & ~SYSCTL_SYSAHBCLKDIV_RESERVED);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get USART 0/1/2 UART base rate */
|
||
|
|
uint32_t Chip_Clock_GetUSARTNBaseClockRate(void)
|
||
|
|
{
|
||
|
|
uint64_t inclk;
|
||
|
|
uint32_t div;
|
||
|
|
|
||
|
|
div = (uint32_t) Chip_Clock_GetUARTClockDiv();
|
||
|
|
if (div == 0) {
|
||
|
|
/* Divider is 0 so UART clock is disabled */
|
||
|
|
inclk = 0;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
uint32_t mult, divf;
|
||
|
|
|
||
|
|
/* Input clock into FRG block is the divided main system clock */
|
||
|
|
inclk = (uint64_t) (Chip_Clock_GetMainClockRate() / div);
|
||
|
|
|
||
|
|
divf = Chip_SYSCTL_GetUSARTFRGDivider();
|
||
|
|
if (divf == 0xFF) {
|
||
|
|
/* Fractional part is enabled, get multiplier */
|
||
|
|
mult = (uint32_t) Chip_SYSCTL_GetUSARTFRGMultiplier();
|
||
|
|
|
||
|
|
/* Get fractional error */
|
||
|
|
inclk = (inclk * 256) / (uint64_t) (256 + mult);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return (uint32_t) inclk;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Set USART 0/1/2 UART base rate */
|
||
|
|
uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable)
|
||
|
|
{
|
||
|
|
uint32_t div, inclk;
|
||
|
|
|
||
|
|
/* Input clock into FRG block is the main system clock */
|
||
|
|
inclk = Chip_Clock_GetMainClockRate();
|
||
|
|
|
||
|
|
/* Get integer divider for coarse rate */
|
||
|
|
div = inclk / rate;
|
||
|
|
if (div == 0) {
|
||
|
|
div = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Approximated rate with only integer divider */
|
||
|
|
Chip_Clock_SetUARTClockDiv((uint8_t) div);
|
||
|
|
|
||
|
|
if (fEnable) {
|
||
|
|
uint32_t uart_fra_multiplier;
|
||
|
|
|
||
|
|
/* Reset FRG */
|
||
|
|
Chip_SYSCTL_PeriphReset(RESET_UARTFBRG);
|
||
|
|
|
||
|
|
/* Enable fractional divider */
|
||
|
|
Chip_SYSCTL_SetUSARTFRGDivider(0xFF);
|
||
|
|
|
||
|
|
/* Compute the fractional divisor (the lower byte is the
|
||
|
|
fractional portion) */
|
||
|
|
uart_fra_multiplier = ((inclk / div) * 256) / rate;
|
||
|
|
|
||
|
|
/* ...just the fractional portion (the lower byte) */
|
||
|
|
Chip_SYSCTL_SetUSARTFRGMultiplier((uint8_t) uart_fra_multiplier);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
/* Disable fractional generator and use integer divider only */
|
||
|
|
Chip_SYSCTL_SetUSARTFRGDivider(0);
|
||
|
|
}
|
||
|
|
|
||
|
|
return Chip_Clock_GetUSARTNBaseClockRate();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get the IOCONCLKDIV clock rate */
|
||
|
|
uint32_t Chip_Clock_GetIOCONCLKDIVClockRate(CHIP_PIN_CLKDIV_T reg)
|
||
|
|
{
|
||
|
|
uint32_t div = LPC_SYSCTL->IOCONCLKDIV[reg] & ~SYSCTL_IOCONCLKDIV_RESERVED;
|
||
|
|
uint32_t main_clk = Chip_Clock_GetMainClockRate();
|
||
|
|
|
||
|
|
return (div == 0) ? 0 : (main_clk / div);
|
||
|
|
}
|
||
|
|
|
||
|
|
void Chip_Clock_SetIOCONCLKDIV(CHIP_PIN_CLKDIV_T reg, uint8_t div)
|
||
|
|
{
|
||
|
|
int t_reg = IOCONCLK_MAX-reg;
|
||
|
|
LPC_SYSCTL->IOCONCLKDIV[t_reg] = div;
|
||
|
|
}
|