2023-09-22 13:38:33 +08:00
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/*
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2023-09-22 18:27:20 +08:00
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* Copyright (c) 2006-2023, RT-Thread Development Team
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2023-09-22 13:38:33 +08:00
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Email Notes
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* 2023-09-16 luhuadong luhuadong@163.com First Release
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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// <o> Internal SRAM memory size[Kbytes] <128-256>
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// <i>Default: 256
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#if defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__)
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#define SAME5x_SRAM_SIZE 128
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#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__)
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#define SAME5x_SRAM_SIZE 256
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#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__)
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#define SAME5x_SRAM_SIZE 256
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#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__)
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#define SAME5x_SRAM_SIZE 256
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#elif defined(__SAME54N19A__) || defined(__ATSAME54N19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__)
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#define SAME5x_SRAM_SIZE 256
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#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__)
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#define SAME5x_SRAM_SIZE 256
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#elif defined(__SAME53J18A__) || defined(__ATSAME53J18A__)
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#define SAME5x_SRAM_SIZE 128
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#elif defined(__SAME53J19A__) || defined(__ATSAME53J19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAME53J20A__) || defined(__ATSAME53J20A__)
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#define SAME5x_SRAM_SIZE 256
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#elif defined(__SAME53N19A__) || defined(__ATSAME53N19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAME53N20A__) || defined(__ATSAME53N20A__)
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#define SAME5x_SRAM_SIZE 256
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#elif defined(__SAME51J18A__) || defined(__ATSAME51J18A__)
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#define SAME5x_SRAM_SIZE 128
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#elif defined(__SAME51J19A__) || defined(__ATSAME51J19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAME51J20A__) || defined(__ATSAME51J20A__)
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#define SAME5x_SRAM_SIZE 256
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#elif defined(__SAME51N19A__) || defined(__ATSAME51N19A__)
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#define SAME5x_SRAM_SIZE 192
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#elif defined(__SAME51N20A__) || defined(__ATSAME51N20A__)
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#define SAME5x_SRAM_SIZE 256
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#else
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#error Board does not support the specified device.
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#endif
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#define SAME5x_SRAM_END (0x20000000 + SAME5x_SRAM_SIZE * 1024)
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#if defined(__ARMCC_VERSION)
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extern int Image$$RW_IRAM1$$ZI$$Limit;
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#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit)
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#elif __ICCARM__
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#pragma section="HEAP"
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#define HEAP_BEGIN (__segment_begin("HEAP"))
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#define HEAP_END (__segment_end("HEAP"))
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#else
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extern int __bss_end;
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#define HEAP_BEGIN (&__bss_end)
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#define HEAP_END SAME5x_SRAM_END
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#endif
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#ifdef RT_USING_SERIAL
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#include "hpl_sercom_config.h"
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2023-09-22 18:06:18 +08:00
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#define DEFAULT_USART_BAUD_RATE CONF_SERCOM_2_USART_BAUD_RATE
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2023-09-22 13:38:33 +08:00
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#endif
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void rt_hw_board_init(void);
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#endif
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